Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21553

1

T1

7

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3261

1

T1

11

T2

1

T4

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18823

1

T1

7

T2

2

T3

20

auto[1]

5991

1

T1

11

T4

23

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	36	1			T127	27		T228	9		-	-
values[0]	81	1			T229	1		T82	12		T230	24
values[1]	636	1			T4	23		T12	8		T18	3
values[2]	600	1			T18	2		T231	1		T123	7
values[3]	656	1			T2	1		T11	13		T209	11
values[4]	767	1			T12	12		T20	17		T130	1
values[5]	2739	1			T5	3		T13	28		T17	1
values[6]	614	1			T10	27		T13	4		T209	10
values[7]	467	1			T7	3		T11	9		T12	3
values[8]	785	1			T1	11		T4	9		T136	20
values[9]	1244	1			T1	7		T2	1		T7	27
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	854	1			T4	23		T12	8		T18	3
values[1]	558	1			T11	13		T18	2		T231	1
values[2]	697	1			T2	1		T130	1		T162	1
values[3]	2801	1			T5	3		T12	12		T86	2
values[4]	724	1			T13	28		T17	1		T178	1
values[5]	575	1			T7	3		T10	27		T11	9
values[6]	528	1			T4	9		T136	20		T121	5
values[7]	839	1			T1	11		T7	5		T15	2
values[8]	726	1			T1	7		T2	1		T7	22
values[9]	321	1			T11	4		T209	14		T32	2
minimum	16191	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	5		T18	3		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T4	18		T12	8		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T231	1		T232	1		T125	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	13		T18	2		T205	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	1		T130	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T162	1		T26	7		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T5	3		T86	2		T87	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	12		T209	1		T121	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	14		T178	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	1		T151	5		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	3		T13	4		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	1		T10	14		T11	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T136	11		T121	5		T234	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T4	9		T16	6		T151	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T133	3		T169	1		T235	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	11		T7	3		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	7		T7	12		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T2	1		T17	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T11	4		T32	1		T127	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T209	1		T236	12		T139	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16054	1			T3	20		T6	17		T8	192
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T208	4		T122	12		T237	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	2		T123	6		T125	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T125	11		T73	1		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T205	2		T239	8		T240	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T123	2		T241	8		T126	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T26	8		T199	5		T127	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T87	24		T20	9		T242	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T209	10		T122	9		T243	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	14		T32	21		T244	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T151	2		T127	13		T154	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T181	3		T230	10		T245	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	2		T10	13		T209	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T136	9		T246	2		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T16	2		T151	5		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T133	6		T235	2		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	2		T15	1		T134	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	10		T10	1		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T24	9		T133	7		T124	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T32	1		T127	13		T182	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T209	13		T236	12		T139	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T127	14		T228	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T82	1		T248	1		T249	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T229	1		T230	11		T161	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	5		T18	3		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	18		T12	8		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T231	1		T237	13		T137	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T18	2		T123	1		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T2	1		T241	7		T126	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	13		T209	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T20	8		T130	1		T175	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	12		T122	9		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T5	3		T13	14		T86	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T17	1		T121	10		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	4		T162	1		T32	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	14		T209	1		T131	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	3		T121	5		T246	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	1		T11	9		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T136	11		T16	6		T234	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	11		T4	9		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	7		T7	12		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	395	1			T2	1		T7	3		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T127	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T82	11		T249	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T230	13		T161	2		T250	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T208	4		T122	12		T247	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T15	2		T194	6		T202	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T237	2		T125	11		T73	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T123	6		T125	12		T240	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T241	8		T126	10		T212	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T209	10		T26	8		T205	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T20	9		T175	9		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T122	9		T243	11		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T13	14		T87	24		T242	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T127	13		T154	13		T251	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T32	19		T190	9		T252	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	13		T209	9		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T246	2		T253	11		T79	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T7	2		T148	14		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T136	9		T16	4		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T16	1		T134	9		T123	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	10		T10	1		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T7	2		T15	1		T209	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T4	1		T18	2		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T4	1		T12	1		T130	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T231	1		T232	1		T125	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	1		T18	1		T205	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T2	1		T130	1		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T162	1		T26	13		T199	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1391	1			T5	3		T86	2		T87	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T209	11		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T13	15		T178	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	1		T151	3		T232	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	1		T13	1		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	3		T10	14		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T136	10		T121	1		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	1		T16	6		T151	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T133	7		T169	1		T235	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T1	1		T7	3		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T7	11		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	1		T17	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T11	1		T32	2		T127	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T209	14		T236	13		T139	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16190	1			T3	20		T6	17		T8	192
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	4		T18	1		T208	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	17		T12	7		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T125	2		T254	10		T73	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T11	12		T18	1		T205	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	2		T241	6		T212	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T26	2		T54	1		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T19	20		T20	7		T163	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	11		T121	9		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	13		T32	27		T255	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T151	4		T127	14		T256	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T12	2		T13	3		T257	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	13		T11	8		T131	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T136	10		T121	4		T234	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T4	8		T16	2		T151	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T133	2		T235	3		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	10		T7	2		T258	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	6		T7	11		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	10		T133	7		T255	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T11	3		T127	13		T182	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T236	11		T139	11		T155	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T215	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T127	14		T228	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T82	12		T248	1		T249	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T229	1		T230	14		T161	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	1		T18	2		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	1		T12	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T231	1		T237	3		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T18	1		T123	7		T125	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T2	1		T241	9		T126	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	1		T209	11		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T20	10		T130	1		T175	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T12	1		T122	10		T243	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T5	3		T13	15		T86	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	1		T121	1		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	1		T162	1		T32	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	14		T209	10		T131	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	1		T121	1		T246	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	3		T11	1		T148	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T136	10		T16	6		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	1		T4	1		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T1	1		T7	11		T10	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	445	1			T2	1		T7	3		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T127	13		T228	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T249	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T230	10		T161	4		T250	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T4	4		T18	1		T208	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	17		T12	7		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T237	12		T137	2		T125	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T18	1		T240	8		T155	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T241	6		T212	1		T259	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T11	12		T26	2		T205	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T20	7		T175	7		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	11		T122	8		T140	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T13	13		T19	20		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T121	9		T127	14		T256	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	3		T32	16		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	13		T131	12		T24	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	2		T121	4		T246	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	8		T16	1		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T136	10		T16	4		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	10		T4	8		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	6		T7	11		T11	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T7	2		T24	10		T133	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21601

1

T1

7

T3

20

T4

5

auto[ADC_CTRL_FILTER_COND_OUT]

3213

1

T1

11

T2

2

T4

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19541

1

T2

2

T3

20

T4

14

auto[1]

5273

1

T1

18

T4

18

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T10	2		T260	1		T261	9
values[0]	29	1			T121	5		T262	22		T263	1
values[1]	604	1			T11	13		T12	8		T13	28
values[2]	607	1			T1	7		T2	1		T7	22
values[3]	683	1			T12	12		T17	1		T231	1
values[4]	2729	1			T5	3		T11	9		T17	1
values[5]	508	1			T4	18		T16	10		T123	7
values[6]	686	1			T7	3		T17	1		T18	2
values[7]	877	1			T178	1		T16	3		T32	2
values[8]	599	1			T1	11		T10	27		T13	4
values[9]	1291	1			T2	1		T4	14		T7	5
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	728	1			T7	22		T12	8		T121	15
values[1]	780	1			T1	7		T2	1		T11	13
values[2]	503	1			T12	12		T17	2		T24	20
values[3]	2708	1			T5	3		T11	9		T86	2
values[4]	647	1			T7	3		T178	1		T16	5
values[5]	608	1			T4	18		T17	1		T18	2
values[6]	846	1			T148	15		T32	2		T132	1
values[7]	716	1			T1	11		T10	27		T178	1
values[8]	864	1			T2	1		T4	14		T7	5
values[9]	225	1			T20	17		T130	1		T162	1
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	8		T121	10		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	12		T121	5		T258	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	7		T13	14		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T11	13		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T17	2		T24	11		T264	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	12		T126	1		T255	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1456	1			T5	3		T11	9		T86	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T15	7		T169	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	1		T178	1		T16	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T24	10		T123	1		T244	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T18	2		T178	1		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	18		T17	1		T209	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T148	1		T32	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T151	9		T234	9		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	14		T131	13		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	11		T178	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T4	5		T7	3		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T2	1		T4	9		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T130	1		T162	1		T26	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T20	8		T265	1		T229	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T122	9		T266	1		T267	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	10		T127	13		T236	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	14		T209	9		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T134	9		T239	8		T268	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T24	9		T205	4		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T126	3		T255	3		T212	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T87	24		T242	15		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	3		T127	1		T269	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	2		T16	1		T190	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T24	11		T123	2		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T16	4		T123	19		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T209	13		T270	6		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T148	14		T32	1		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T151	8		T243	11		T124	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	13		T131	12		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T209	10		T133	6		T151	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	2		T10	1		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T208	4		T175	9		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T26	8		T79	7		T271	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T20	9		T265	7		T155	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T10	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T260	1		T261	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T262	12		T272	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T121	5		T263	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T12	8		T13	14		T121	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	13		T258	5		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	7		T129	1		T209	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	1		T7	12		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T17	1		T231	1		T205	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	12		T126	1		T212	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T5	3		T11	9		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	7		T24	10		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	6		T123	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T4	18		T244	1		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	1		T18	2		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	1		T209	1		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T178	1		T16	2		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T234	9		T243	1		T125	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	14		T148	1		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	11		T13	4		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	431	1			T4	5		T7	3		T11	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T2	1		T4	9		T18	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T10	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T262	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	14		T267	11		T238	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T127	13		T236	12		T273	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T209	9		T122	9		T205	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	10		T134	9		T255	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T205	4		T247	25		T269	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T126	3		T212	1		T268	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T87	24		T242	15		T136	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	3		T24	11		T123	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	4		T123	6		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T244	10		T213	5		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	2		T16	1		T126	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T209	13		T124	7		T127	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T16	1		T32	1		T123	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T243	11		T125	11		T270	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	13		T148	14		T122	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T209	10		T151	8		T125	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T7	2		T131	12		T32	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T20	9		T208	4		T175	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1