Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21054

1

T1

18

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3760

1

T2

1

T4

9

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18785

1

T1

18

T2

1

T3

20

auto[1]

6029

1

T2

1

T4

9

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	463	1			T8	2		T9	2		T18	6
values[0]	52	1			T2	1		T18	5		T191	18
values[1]	621	1			T208	9		T16	15		T175	17
values[2]	2774	1			T1	7		T5	3		T17	1
values[3]	635	1			T2	1		T10	27		T12	11
values[4]	613	1			T7	25		T11	13		T209	14
values[5]	795	1			T4	18		T7	5		T17	1
values[6]	783	1			T129	1		T15	8		T178	2
values[7]	557	1			T4	9		T12	12		T13	4
values[8]	499	1			T1	11		T13	28		T178	1
values[9]	1249	1			T4	5		T10	2		T11	13
minimum	15773	1			T3	20		T6	17		T8	190

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	853	1			T1	7		T2	1		T18	5
values[1]	2703	1			T5	3		T12	11		T17	1
values[2]	766	1			T2	1		T10	27		T11	13
values[3]	553	1			T7	30		T24	21		T264	1
values[4]	726	1			T4	18		T17	1		T130	1
values[5]	789	1			T4	9		T12	12		T129	1
values[6]	507	1			T13	4		T234	9		T137	3
values[7]	619	1			T1	11		T10	2		T178	1
values[8]	888	1			T4	5		T11	13		T13	28
values[9]	216	1			T209	21		T151	17		T265	8
minimum	16194	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	7		T2	1		T18	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T18	2		T208	5		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1319	1			T5	3		T12	3		T86	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	8		T17	1		T264	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T121	10		T246	9		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	1		T10	14		T11	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	12		T235	4		T190	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	4		T24	10		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	18		T16	2		T205	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T17	1		T130	1		T133	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	1		T15	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T4	9		T12	12		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T234	9		T137	3		T284	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	4		T54	2		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	11		T162	1		T236	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	1		T178	1		T258	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	5		T131	13		T121	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T11	13		T13	14		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T209	2		T151	9		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T265	1		T229	1		T192	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16053	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T282	1		T338	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T16	4		T175	9		T151	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T208	4		T16	1		T32	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	999	1			T87	24		T20	9		T242	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T123	6		T155	9		T275	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T246	2		T241	8		T126	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	13		T209	13		T26	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	10		T235	2		T190	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	4		T24	11		T124	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T16	1		T205	4		T125	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T133	6		T265	9		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	1		T123	13		T255	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T15	2		T32	21		T123	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T284	5		T273	8		T277	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T54	1		T154	13		T240	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T236	12		T190	12		T239	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	1		T125	12		T267	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T131	12		T122	9		T151	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	14		T136	9		T24	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T209	19		T151	8		T269	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T265	7		T192	7		T339	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T338	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	425	1			T8	2		T9	2		T18	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T340	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T2	1		T18	3		T341	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T18	2		T191	14		T342	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	6		T175	8		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T208	5		T16	4		T205	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T1	7		T5	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T17	1		T162	1		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	3		T20	8		T121	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	1		T10	14		T12	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	12		T246	9		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T11	13		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T4	18		T15	1		T16	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	3		T17	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T129	1		T178	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T15	6		T178	1		T32	29
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T137	3		T284	7		T273	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T4	9		T12	12		T13	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	11		T162	1		T234	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	14		T178	1		T24	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T4	5		T209	2		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	441	1			T10	1		T11	13		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15636	1			T3	20		T6	17		T8	190
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T45	13		T85	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T340	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T191	4		T343	2		T344	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	4		T175	9		T151	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T208	4		T16	1		T205	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T87	24		T242	15		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T32	1		T126	3		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T20	9		T134	9		T241	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	13		T26	8		T141	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	10		T246	2		T235	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	2		T209	13		T24	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	1		T16	1		T205	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	2		T133	6		T265	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T123	13		T255	3		T318	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T15	2		T32	21		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T284	5		T273	8		T240	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T154	13		T240	9		T277	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T236	12		T239	8		T332	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T13	14		T24	9		T122	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T209	19		T131	12		T122	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T10	1		T136	9		T133	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	1		T2	1		T18	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T18	1		T208	5		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T5	3		T12	1		T86	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T12	1		T17	1		T264	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T121	1		T246	8		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T2	1		T10	14		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	11		T235	3		T190	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	6		T24	12		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	1		T16	2		T205	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T17	1		T130	1		T133	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	1		T15	2		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T4	1		T12	1		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T234	1		T137	1		T284	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	1		T54	2		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T162	1		T236	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	2		T178	1		T258	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T131	13		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T11	2		T13	15		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T209	21		T151	9		T269	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T265	8		T229	1		T192	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16190	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T282	1		T338	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	6		T18	1		T16	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T18	1		T208	4		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T12	2		T19	20		T20	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	7		T258	16		T259	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T121	9		T246	3		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T10	13		T11	12		T26	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	11		T235	3		T155	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T7	2		T24	9		T270	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	17		T16	1		T205	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	2		T240	8		T268	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T54	2		T255	11		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	8		T12	11		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T234	8		T137	2		T284	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	3		T54	1		T240	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	10		T236	11		T215	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T258	5		T279	6		T254	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	4		T131	12		T121	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T11	11		T13	13		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T151	8		T345	14		T217	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T192	7		T257	10		T158	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T338	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	433	1			T8	2		T9	2		T18	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T340	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T2	1		T18	2		T341	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T18	1		T191	5		T342	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	6		T175	10		T151	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T208	5		T16	4		T205	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T1	1		T5	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T17	1		T162	1		T32	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T20	10		T121	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	1		T10	14		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	11		T246	8		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	3		T11	1		T209	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	1		T15	2		T16	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	3		T17	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T129	1		T178	1		T231	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T15	6		T178	1		T32	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T137	1		T284	6		T273	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	1		T12	1		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	1		T162	1		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T13	15		T178	1		T24	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T4	1		T209	21		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T10	2		T11	2		T130	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15773	1			T3	20		T6	17		T8	190
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T45	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T340	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T18	1		T341	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T18	1		T191	13		T342	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	4		T175	7		T151	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T208	4		T16	1		T205	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T1	6		T19	20		T163	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T258	4		T127	14		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T12	2		T20	7		T121	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	13		T12	7		T26	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T7	11		T246	3		T235	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	12		T24	9		T289	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T4	17		T16	1		T205	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	2		T133	2		T141	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T54	2		T255	11		T276	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	2		T32	27		T244	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T137	2		T284	6		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	8		T12	11		T13	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	10		T234	8		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	13		T24	10		T122	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	4		T131	12		T121	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T11	11		T136	10		T133	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13