Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19508

1

T1

11

T3

20

T4

5

auto[ADC_CTRL_FILTER_COND_OUT]

5306

1

T1

7

T2

2

T4

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18958

1

T2

1

T3

20

T6

17

auto[1]

5856

1

T1

18

T2

1

T4

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	49	1			T132	1		T240	23		T333	2
values[0]	10	1			T139	5		T346	1		T290	1
values[1]	649	1			T4	23		T7	5		T11	4
values[2]	740	1			T178	1		T16	5		T32	36
values[3]	576	1			T2	1		T10	27		T11	9
values[4]	732	1			T1	7		T7	22		T12	15
values[5]	672	1			T10	2		T18	2		T130	2
values[6]	539	1			T12	8		T17	1		T209	10
values[7]	655	1			T1	11		T2	1		T4	9
values[8]	748	1			T11	13		T15	10		T148	15
values[9]	3255	1			T5	3		T7	3		T13	4
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	748	1			T4	18		T7	5		T11	4
values[1]	2707	1			T2	1		T4	5		T5	3
values[2]	694	1			T1	7		T10	27		T11	9
values[3]	785	1			T7	22		T12	12		T18	2
values[4]	597	1			T12	11		T17	1		T130	2
values[5]	568	1			T10	2		T209	10		T162	1
values[6]	687	1			T1	11		T2	1		T4	9
values[7]	717	1			T7	3		T11	13		T17	1
values[8]	825	1			T17	1		T129	1		T178	1
values[9]	252	1			T13	4		T18	3		T133	15
minimum	16234	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	3		T209	1		T32	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	18		T11	4		T16	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T4	5		T178	1		T32	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1317	1			T2	1		T5	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	9		T178	1		T137	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	7		T10	14		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T18	2		T24	10		T175	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	12		T12	12		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	8		T162	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T12	3		T17	1		T130	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T209	1		T162	1		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	1		T151	9		T246	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	11		T20	8		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T4	9		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	7		T148	1		T121	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	1		T11	13		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T129	1		T208	5		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T17	1		T178	1		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T18	3		T279	7		T141	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T13	4		T133	8		T202	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16061	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T13	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	2		T209	10		T32	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T16	1		T122	12		T151	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T32	19		T244	5		T255	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	934	1			T87	24		T242	15		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T235	2		T255	3		T277	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	13		T127	13		T268	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T24	11		T175	9		T205	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	10		T209	13		T133	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T205	2		T270	6		T190	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T24	9		T289	3		T199	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T209	9		T237	2		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T10	1		T151	8		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T20	9		T134	9		T241	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T125	11		T126	13		T269	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	3		T148	14		T123	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	2		T32	2		T155	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T208	4		T243	11		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T131	12		T136	9		T240	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T141	19		T45	13		T192	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T133	7		T202	9		T238	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T112	2		T16	5		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T13	14		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T132	1		T240	13		T333	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T347	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T346	1		T290	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T139	3		T348	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	5		T7	3		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	18		T11	4		T13	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T178	1		T32	17		T244	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	4		T231	1		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	9		T178	1		T137	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	1		T10	14		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T205	6		T123	1		T124	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T1	7		T7	12		T12	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T18	2		T24	10		T175	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	1		T130	2		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T12	8		T209	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T17	1		T289	14		T125	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	11		T20	8		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	1		T4	9		T246	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	7		T148	1		T234	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	13		T32	12		T258	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T18	3		T129	1		T208	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1527	1			T5	3		T7	1		T13	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T240	10		T333	1		T349	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T347	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T139	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	2		T209	10		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	14		T16	1		T122	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T32	19		T244	5		T127	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T16	1		T124	7		T247	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T255	3		T277	23		T230	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	13		T209	13		T268	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T205	4		T123	2		T124	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	10		T24	9		T127	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T24	11		T175	9		T205	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	1		T133	6		T151	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T209	9		T237	2		T125	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T289	3		T125	10		T199	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T20	9		T134	9		T274	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T246	2		T125	11		T126	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	3		T148	14		T123	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T32	2		T155	2		T266	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T208	4		T243	11		T284	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1175	1			T7	2		T87	24		T242	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	3		T209	11		T32	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	1		T11	1		T16	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T4	1		T178	1		T32	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1274	1			T2	1		T5	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	1		T178	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T1	1		T10	14		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T18	1		T24	12		T175	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	11		T12	1		T209	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	1		T162	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	1		T17	1		T130	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T209	10		T162	1		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	2		T151	9		T246	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T20	10		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T4	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T15	8		T148	15		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	3		T11	1		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T129	1		T208	5		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T17	1		T178	1		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T18	2		T279	1		T141	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T13	1		T133	8		T202	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16200	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T13	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	2		T26	2		T122	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	17		T11	3		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	4		T32	16		T244	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	977	1			T19	20		T16	1		T163	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	8		T137	2		T235	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	6		T10	13		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T18	1		T24	9		T175	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	11		T12	11		T133	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	7		T205	2		T258	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T12	2		T24	10		T289	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T237	12		T54	2		T297	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T151	8		T246	3		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	10		T20	7		T241	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T4	8		T258	5		T125	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T15	2		T121	4		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	12		T32	11		T155	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T208	4		T247	11		T240	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T131	12		T136	10		T121	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T18	1		T279	6		T141	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T13	3		T133	7		T202	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T16	4		T298	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T13	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T132	1		T240	11		T333	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T347	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T346	1		T290	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T139	3		T348	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	1		T7	3		T209	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	1		T11	1		T13	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T178	1		T32	20		T244	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	4		T231	1		T124	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T11	1		T178	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T10	14		T209	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T205	8		T123	3		T124	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T7	11		T12	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T18	1		T24	12		T175	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	2		T130	2		T133	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T12	1		T209	10		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T17	1		T289	4		T125	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T20	10		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T2	1		T4	1		T246	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T15	8		T148	15		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	1		T32	3		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T18	2		T129	1		T208	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1556	1			T5	3		T7	3		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T240	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T347	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T139	2		T348	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	4		T7	2		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	17		T11	3		T13	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T32	16		T244	2		T127	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T16	1		T247	4		T186	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	8		T137	2		T255	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T10	13		T141	2		T277	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T205	2		T235	3		T140	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	6		T7	11		T12	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T18	1		T24	9		T175	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T133	2		T151	8		T278	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	7		T237	12		T258	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T289	13		T125	10		T254	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T1	10		T20	7		T274	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	8		T246	3		T125	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	2		T234	8		T241	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	12		T32	11		T258	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T18	1		T208	4		T121	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1146	1			T13	3		T19	20		T131	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13