Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21078

1

T1

18

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3736

1

T2

1

T4

9

T7

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18831

1

T1

18

T2

1

T3

20

auto[1]

5983

1

T2

1

T4

9

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	640	1			T4	5		T8	2		T9	2
values[0]	25	1			T2	1		T16	5		T341	16
values[1]	681	1			T18	5		T208	9		T16	10
values[2]	2747	1			T1	7		T5	3		T17	1
values[3]	612	1			T2	1		T10	27		T12	11
values[4]	698	1			T7	25		T11	13		T209	14
values[5]	774	1			T4	18		T7	5		T17	1
values[6]	726	1			T12	12		T129	1		T15	10
values[7]	571	1			T4	9		T13	4		T137	3
values[8]	480	1			T1	11		T178	1		T162	1
values[9]	1087	1			T10	2		T11	13		T13	28
minimum	15773	1			T3	20		T6	17		T8	190

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	679	1			T1	7		T18	3		T208	9
values[1]	2675	1			T5	3		T12	11		T17	1
values[2]	714	1			T2	1		T10	27		T17	1
values[3]	571	1			T7	30		T11	13		T16	3
values[4]	764	1			T4	18		T17	1		T130	1
values[5]	769	1			T4	9		T12	12		T129	1
values[6]	478	1			T13	4		T137	3		T54	3
values[7]	737	1			T1	11		T10	2		T13	28
values[8]	873	1			T4	5		T11	13		T130	1
values[9]	132	1			T209	11		T151	17		T265	8
minimum	16422	1			T2	1		T3	20		T6	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	7		T18	3		T208	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T162	1		T151	5		T205	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T5	3		T12	3		T86	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	8		T17	1		T32	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T209	1		T246	9		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T2	1		T10	14		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	12		T16	2		T235	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	4		T11	13		T24	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T4	18		T133	3		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T17	1		T130	1		T205	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	12		T129	1		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T4	9		T15	1		T178	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T137	3		T284	7		T265	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	4		T54	2		T273	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	11		T162	1		T234	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	1		T13	14		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T4	5		T11	4		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T11	9		T136	11		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T209	1		T151	9		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T265	1		T229	1		T345	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16103	1			T2	1		T3	20		T6	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T18	2		T16	4		T175	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T208	4		T16	4		T123	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T151	2		T205	2		T124	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T87	24		T20	9		T242	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T32	1		T127	13		T155	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T209	13		T246	2		T241	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	13		T26	8		T289	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	10		T16	1		T235	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	4		T24	11		T124	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T133	6		T125	11		T139	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T205	4		T247	11		T265	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	2		T123	2		T255	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	1		T32	21		T123	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T284	5		T277	1		T79	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T54	1		T273	8		T154	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T125	12		T266	1		T181	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	1		T13	14		T24	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T209	9		T131	12		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T136	9		T243	11		T194	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T209	10		T151	8		T269	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T265	7		T339	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T16	1		T175	9		T139	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	478	1			T4	5		T8	2		T9	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T229	1		T257	11		T345	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T2	1		T341	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T16	4		T343	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	3		T208	5		T16	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T18	2		T175	8		T151	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T1	7		T5	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T17	1		T162	1		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T12	3		T20	8		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	1		T10	14		T12	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	12		T209	1		T246	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T11	13		T24	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	18		T16	2		T133	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	3		T17	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	12		T129	1		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T15	1		T178	2		T32	29
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T137	3		T284	7		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	9		T13	4		T273	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	11		T162	1		T234	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T178	1		T24	11		T122	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	4		T209	1		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T10	1		T11	9		T13	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15636	1			T3	20		T6	17		T8	190
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T209	10		T133	7		T269	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T350	1		T339	12		T351	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T16	1		T343	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T208	4		T16	4		T123	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T175	9		T151	2		T205	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T87	24		T242	15		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T32	1		T127	13		T247	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T20	9		T134	9		T241	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	13		T26	8		T126	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	10		T209	13		T246	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	2		T24	11		T289	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T16	1		T133	6		T125	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	2		T205	4		T247	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T15	2		T123	2		T255	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	1		T32	21		T123	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T284	5		T240	10		T277	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T273	8		T154	13		T240	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T266	1		T181	7		T159	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	9		T122	12		T54	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T209	9		T131	12		T122	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	1		T13	14		T136	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T18	2		T208	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T162	1		T151	3		T205	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T5	3		T12	1		T86	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T17	1		T32	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T209	14		T246	8		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	1		T10	14		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	11		T16	2		T235	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	6		T11	1		T24	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T4	1		T133	7		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T17	1		T130	1		T205	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	1		T129	1		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	1		T15	2		T178	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T137	1		T284	6		T265	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T54	2		T273	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	1		T162	1		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	2		T13	15		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T4	1		T11	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	1		T136	10		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T209	11		T151	9		T269	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T265	8		T229	1		T345	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16248	1			T2	1		T3	20		T6	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T18	1		T16	4		T175	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T1	6		T18	1		T208	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T151	4		T205	2		T247	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T12	2		T19	20		T20	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	7		T258	4		T127	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T246	3		T241	6		T125	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	13		T121	9		T26	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T7	11		T16	1		T235	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	2		T11	12		T24	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	17		T133	2		T125	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T205	2		T247	11		T141	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	11		T15	2		T255	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	8		T32	27		T244	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T137	2		T284	6		T277	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	3		T54	1		T240	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	10		T234	8		T258	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	13		T121	4		T24	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	4		T11	3		T131	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	8		T136	10		T278	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T151	8		T331	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T345	14		T158	4		T339	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T141	2		T187	12		T337	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T18	1		T16	1		T175	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	492	1			T4	1		T8	2		T9	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T229	1		T257	1		T345	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T2	1		T341	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T16	4		T343	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T18	2		T208	5		T16	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T18	1		T175	10		T151	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T1	1		T5	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T17	1		T162	1		T32	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	1		T20	10		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T10	14		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	11		T209	14		T246	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	3		T11	1		T24	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T4	1		T16	2		T133	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	3		T17	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T12	1		T129	1		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T15	2		T178	2		T32	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T137	1		T284	6		T265	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	1		T13	1		T273	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T1	1		T162	1		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T178	1		T24	10		T122	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T11	1		T209	10		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T10	2		T11	1		T13	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15773	1			T3	20		T6	17		T8	190
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T4	4		T133	7		T45	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T257	10		T345	14		T330	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T341	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T16	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T18	1		T208	4		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T18	1		T175	7		T151	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T1	6		T19	20		T163	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T258	4		T127	14		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T12	2		T20	7		T258	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	13		T12	7		T121	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	11		T246	3		T125	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	12		T24	9		T289	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	17		T16	1		T133	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T7	2		T205	2		T247	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	11		T15	2		T255	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T32	27		T244	2		T54	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T137	2		T284	6		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	8		T13	3		T240	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T1	10		T234	8		T258	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T24	10		T122	10		T279	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	3		T131	12		T122	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T11	8		T13	13		T136	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13