Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21510

1

T1

11

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3304

1

T1

7

T2

1

T4

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19054

1

T1

18

T3

20

T4

27

auto[1]

5760

1

T2

2

T4

5

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	268	1			T12	12		T16	3		T24	21
values[0]	55	1			T228	9		T316	1		T161	18
values[1]	635	1			T1	7		T10	27		T12	3
values[2]	823	1			T2	2		T13	4		T148	15
values[3]	660	1			T4	5		T12	8		T130	1
values[4]	622	1			T7	5		T20	17		T15	8
values[5]	686	1			T7	3		T13	28		T178	1
values[6]	565	1			T4	27		T17	1		T209	11
values[7]	688	1			T11	13		T130	1		T178	1
values[8]	2722	1			T5	3		T10	2		T17	1
values[9]	901	1			T1	11		T7	22		T11	13
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	727	1			T1	7		T12	3		T13	4
values[1]	721	1			T2	2		T12	8		T148	15
values[2]	622	1			T4	5		T130	1		T178	1
values[3]	687	1			T7	5		T13	28		T20	17
values[4]	600	1			T7	3		T17	1		T178	1
values[5]	712	1			T4	27		T11	13		T209	11
values[6]	2653	1			T5	3		T86	2		T87	27
values[7]	710	1			T10	2		T17	1		T129	1
values[8]	807	1			T1	11		T7	22		T11	13
values[9]	151	1			T264	1		T254	11		T172	8
minimum	16424	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	3		T18	5		T32	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T1	7		T13	4		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	1		T24	11		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	1		T12	8		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	5		T130	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T168	1		T232	1		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	3		T15	6		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	14		T20	8		T131	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	1		T17	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T178	1		T16	6		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	13		T133	3		T234	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	27		T209	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T5	3		T86	2		T87	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T178	1		T136	11		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T10	1		T121	10		T123	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	1		T129	1		T26	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	11		T11	9		T12	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T7	12		T11	4		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T313	14		T304	4		T158	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T264	1		T254	11		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16122	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T10	14		T15	1		T162	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T32	2		T244	10		T127	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T209	13		T241	8		T190	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T24	9		T151	2		T194	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T148	14		T122	9		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T208	4		T205	2		T124	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T199	5		T236	12		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	2		T15	2		T209	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	14		T20	9		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	2		T237	2		T126	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T16	4		T32	1		T205	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T133	6		T155	9		T268	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T209	10		T139	11		T256	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T87	24		T242	15		T142	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T136	9		T318	11		T296	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T10	1		T123	2		T293	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T26	8		T289	3		T125	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T16	1		T244	5		T270	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T7	10		T16	1		T24	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T216	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T172	7		T324	1		T245	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T10	13		T15	1		T124	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T12	12		T16	2		T274	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T24	10		T175	8		T133	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T316	1		T161	9		T320	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T228	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	3		T18	5		T32	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	7		T10	14		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T2	1		T24	11		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	1		T13	4		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T4	5		T130	1		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T12	8		T168	1		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	3		T15	6		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T20	8		T123	2		T246	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	1		T231	1		T237	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	14		T178	1		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T17	1		T282	1		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	27		T209	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	13		T130	1		T133	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T178	1		T136	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T5	3		T10	1		T86	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	1		T129	1		T26	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	11		T11	9		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T7	12		T11	4		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T16	1		T274	10		T214	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T24	11		T175	9		T133	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T161	9		T320	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T32	2		T151	2		T127	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	13		T15	1		T209	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T24	9		T244	10		T194	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T148	14		T122	9		T202	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T208	4		T205	2		T124	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T54	1		T236	12		T247	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	2		T15	2		T209	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T20	9		T123	19		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	2		T237	2		T126	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	14		T131	12		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T46	7		T262	10		T251	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T209	10		T256	4		T46	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T133	6		T134	9		T284	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T136	9		T139	11		T318	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T10	1		T87	24		T242	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T26	8		T289	3		T125	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T123	2		T244	5		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T7	10		T16	1		T122	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T18	3		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T1	1		T13	1		T209	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	1		T24	10		T151	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T2	1		T12	1		T148	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	1		T130	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T168	1		T232	1		T199	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	3		T15	6		T209	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	15		T20	10		T131	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	3		T17	1		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T178	1		T16	6		T32	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	1		T133	7		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T4	2		T209	11		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T5	3		T86	2		T87	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T178	1		T136	10		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	2		T121	1		T123	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T17	1		T129	1		T26	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T11	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T7	11		T11	1		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T313	1		T304	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T264	1		T254	1		T172	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16262	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T10	14		T15	2		T162	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	2		T18	2		T32	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	6		T13	3		T241	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T24	10		T151	4		T258	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	7		T122	8		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	4		T208	4		T121	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T236	11		T139	2		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	2		T15	2		T32	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	13		T20	7		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T237	12		T258	5		T54	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T16	4		T205	2		T125	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	12		T133	2		T234	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	25		T139	11		T300	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T19	20		T163	22		T135	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T136	10		T258	4		T321	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T121	9		T253	9		T79	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T26	2		T289	13		T254	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T1	10		T11	8		T12	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	11		T11	3		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T313	13		T304	3		T158	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T254	10		T352	12		T245	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T269	8		T56	4		T353	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T10	13		T335	13		T228	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T12	1		T16	2		T274	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T24	12		T175	10		T133	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T316	1		T161	10		T320	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T228	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	1		T18	3		T32	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T10	14		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	1		T24	10		T244	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T2	1		T13	1		T148	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	1		T130	1		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T168	1		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	3		T15	6		T209	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T20	10		T123	21		T246	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	3		T231	1		T237	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	15		T178	1		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T17	1		T282	1		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	2		T209	11		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	1		T130	1		T133	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T178	1		T136	10		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T5	3		T10	2		T86	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T17	1		T129	1		T26	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T11	1		T123	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T7	11		T11	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T12	11		T16	1		T274	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T24	9		T175	7		T133	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T161	8		T320	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T228	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	2		T18	2		T32	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	6		T10	13		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T24	10		T258	12		T255	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	3		T122	8		T202	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	4		T208	4		T205	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T12	7		T54	1		T236	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	2		T15	2		T121	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T20	7		T246	3		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T237	12		T258	5		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	13		T131	12		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T278	17		T262	11		T313	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	25		T300	10		T53	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	12		T133	2		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T136	10		T258	4		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T19	20		T121	9		T163	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T26	2		T289	13		T254	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	10		T11	8		T244	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	11		T11	3		T16	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13