Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21591

1

T1

11

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3223

1

T1

7

T2

1

T4

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19097

1

T3

20

T4

14

T6

17

auto[1]

5717

1

T1

18

T2

2

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	152	1			T11	4		T15	8		T123	7
values[0]	89	1			T127	28		T256	8		T281	19
values[1]	649	1			T162	2		T151	7		T234	9
values[2]	651	1			T7	22		T12	12		T13	4
values[3]	883	1			T1	18		T10	27		T11	13
values[4]	655	1			T2	2		T11	9		T17	1
values[5]	2858	1			T4	9		T5	3		T18	2
values[6]	442	1			T12	3		T15	2		T178	1
values[7]	405	1			T4	18		T7	5		T10	2
values[8]	869	1			T7	3		T209	11		T136	20
values[9]	972	1			T4	5		T12	8		T20	17
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	591	1			T13	4		T162	1		T134	10
values[1]	596	1			T7	22		T10	27		T12	12
values[2]	949	1			T1	18		T11	13		T17	1
values[3]	2705	1			T2	2		T5	3		T11	9
values[4]	732	1			T4	9		T130	1		T148	15
values[5]	416	1			T12	3		T13	28		T15	2
values[6]	550	1			T4	18		T7	8		T10	2
values[7]	695	1			T209	11		T16	3		T151	17
values[8]	917	1			T11	4		T12	8		T20	17
values[9]	127	1			T4	5		T15	8		T123	7
minimum	16536	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	4		T162	1		T134	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T205	6		T123	1		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	1		T178	1		T121	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	12		T10	14		T12	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T1	11		T11	13		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	7		T175	8		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T2	1		T5	3		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	1		T11	9		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T4	9		T130	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T148	1		T16	6		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T12	3		T16	4		T32	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	14		T15	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	1		T10	1		T122	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	18		T7	3		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T138	2		T270	4		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T209	1		T16	2		T151	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T20	8		T136	11		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	4		T12	8		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T125	3		T73	3		T354	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T4	5		T15	6		T123	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16159	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T162	1		T168	1		T279	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T134	9		T151	2		T244	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T205	4		T123	13		T199	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	19		T244	5		T54	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	10		T10	13		T209	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T209	13		T131	12		T126	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T175	9		T139	2		T213	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T87	24		T242	15		T142	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T208	4		T24	11		T133	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T26	8		T124	7		T247	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	14		T16	4		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T16	1		T32	2		T124	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T13	14		T15	1		T151	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	2		T10	1		T122	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T7	2		T194	6		T273	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T270	6		T155	4		T268	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T209	10		T16	1		T151	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T20	9		T136	9		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T212	1		T190	12		T239	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T125	11		T73	1		T308	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T15	2		T123	6		T79	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T127	13		T48	5		T181	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T73	7		T171	1		T55	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T11	4		T15	6		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T256	8		T281	8		T355	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T127	15		T288	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T162	1		T151	5		T234	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T162	1		T205	6		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	4		T17	1		T121	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	12		T12	12		T246	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	11		T11	13		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T1	7		T10	14		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T2	1		T18	3		T24	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	1		T11	9		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1472	1			T4	9		T5	3		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T129	1		T208	5		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T12	3		T16	4		T32	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	1		T178	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T10	1		T122	11		T282	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	18		T7	3		T13	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T7	1		T136	11		T244	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T209	1		T151	9		T205	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T20	8		T32	1		T137	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T4	5		T12	8		T16	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T73	5		T171	2		T55	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T15	2		T123	6		T212	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T281	11		T355	2		T356	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T127	13		T288	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T151	2		T244	10		T265	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T205	4		T123	13		T199	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T32	19		T134	9		T244	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T7	10		T246	2		T127	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T209	13		T131	12		T126	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	13		T209	9		T289	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T24	9		T269	6		T141	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T24	11		T175	9		T133	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1098	1			T87	24		T242	15		T142	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T208	4		T148	14		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T16	1		T32	2		T125	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T15	1		T243	11		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T10	1		T122	12		T124	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	2		T13	14		T151	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	2		T136	9		T244	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T209	10		T151	8		T205	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T20	9		T32	1		T125	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T16	1		T190	12		T239	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	1		T162	1		T134	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T205	8		T123	14		T199	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T17	1		T178	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	11		T10	14		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T1	1		T11	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	1		T175	10		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T2	1		T5	3		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T11	1		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T4	1		T130	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T148	15		T16	6		T243	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	1		T16	4		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	15		T15	2		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	3		T10	2		T122	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T4	1		T7	3		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T138	2		T270	9		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T209	11		T16	2		T151	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T20	10		T136	10		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T11	1		T12	1		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T125	12		T73	3		T354	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T4	1		T15	6		T123	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16310	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T162	1		T168	1		T279	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	3		T151	4		T234	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T205	2		T267	12		T222	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T121	9		T32	16		T244	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	11		T10	13		T12	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	10		T11	12		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	6		T175	7		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T18	1		T19	20		T163	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	8		T208	4		T121	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	8		T26	2		T247	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T16	4		T127	13		T140	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T12	2		T16	1		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	13		T151	7		T237	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T122	10		T235	3		T253	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T4	17		T7	2		T278	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T270	1		T155	4		T268	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	1		T151	8		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T20	7		T136	10		T137	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	3		T12	7		T258	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T125	2		T73	1		T74	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T4	4		T15	2		T79	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T256	7		T238	10		T275	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T279	6		T127	14		T174	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T73	9		T171	3		T55	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T11	1		T15	6		T123	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T256	1		T281	12		T355	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T127	14		T288	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T162	1		T151	3		T234	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T162	1		T205	8		T123	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	1		T17	1		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	11		T12	1		T246	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	1		T11	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T10	14		T209	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T2	1		T18	2		T24	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T2	1		T11	1		T17	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1460	1			T4	1		T5	3		T18	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T129	1		T208	5		T148	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T16	4		T32	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	2		T178	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T10	2		T122	13		T282	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	1		T7	3		T13	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T7	3		T136	10		T244	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T209	11		T151	9		T205	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T20	10		T32	2		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T4	1		T12	1		T16	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T73	3		T55	8		T275	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T11	3		T15	2		T212	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T256	7		T281	7		T355	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T127	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T151	4		T234	8		T238	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T205	2		T279	6		T214	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	3		T121	9		T32	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	11		T12	11		T246	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	10		T11	12		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	6		T10	13		T289	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T18	1		T24	10		T141	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	8		T121	4		T24	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1110	1			T4	8		T18	1		T19	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T208	4		T16	4		T127	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T12	2		T16	1		T32	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T237	12		T247	11		T240	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T122	10		T235	3		T253	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	17		T7	2		T13	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T136	10		T270	1		T155	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T151	8		T205	2		T241	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T20	7		T137	2		T125	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	4		T12	7		T16	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13