Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21287

1

T2

1

T3

20

T4

32

auto[ADC_CTRL_FILTER_COND_OUT]

3527

1

T1

18

T2

1

T7

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19191

1

T1

18

T2

1

T3

20

auto[1]

5623

1

T2

1

T4

23

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	129	1			T11	9		T17	1		T18	3
values[0]	31	1			T125	14		T310	1		T311	16
values[1]	647	1			T13	4		T130	1		T178	2
values[2]	618	1			T2	1		T4	9		T7	22
values[3]	677	1			T11	13		T18	2		T16	10
values[4]	832	1			T4	5		T7	5		T10	2
values[5]	696	1			T12	3		T17	2		T209	10
values[6]	612	1			T1	7		T2	1		T178	1
values[7]	607	1			T1	11		T10	27		T11	4
values[8]	755	1			T4	18		T7	3		T130	1
values[9]	3021	1			T5	3		T129	1		T86	2
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	647	1			T4	9		T13	4		T130	1
values[1]	703	1			T2	1		T7	22		T11	13
values[2]	570	1			T18	2		T16	10		T24	20
values[3]	927	1			T4	5		T7	5		T13	28
values[4]	657	1			T10	2		T12	3		T17	2
values[5]	647	1			T1	7		T2	1		T12	12
values[6]	2660	1			T1	11		T5	3		T10	27
values[7]	772	1			T4	18		T7	3		T209	11
values[8]	746	1			T11	9		T17	1		T18	3
values[9]	126	1			T126	11		T254	15		T79	17
minimum	16359	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	9		T130	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	4		T178	2		T131	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T2	1		T246	9		T62	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	12		T11	13		T12	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T24	11		T132	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T18	2		T16	6		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	5		T208	5		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	3		T13	14		T32	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T10	1		T32	1		T151	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	3		T17	2		T175	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T178	1		T134	1		T151	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	7		T2	1		T12	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T5	3		T11	4		T86	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T1	11		T10	14		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	18		T7	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T133	3		T205	6		T123	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	9		T17	1		T18	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T129	1		T15	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T126	1		T305	1		T158	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T254	15		T79	10		T308	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16091	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T258	5		T126	1		T265	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T199	5		T236	12		T235	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T131	12		T123	13		T124	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T246	2		T293	2		T276	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	10		T20	9		T26	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T24	9		T127	13		T306	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T16	4		T247	11		T269	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T208	4		T209	9		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	2		T13	14		T32	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	1		T32	1		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T175	9		T139	11		T255	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T134	9		T151	8		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T122	12		T124	7		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T87	24		T242	15		T209	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T10	13		T16	1		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	2		T209	10		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T133	6		T205	4		T123	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T15	2		T16	1		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	1		T148	14		T32	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T126	10		T250	9		T357	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T79	7		T308	6		T339	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T126	3		T311	4		T160	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T11	9		T17	1		T18	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T15	1		T232	1		T229	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T125	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T310	1		T311	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T130	1		T121	5		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	4		T178	2		T131	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	1		T4	9		T246	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	12		T12	8		T20	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T24	11		T132	1		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	13		T18	2		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T4	5		T10	1		T208	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T7	3		T13	14		T32	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T209	1		T136	11		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T12	3		T17	2		T234	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T178	1		T134	1		T151	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	7		T2	1		T175	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	4		T209	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	11		T10	14		T12	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	18		T7	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T130	1		T16	4		T133	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T5	3		T86	2		T87	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T129	1		T148	1		T32	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T126	10		T306	10		T192	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T15	1		T79	7		T351	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T125	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T311	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T244	10		T199	5		T235	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T131	12		T124	7		T126	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T246	2		T236	12		T293	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	10		T20	9		T26	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T24	9		T187	13		T48	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T16	4		T247	11		T240	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	1		T208	4		T127	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	2		T13	14		T32	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T209	9		T136	9		T32	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T125	10		T54	1		T255	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T134	9		T151	2		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T175	9		T122	12		T124	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T209	13		T151	8		T289	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T10	13		T155	9		T172	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	2		T209	10		T24	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T16	1		T133	6		T123	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1046	1			T87	24		T242	15		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T148	14		T32	19		T243	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	1		T130	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	1		T178	2		T131	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	1		T246	8		T62	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	11		T11	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T24	10		T132	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T18	1		T16	6		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	1		T208	5		T209	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T7	3		T13	15		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	2		T32	2		T151	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T17	2		T175	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T178	1		T134	10		T151	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	1		T2	1		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T5	3		T11	1		T86	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	1		T10	14		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	1		T7	3		T209	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T133	7		T205	8		T123	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	1		T17	1		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T129	1		T15	2		T148	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T126	11		T305	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T254	1		T79	8		T308	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16248	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T258	1		T126	4		T265	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T4	8		T236	11		T235	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	3		T131	12		T202	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T246	3		T259	17		T276	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	11		T11	12		T12	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T24	10		T127	13		T274	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T18	1		T16	4		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	4		T208	4		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	2		T13	13		T32	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T151	4		T244	2		T127	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	2		T175	7		T234	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T151	8		T237	12		T277	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	6		T12	11		T122	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T11	3		T19	20		T163	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	10		T10	13		T121	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T4	17		T133	7		T151	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T133	2		T205	2		T140	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	8		T18	1		T15	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T32	16		T241	6		T54	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T158	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T254	14		T79	9		T339	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T121	4		T125	2		T47	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T258	4		T311	11		T358	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T11	1		T17	1		T18	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T15	2		T232	1		T229	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T125	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T310	1		T311	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T130	1		T121	1		T162	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	1		T178	2		T131	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T2	1		T4	1		T246	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T7	11		T12	1		T20	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T24	10		T132	1		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	1		T18	1		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T10	2		T208	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T7	3		T13	15		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T209	10		T136	10		T32	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	1		T17	2		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T178	1		T134	10		T151	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	1		T2	1		T175	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T209	14		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	1		T10	14		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	1		T7	3		T209	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T130	1		T16	4		T133	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T5	3		T86	2		T87	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T129	1		T148	15		T32	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T11	8		T18	1		T192	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T79	9		T174	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T125	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T311	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T121	4		T235	3		T47	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	3		T131	12		T258	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T4	8		T246	3		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	11		T12	7		T20	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	10		T187	12		T274	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	12		T18	1		T16	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T4	4		T208	4		T279	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	2		T13	13		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T136	10		T244	2		T127	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T12	2		T234	8		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T151	4		T237	12		T314	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	6		T175	7		T122	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	3		T151	8		T289	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	10		T10	13		T12	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	17		T24	9		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	1		T133	2		T140	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1031	1			T19	20		T15	2		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T32	16		T205	2		T241	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13