Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21552

1

T1

7

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3262

1

T1

11

T2

1

T4

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18835

1

T1

7

T2

2

T3

20

auto[1]

5979

1

T1

11

T4

23

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	160	1			T1	7		T17	1		T124	8
values[0]	97	1			T202	23		T229	1		T82	12
values[1]	612	1			T4	23		T12	8		T18	3
values[2]	583	1			T11	13		T18	2		T231	1
values[3]	622	1			T2	1		T162	1		T26	15
values[4]	811	1			T12	12		T20	17		T130	1
values[5]	2810	1			T5	3		T13	28		T17	1
values[6]	545	1			T10	27		T13	4		T209	10
values[7]	517	1			T7	3		T11	9		T12	3
values[8]	720	1			T4	9		T136	20		T16	5
values[9]	1148	1			T1	11		T2	1		T7	27
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	588	1			T4	5		T12	8		T129	1
values[1]	645	1			T11	13		T18	2		T231	1
values[2]	665	1			T2	1		T130	1		T162	1
values[3]	2816	1			T5	3		T12	12		T86	2
values[4]	650	1			T13	28		T17	1		T178	1
values[5]	621	1			T7	3		T10	27		T11	9
values[6]	588	1			T4	9		T136	20		T148	15
values[7]	760	1			T1	11		T15	2		T16	10
values[8]	906	1			T1	7		T2	1		T7	27
values[9]	163	1			T209	14		T32	2		T236	24
minimum	16412	1			T3	20		T4	18		T6	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T4	5		T129	1		T208	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	8		T130	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T231	1		T237	13		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	13		T18	2		T205	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T2	1		T130	1		T123	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T162	1		T26	7		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T5	3		T86	2		T87	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	12		T209	1		T121	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	14		T178	1		T32	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	1		T232	1		T127	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	3		T13	4		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	1		T10	14		T11	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T136	11		T121	5		T234	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	9		T148	1		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T16	6		T133	3		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	11		T15	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	7		T7	12		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T2	1		T7	3		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T32	1		T182	16		T359	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T209	1		T236	12		T158	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16112	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T4	18		T15	6		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T208	4		T122	12		T247	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T123	6		T125	12		T194	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T237	2		T125	11		T73	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T205	2		T239	8		T240	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T123	2		T241	8		T126	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T26	8		T199	5		T127	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T87	24		T20	9		T242	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T209	10		T122	9		T243	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	14		T32	2		T244	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T127	13		T154	13		T251	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T32	19		T181	3		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	2		T10	13		T209	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	9		T246	2		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T148	14		T16	2		T151	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T16	4		T133	6		T247	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	1		T134	9		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	10		T10	1		T244	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	2		T24	9		T133	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T32	1		T182	17		T359	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T209	13		T236	12		T360	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T15	2		T202	9		T281	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T1	7		T244	3		T332	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T17	1		T124	1		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T82	1		T248	1		T249	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T202	14		T229	1		T230	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	5		T18	3		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	18		T12	8		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T231	1		T237	13		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	13		T18	2		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T137	3		T241	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T162	1		T26	7		T205	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T20	8		T130	1		T175	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	12		T209	1		T121	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1452	1			T5	3		T13	14		T86	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T17	1		T232	1		T127	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T13	4		T162	1		T244	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	14		T209	1		T131	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	3		T121	5		T246	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	1		T11	9		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T136	11		T234	9		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	9		T16	4		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	12		T10	1		T11	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	386	1			T1	11		T2	1		T7	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T244	5		T332	6		T182	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T124	7		T268	11		T336	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T82	11		T249	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T202	9		T230	13		T250	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T208	4		T122	12		T247	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T15	2		T194	6		T240	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T237	2		T125	11		T73	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T123	6		T125	12		T239	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T241	8		T212	1		T265	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T26	8		T205	2		T199	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T20	9		T175	9		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T209	10		T122	9		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1085	1			T13	14		T87	24		T242	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T127	13		T154	13		T251	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T244	4		T190	21		T181	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	13		T209	9		T131	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T246	2		T253	11		T79	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	2		T148	14		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T136	9		T125	10		T247	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T16	1		T134	9		T123	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	10		T10	1		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T7	2		T15	1		T209	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	1		T129	1		T208	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T130	1		T123	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T231	1		T237	3		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T18	1		T205	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T2	1		T130	1		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T162	1		T26	13		T199	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T5	3		T86	2		T87	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T209	11		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T13	15		T178	1		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T17	1		T232	1		T127	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	1		T13	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	3		T10	14		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	10		T121	1		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	1		T148	15		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T16	6		T133	7		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T15	2		T134	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	1		T7	11		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T2	1		T7	3		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T32	2		T182	18		T359	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T209	14		T236	13		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16244	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T4	1		T15	6		T169	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T4	4		T208	4		T122	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T12	7		T258	5		T240	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T237	12		T125	2		T254	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	12		T18	1		T205	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	2		T241	6		T212	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T26	2		T54	1		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1079	1			T19	20		T20	7		T163	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	11		T121	9		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	13		T32	11		T255	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T127	14		T256	7		T156	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	2		T13	3		T32	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	13		T11	8		T131	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T136	10		T121	4		T234	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T4	8		T16	2		T151	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T16	4		T133	2		T247	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	10		T258	12		T284	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	6		T7	11		T11	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T7	2		T24	10		T133	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T182	15		T359	10		T340	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T236	11		T158	4		T360	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T18	1		T258	4		T52	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T4	17		T15	2		T202	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T1	1		T244	6		T332	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T17	1		T124	8		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T82	12		T248	1		T249	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T202	10		T229	1		T230	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T18	2		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	1		T12	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T231	1		T237	3		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	1		T18	1		T123	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T137	1		T241	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T162	1		T26	13		T205	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T20	10		T130	1		T175	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	1		T209	11		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T5	3		T13	15		T86	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	1		T232	1		T127	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	1		T162	1		T244	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	14		T209	10		T131	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	1		T121	1		T246	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	3		T11	1		T148	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T136	10		T234	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	1		T16	4		T134	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T7	11		T10	2		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T1	1		T2	1		T7	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T1	6		T244	2		T332	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T353	10		T336	12		T360	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T249	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T202	13		T230	10		T250	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T4	4		T18	1		T208	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	17		T12	7		T15	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T237	12		T125	2		T254	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T11	12		T18	1		T240	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T137	2		T241	6		T212	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T26	2		T205	2		T54	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T20	7		T175	7		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	11		T121	9		T122	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1101	1			T13	13		T19	20		T32	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T127	14		T256	7		T156	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T13	3		T156	12		T181	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	13		T131	12		T24	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	2		T121	4		T246	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	8		T16	1		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T136	10		T234	8		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T4	8		T16	1		T258	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	11		T11	3		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T1	10		T7	2		T24	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13