Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	1		T121	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	11		T121	1		T258	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T13	15		T129	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T2	1		T11	1		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T17	2		T24	10		T264	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	1		T126	4		T255	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T5	3		T11	1		T86	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	8		T169	1		T127	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	3		T178	1		T16	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T24	12		T123	3		T244	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T18	1		T178	1		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	1		T17	1		T209	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T148	15		T32	2		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T151	9		T234	1		T243	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	14		T131	13		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	1		T178	1		T209	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	1		T7	3		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T2	1		T4	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T130	1		T162	1		T26	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T20	10		T265	8		T229	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	7		T121	9		T122	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	11		T121	4		T258	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	6		T13	13		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	12		T79	12		T274	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T24	10		T205	2		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	11		T255	11		T212	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1103	1			T11	8		T19	20		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T15	2		T266	12		T275	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T16	1		T140	10		T276	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T24	9		T127	13		T240	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T18	1		T16	4		T277	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T4	17		T270	1		T278	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T246	3		T241	6		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T151	8		T234	8		T125	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T10	13		T131	12		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	10		T133	2		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T4	4		T7	2		T11	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	8		T13	3		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T26	2		T254	18		T79	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T20	7		T155	12		T47	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T10	2		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T260	1		T261	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T262	11		T272	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T121	1		T263	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T13	15		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	1		T258	1		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T129	1		T209	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T7	11		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T17	1		T231	1		T205	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T12	1		T126	4		T212	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T5	3		T11	1		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T15	8		T24	12		T123	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	6		T123	7		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T4	1		T244	11		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	3		T18	1		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T17	1		T209	14		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T178	1		T16	2		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T234	1		T243	12		T125	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T10	14		T148	15		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T1	1		T13	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	390	1			T4	1		T7	3		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T2	1		T4	1		T18	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T261	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T262	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T121	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T12	7		T13	13		T121	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	12		T258	4		T127	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	6		T122	8		T205	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	11		T279	6		T255	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T205	2		T137	2		T247	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	11		T212	1		T274	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T11	8		T19	20		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	2		T24	9		T73	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	4		T139	2		T276	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T4	17		T278	7		T213	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T18	1		T16	1		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T127	13		T240	9		T141	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	1		T246	3		T241	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T234	8		T125	2		T270	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T10	13		T122	10		T244	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	10		T13	3		T151	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T4	4		T7	2		T11	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	8		T18	1		T20	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13