Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21474

1

T1

11

T3

20

T5

3

auto[ADC_CTRL_FILTER_COND_OUT]

3340

1

T1

7

T2

2

T4

32

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19189

1

T3

20

T4

14

T6

17

auto[1]

5625

1

T1

18

T2

2

T4

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T280	1		T172	13		-	-
values[0]	84	1			T256	8		T174	11		T281	19
values[1]	637	1			T162	2		T234	9		T123	14
values[2]	720	1			T7	22		T12	12		T13	4
values[3]	835	1			T1	18		T10	27		T11	13
values[4]	645	1			T2	2		T11	9		T17	1
values[5]	2837	1			T4	9		T5	3		T18	2
values[6]	493	1			T12	3		T15	2		T178	1
values[7]	391	1			T7	5		T10	2		T13	28
values[8]	817	1			T4	18		T7	3		T209	11
values[9]	1152	1			T4	5		T11	4		T12	8
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	939	1			T13	4		T162	2		T32	36
values[1]	560	1			T7	22		T10	27		T12	12
values[2]	930	1			T1	11		T2	1		T11	13
values[3]	2679	1			T1	7		T2	1		T5	3
values[4]	794	1			T4	9		T130	1		T148	15
values[5]	380	1			T12	3		T13	28		T15	2
values[6]	610	1			T4	18		T7	8		T10	2
values[7]	722	1			T209	11		T16	3		T151	17
values[8]	749	1			T12	8		T20	17		T136	20
values[9]	242	1			T4	5		T11	4		T15	8
minimum	16209	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T32	17		T134	1		T151	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	4		T162	2		T205	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	1		T178	1		T121	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	12		T10	14		T12	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	11		T11	13		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	1		T175	8		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T5	3		T17	1		T18	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	7		T2	1		T11	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T130	1		T148	1		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	9		T16	6		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T12	3		T16	4		T32	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	14		T15	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	1		T122	11		T282	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	18		T7	3		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T16	2		T138	1		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T209	1		T151	9		T205	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T20	8		T136	11		T32	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	8		T232	1		T258	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T236	12		T284	7		T73	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T4	5		T11	4		T15	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16061	1			T3	20		T6	17		T8	192
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T32	19		T134	9		T151	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T205	4		T123	13		T199	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T246	2		T244	5		T54	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T7	10		T10	13		T209	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T209	13		T131	12		T126	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T175	9		T133	6		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T87	24		T242	15		T142	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T208	4		T24	11		T133	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T148	14		T26	8		T124	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	4		T243	11		T123	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T16	1		T32	2		T125	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T13	14		T15	1		T151	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	2		T122	12		T235	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	2		T10	1		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T16	1		T155	4		T268	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T209	10		T151	8		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T20	9		T136	9		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T139	11		T265	9		T276	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T236	12		T284	5		T73	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T15	2		T123	6		T125	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T112	2		T16	1		T118	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T172	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T256	8		T281	8		T285	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T174	11		T286	1		T287	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T234	9		T244	1		T265	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T162	2		T123	1		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T17	1		T121	10		T32	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	12		T12	12		T13	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	11		T11	13		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T1	7		T10	14		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T17	1		T18	3		T24	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	2		T11	9		T121	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T5	3		T18	2		T86	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	9		T129	1		T208	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T12	3		T16	4		T32	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T15	1		T178	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T122	11		T282	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	3		T10	1		T13	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T7	1		T136	11		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	18		T209	1		T151	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T20	8		T16	2		T32	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T4	5		T11	4		T12	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T172	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T281	11		T285	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T286	9		T287	1		T288	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T244	10		T265	7		T238	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T123	13		T199	5		T127	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T32	19		T134	9		T151	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	10		T209	9		T289	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T209	13		T131	12		T126	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	13		T139	2		T269	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T24	9		T122	9		T269	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T24	11		T175	9		T133	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1065	1			T87	24		T242	15		T142	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T208	4		T16	4		T127	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T16	1		T32	2		T125	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	1		T243	11		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T122	12		T235	2		T253	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T7	2		T10	1		T13	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	2		T136	9		T155	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T209	10		T151	8		T205	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T20	9		T16	1		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T15	2		T123	6		T125	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T32	20		T134	10		T151	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T13	1		T162	2		T205	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	1		T178	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	11		T10	14		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	1		T11	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	1		T175	10		T133	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T5	3		T17	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	1		T2	1		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T130	1		T148	15		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T4	1		T16	6		T243	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	1		T16	4		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	15		T15	2		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	3		T122	13		T282	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T4	1		T7	3		T10	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T16	2		T138	1		T283	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T209	11		T151	9		T205	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T20	10		T136	10		T32	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T232	1		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T236	13		T284	6		T73	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T4	1		T11	1		T15	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16202	1			T3	20		T6	17		T8	192
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T32	16		T151	4		T234	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	3		T205	2		T279	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T121	9		T246	3		T244	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	11		T10	13		T12	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	10		T11	12		T18	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T175	7		T133	2		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T18	1		T19	20		T163	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	6		T11	8		T208	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T26	2		T141	12		T186	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	8		T16	4		T127	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T12	2		T16	1		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	13		T151	7		T237	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T122	10		T235	3		T253	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	17		T7	2		T278	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T16	1		T155	4		T268	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T151	8		T205	2		T241	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T20	7		T136	10		T137	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	7		T258	12		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T236	11		T284	6		T73	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T4	4		T11	3		T15	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T281	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T172	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T280	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T256	1		T281	12		T285	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T174	1		T286	10		T287	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T234	1		T244	11		T265	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T162	2		T123	14		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T17	1		T121	1		T32	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	11		T12	1		T13	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	1		T11	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	1		T10	14		T231	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T17	1		T18	2		T24	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T2	2		T11	1		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1417	1			T5	3		T18	1		T86	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T4	1		T129	1		T208	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T12	1		T16	4		T32	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	2		T178	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T122	13		T282	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	3		T10	2		T13	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	3		T136	10		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	1		T209	11		T151	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T20	10		T16	2		T32	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T4	1		T11	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T256	7		T281	7		T285	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T174	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T234	8		T238	10		T275	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T279	6		T127	14		T214	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T121	9		T32	16		T151	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	11		T12	11		T13	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	10		T11	12		T131	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	6		T10	13		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T18	1		T24	10		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	8		T121	4		T24	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1054	1			T18	1		T19	20		T163	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	8		T208	4		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T12	2		T16	1		T32	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T237	12		T247	11		T259	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T122	10		T235	3		T253	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	2		T13	13		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T136	10		T155	4		T268	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	17		T151	8		T205	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T20	7		T16	1		T137	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T4	4		T11	3		T12	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13