Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19527

1

T1

18

T3

20

T4

5

auto[ADC_CTRL_FILTER_COND_OUT]

5287

1

T2

2

T4

27

T5

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18900

1

T2

1

T3

20

T6

17

auto[1]

5914

1

T1

18

T2

1

T4

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	341	1			T13	4		T17	1		T178	1
values[0]	1	1			T290	1		-	-		-	-
values[1]	610	1			T4	23		T7	5		T11	4
values[2]	788	1			T178	1		T16	5		T32	36
values[3]	557	1			T2	1		T10	27		T11	9
values[4]	730	1			T1	7		T7	22		T12	15
values[5]	727	1			T10	2		T18	2		T130	2
values[6]	494	1			T12	8		T17	1		T209	10
values[7]	658	1			T1	11		T2	1		T4	9
values[8]	694	1			T11	13		T15	10		T148	15
values[9]	3025	1			T5	3		T7	3		T17	1
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	715	1			T4	18		T7	5		T13	28
values[1]	2753	1			T2	1		T4	5		T5	3
values[2]	665	1			T1	7		T10	27		T11	9
values[3]	750	1			T7	22		T12	15		T18	2
values[4]	656	1			T12	8		T17	1		T130	1
values[5]	515	1			T10	2		T209	10		T162	1
values[6]	685	1			T1	11		T2	1		T4	9
values[7]	737	1			T7	3		T11	13		T17	1
values[8]	896	1			T17	1		T18	3		T129	1
values[9]	175	1			T13	4		T247	22		T141	32
minimum	16267	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	3		T209	1		T16	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	18		T13	14		T16	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	5		T178	1		T32	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1371	1			T2	1		T5	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T1	7		T11	9		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	14		T209	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	12		T18	2		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	15		T133	3		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T12	8		T162	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	1		T130	1		T24	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T209	1		T162	1		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	1		T246	9		T125	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	11		T20	8		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T4	9		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	7		T148	1		T234	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	1		T11	13		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T18	3		T129	1		T208	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T17	1		T178	1		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T247	12		T141	13		T45	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T13	4		T291	1		T292	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16063	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T11	4		T127	1		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	2		T209	10		T16	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	14		T16	1		T122	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T32	19		T244	5		T255	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	975	1			T87	24		T242	15		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T235	2		T255	3		T277	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	13		T209	13		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	10		T24	11		T175	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T133	6		T293	2		T56	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T289	3		T205	2		T270	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T24	9		T151	8		T199	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T209	9		T237	2		T125	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	1		T246	2		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T20	9		T134	9		T265	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T241	8		T125	11		T126	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	3		T148	14		T123	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	2		T32	2		T126	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T208	4		T243	11		T190	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T131	12		T136	9		T133	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T247	10		T141	19		T45	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T291	6		T292	2		T294	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T127	1		T295	5		T285	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T132	1		T243	1		T211	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T13	4		T17	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T290	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	5		T7	3		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	18		T11	4		T13	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T178	1		T32	17		T244	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T16	4		T124	1		T247	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	9		T178	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	1		T10	14		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	7		T7	12		T205	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	15		T169	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T18	2		T130	1		T24	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	1		T130	1		T24	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	8		T209	1		T162	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	1		T151	9		T125	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	11		T20	8		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	1		T4	9		T246	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T15	7		T148	1		T123	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	13		T32	12		T258	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T18	3		T129	1		T208	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1507	1			T5	3		T7	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T243	11		T247	10		T240	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T262	5		T157	12		T291	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	2		T209	10		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	14		T16	1		T122	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T32	19		T244	5		T127	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T16	1		T124	7		T247	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T235	2		T255	3		T277	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	13		T209	13		T127	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	10		T205	4		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T171	7		T296	11		T56	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T24	11		T175	9		T205	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T10	1		T24	9		T133	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T209	9		T289	3		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T151	8		T125	10		T199	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T20	9		T134	9		T265	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T246	2		T125	11		T126	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T15	3		T148	14		T123	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T32	2		T241	8		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T208	4		T284	5		T212	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1143	1			T7	2		T87	24		T242	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	3		T209	11		T16	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T4	1		T13	15		T16	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	1		T178	1		T32	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1325	1			T2	1		T5	3		T86	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	1		T11	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	14		T209	14		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T7	11		T18	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	2		T133	7		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	1		T162	1		T264	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T17	1		T130	1		T24	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T209	10		T162	1		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	2		T246	8		T125	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	1		T20	10		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T2	1		T4	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T15	8		T148	15		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	3		T11	1		T17	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T18	2		T129	1		T208	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T17	1		T178	1		T131	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T247	11		T141	20		T45	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T13	1		T291	7		T292	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16202	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T11	1		T127	2		T203	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	2		T16	4		T26	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	17		T13	13		T16	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	4		T32	16		T244	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1021	1			T19	20		T16	1		T163	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	6		T11	8		T137	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	13		T127	13		T277	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	11		T18	1		T24	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	13		T133	2		T56	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	7		T289	13		T205	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T24	10		T151	8		T278	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T237	12		T54	2		T297	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T246	3		T125	10		T254	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	10		T20	7		T278	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	8		T258	5		T241	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T15	2		T234	8		T284	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	12		T32	11		T155	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T18	1		T208	4		T121	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T131	12		T136	10		T121	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T247	11		T141	12		T45	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T13	3		T294	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T230	2		T298	2		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T11	3		T295	6		T285	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T132	1		T243	12		T211	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T13	1		T17	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T290	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	1		T7	3		T209	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	1		T11	1		T13	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T178	1		T32	20		T244	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T16	4		T124	8		T247	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	1		T178	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	1		T10	14		T209	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T7	11		T205	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	2		T169	1		T171	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T18	1		T130	1		T24	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	2		T130	1		T24	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	1		T209	10		T162	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T17	1		T151	9		T125	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T20	10		T134	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T2	1		T4	1		T246	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	8		T148	15		T123	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	1		T32	3		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T18	2		T129	1		T208	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1516	1			T5	3		T7	3		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T247	11		T240	12		T141	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T13	3		T262	5		T299	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T4	4		T7	2		T16	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	17		T11	3		T13	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T32	16		T244	2		T127	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T16	1		T247	4		T276	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	8		T235	3		T255	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T10	13		T127	13		T141	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	6		T7	11		T205	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	13		T300	10		T56	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T18	1		T24	9		T175	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T24	10		T133	2		T278	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	7		T289	13		T237	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T151	8		T125	10		T254	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T1	10		T20	7		T73	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	8		T246	3		T125	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T15	2		T278	10		T268	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	12		T32	11		T258	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T18	1		T208	4		T121	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1134	1			T19	20		T131	12		T136	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13