Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21191

1

T2

1

T3

20

T4

14

auto[ADC_CTRL_FILTER_COND_OUT]

3623

1

T1

18

T2

1

T4

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19224

1

T1

18

T2

1

T3

20

auto[1]

5590

1

T2

1

T4

5

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	4	1			T15	2		T301	1		T302	1
values[0]	44	1			T121	5		T199	6		T214	11
values[1]	564	1			T13	4		T130	1		T178	2
values[2]	759	1			T2	1		T4	9		T7	22
values[3]	600	1			T11	13		T18	2		T16	10
values[4]	852	1			T4	5		T7	5		T10	2
values[5]	698	1			T12	3		T17	2		T209	10
values[6]	586	1			T1	7		T2	1		T178	1
values[7]	613	1			T1	11		T10	27		T11	4
values[8]	732	1			T4	18		T7	3		T130	1
values[9]	3173	1			T5	3		T11	9		T17	1
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	815	1			T4	9		T13	4		T20	17
values[1]	648	1			T2	1		T7	22		T11	13
values[2]	633	1			T18	2		T16	10		T24	20
values[3]	924	1			T4	5		T7	5		T10	2
values[4]	624	1			T17	2		T208	9		T32	2
values[5]	625	1			T1	7		T2	1		T12	12
values[6]	2634	1			T1	11		T5	3		T10	27
values[7]	825	1			T4	18		T7	3		T209	11
values[8]	716	1			T11	9		T17	1		T18	3
values[9]	152	1			T240	23		T254	15		T79	22
minimum	16218	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	9		T130	1		T131	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	4		T20	8		T178	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T2	1		T246	9		T62	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	12		T11	13		T12	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T24	11		T132	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T18	2		T16	6		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	5		T10	1		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T7	3		T12	3		T13	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T208	5		T32	1		T151	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T17	2		T175	8		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T178	1		T134	1		T151	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T1	7		T2	1		T12	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T5	3		T11	4		T86	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	11		T10	14		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	1		T209	1		T133	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T4	18		T133	3		T205	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	9		T17	1		T18	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T129	1		T15	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T303	1		T304	10		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T240	13		T254	15		T79	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16055	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T250	12		T193	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T131	12		T244	10		T125	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T20	9		T123	13		T124	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T246	2		T293	2		T276	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	10		T26	8		T122	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T24	9		T127	13		T306	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T16	4		T123	6		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	1		T209	9		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	2		T13	14		T32	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T208	4		T32	1		T151	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T175	9		T190	12		T155	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T134	9		T151	8		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T122	12		T124	7		T154	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T87	24		T242	15		T209	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T10	13		T16	1		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	2		T209	10		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T133	6		T205	4		T79	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T15	2		T16	1		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T15	1		T148	14		T32	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T250	9		T307	11		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T240	10		T79	9		T308	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T250	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T15	1		T301	1		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T121	5		T199	1		T309	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T214	7		T310	1		T311	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T130	1		T162	1		T244	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	4		T178	2		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	1		T4	9		T131	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	12		T12	8		T20	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T132	1		T169	1		T127	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T11	13		T18	2		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	5		T10	1		T208	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T7	3		T13	14		T32	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T209	1		T136	11		T32	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	3		T17	2		T234	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T178	1		T134	1		T151	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	7		T2	1		T175	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	4		T209	1		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T1	11		T10	14		T12	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	1		T24	10		T151	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	18		T130	1		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1449	1			T5	3		T11	9		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T129	1		T148	1		T32	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T15	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T199	5		T309	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T214	4		T311	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T244	10		T125	11		T235	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T124	7		T126	3		T202	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T131	12		T24	9		T246	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	10		T20	9		T26	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T127	13		T48	5		T274	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T16	4		T240	9		T268	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	1		T208	4		T269	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	2		T13	14		T32	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T209	9		T136	9		T32	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T125	10		T54	1		T255	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T134	9		T151	2		T190	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T175	9		T122	12		T124	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T209	13		T151	8		T289	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T10	13		T123	2		T155	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	2		T24	11		T151	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T16	1		T133	6		T79	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1104	1			T87	24		T242	15		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T148	14		T32	19		T243	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T4	1		T130	1		T131	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T13	1		T20	10		T178	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T2	1		T246	8		T62	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	11		T11	1		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T24	10		T132	1		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T18	1		T16	6		T123	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T4	1		T10	2		T209	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	3		T12	1		T13	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T208	5		T32	2		T151	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	2		T175	10		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T178	1		T134	10		T151	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T2	1		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T5	3		T11	1		T86	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T1	1		T10	14		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	3		T209	11		T133	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T4	1		T133	7		T205	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	1		T17	1		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T129	1		T15	2		T148	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T303	1		T304	1		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T240	11		T254	1		T79	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16192	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T250	12		T193	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	8		T131	12		T121	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	3		T20	7		T258	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T246	3		T259	17		T276	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	11		T11	12		T12	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T24	10		T127	13		T254	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T18	1		T16	4		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	4		T136	10		T279	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	2		T12	2		T13	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T208	4		T151	4		T244	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T175	7		T234	8		T278	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T151	8		T237	12		T277	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	6		T12	11		T122	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T11	3		T19	20		T163	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	10		T10	13		T121	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T133	7		T151	7		T289	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T4	17		T133	2		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	8		T18	1		T15	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T32	16		T241	6		T54	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T304	9		T312	14		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T240	12		T254	14		T79	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T309	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T250	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T15	2		T301	1		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T121	1		T199	6		T309	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T214	8		T310	1		T311	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T130	1		T162	1		T244	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	1		T178	2		T124	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	1		T4	1		T131	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T7	11		T12	1		T20	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T132	1		T169	1		T127	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	1		T18	1		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	1		T10	2		T208	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T7	3		T13	15		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T209	10		T136	10		T32	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	1		T17	2		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T178	1		T134	10		T151	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	1		T2	1		T175	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	1		T209	14		T162	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	1		T10	14		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	3		T24	12		T151	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T4	1		T130	1		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1487	1			T5	3		T11	1		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T129	1		T148	15		T32	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T121	4		T309	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T214	3		T311	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T125	2		T235	3		T47	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	3		T258	4		T202	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	8		T131	12		T24	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	11		T12	7		T20	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T127	13		T274	9		T313	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	12		T18	1		T16	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	4		T208	4		T279	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	2		T13	13		T32	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T136	10		T237	12		T244	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T12	2		T234	8		T125	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T151	4		T314	1		T52	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T1	6		T175	7		T122	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	3		T151	8		T289	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	10		T10	13		T12	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T24	9		T151	7		T278	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	17		T16	1		T133	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1066	1			T11	8		T18	1		T19	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T32	16		T205	2		T241	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13