Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21448

1

T1

11

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3366

1

T1

7

T2

1

T4

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18980

1

T1

18

T3

20

T4

27

auto[1]

5834

1

T2

2

T4

5

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	35	1			T12	12		T313	14		T315	9
values[0]	56	1			T228	9		T316	1		T161	18
values[1]	720	1			T1	7		T10	27		T18	5
values[2]	734	1			T2	2		T12	3		T13	4
values[3]	666	1			T4	5		T12	8		T130	1
values[4]	616	1			T7	5		T20	17		T15	8
values[5]	690	1			T7	3		T13	28		T178	1
values[6]	542	1			T4	27		T17	1		T178	1
values[7]	704	1			T11	13		T130	1		T136	20
values[8]	2647	1			T5	3		T10	2		T17	1
values[9]	1215	1			T1	11		T7	22		T11	13
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	968	1			T1	7		T10	27		T12	3
values[1]	701	1			T2	2		T12	8		T148	15
values[2]	583	1			T4	5		T178	1		T208	9
values[3]	758	1			T7	5		T13	28		T20	17
values[4]	578	1			T7	3		T17	1		T178	1
values[5]	676	1			T4	27		T11	13		T136	20
values[6]	2675	1			T5	3		T86	2		T87	27
values[7]	679	1			T10	2		T17	1		T129	1
values[8]	740	1			T1	11		T7	22		T11	13
values[9]	253	1			T12	12		T151	17		T264	1
minimum	16203	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T12	3		T18	5		T32	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T1	7		T10	14		T13	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T24	11		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T12	8		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	5		T178	1		T208	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T168	1		T232	1		T199	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	3		T130	1		T15	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	14		T20	8		T131	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T231	1		T237	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T17	1		T178	1		T209	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T133	3		T234	9		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	27		T11	13		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T5	3		T86	2		T87	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T132	1		T264	1		T258	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	1		T121	10		T293	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T17	1		T129	1		T26	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	11		T11	9		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	12		T11	4		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T12	12		T141	7		T313	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T151	9		T264	1		T127	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T317	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T32	2		T244	10		T127	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T10	13		T15	1		T209	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T24	9		T151	2		T194	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T148	14		T122	9		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T208	4		T205	2		T124	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T199	5		T236	12		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	2		T15	2		T209	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	14		T20	9		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	2		T237	2		T126	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T209	10		T16	4		T205	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T133	6		T155	9		T268	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T136	9		T139	11		T256	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T87	24		T242	15		T142	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T318	11		T296	11		T275	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	1		T293	2		T240	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T26	8		T289	3		T125	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	1		T123	2		T270	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	10		T16	1		T24	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T141	7		T319	14		T216	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T151	8		T127	13		T172	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T12	12		T313	14		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T315	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T316	1		T161	9		T320	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T228	9		T301	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T18	5		T32	12		T151	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	7		T10	14		T15	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T2	1		T12	3		T24	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T2	1		T13	4		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	5		T130	1		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	8		T168	1		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	3		T15	6		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T20	8		T123	1		T246	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T7	1		T231	1		T237	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	14		T178	1		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T178	1		T282	1		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	27		T17	1		T209	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T130	1		T133	3		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	13		T136	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T5	3		T10	1		T86	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T17	1		T129	1		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T1	11		T11	9		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	413	1			T7	12		T11	4		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T161	9		T320	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T32	2		T151	2		T127	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T10	13		T15	1		T209	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T24	9		T244	10		T194	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T148	14		T122	9		T202	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T208	4		T205	2		T124	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T54	1		T236	12		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	2		T15	2		T209	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T20	9		T123	13		T246	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	2		T237	2		T255	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	14		T131	12		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T262	10		T251	10		T182	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T209	10		T256	4		T46	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T133	6		T134	9		T284	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T136	9		T139	11		T48	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T10	1		T87	24		T242	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T16	1		T26	8		T125	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T16	1		T123	2		T270	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T7	10		T24	11		T175	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	1		T18	3		T32	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T1	1		T10	14		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	1		T24	10		T151	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T2	1		T12	1		T148	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	1		T178	1		T208	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T168	1		T232	1		T199	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T7	3		T130	1		T15	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	15		T20	10		T131	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	3		T231	1		T237	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	1		T178	1		T209	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T133	7		T234	1		T282	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T4	2		T11	1		T136	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1411	1			T5	3		T86	2		T87	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T132	1		T264	1		T258	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T10	2		T121	1		T293	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T17	1		T129	1		T26	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T11	1		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	11		T11	1		T17	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T12	1		T141	8		T313	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T151	9		T264	1		T127	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T317	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	2		T18	2		T32	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	6		T10	13		T13	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T24	10		T151	4		T258	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	7		T122	8		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	4		T208	4		T121	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T236	11		T139	2		T141	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	2		T15	2		T32	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	13		T20	7		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T237	12		T258	5		T54	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T16	4		T205	2		T125	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T133	2		T234	8		T278	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	25		T11	12		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1041	1			T19	20		T163	22		T135	22
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T258	4		T321	15		T257	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T121	9		T240	9		T253	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T26	2		T289	13		T256	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T1	10		T11	8		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	11		T11	3		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T12	11		T141	6		T313	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T151	8		T127	13		T254	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T317	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T12	1		T313	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T315	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T316	1		T161	10		T320	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T228	1		T301	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T18	3		T32	3		T151	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T10	14		T15	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	1		T12	1		T24	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T2	1		T13	1		T148	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	1		T130	1		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T168	1		T232	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	3		T15	6		T209	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T20	10		T123	14		T246	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	3		T231	1		T237	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	15		T178	1		T131	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T178	1		T282	1		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	2		T17	1		T209	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T130	1		T133	7		T134	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	1		T136	10		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1368	1			T5	3		T10	2		T86	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	1		T129	1		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T1	1		T11	1		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	408	1			T7	11		T11	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T12	11		T313	13		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T315	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T161	8		T320	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T228	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T18	2		T32	11		T151	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	6		T10	13		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T12	2		T24	10		T255	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	3		T122	8		T202	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	4		T208	4		T205	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T12	7		T54	1		T236	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	2		T15	2		T121	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T20	7		T246	3		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T237	12		T258	5		T54	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	13		T131	12		T16	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T278	10		T262	11		T313	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	25		T258	4		T300	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T133	2		T234	8		T284	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T11	12		T136	10		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T19	20		T121	9		T163	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T16	1		T26	2		T254	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	10		T11	8		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T7	11		T11	3		T24	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13