Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21055

1

T1

11

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3759

1

T1

7

T2

1

T4

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19192

1

T1

7

T2

2

T3

20

auto[1]

5622

1

T1

11

T4

27

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	460	1			T2	1		T11	9		T32	2
values[0]	4	1			T276	2		T179	1		T322	1
values[1]	628	1			T12	8		T20	17		T15	2
values[2]	2700	1			T5	3		T10	2		T86	2
values[3]	731	1			T13	4		T130	1		T209	14
values[4]	738	1			T4	18		T7	25		T12	3
values[5]	761	1			T32	14		T26	15		T246	11
values[6]	547	1			T17	1		T18	2		T130	1
values[7]	621	1			T4	5		T10	27		T11	13
values[8]	691	1			T1	18		T7	5		T17	1
values[9]	744	1			T2	1		T4	9		T11	4
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	573	1			T12	8		T20	17		T121	10
values[1]	2646	1			T5	3		T10	2		T86	2
values[2]	757	1			T7	3		T12	3		T13	4
values[3]	800	1			T4	18		T7	22		T13	28
values[4]	677	1			T32	14		T26	15		T246	11
values[5]	603	1			T17	1		T18	2		T130	1
values[6]	611	1			T4	5		T10	27		T11	13
values[7]	648	1			T1	18		T2	1		T7	5
values[8]	851	1			T4	9		T11	13		T129	1
values[9]	236	1			T2	1		T12	12		T239	9
minimum	16412	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T20	8		T121	10		T122	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	8		T24	11		T244	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T5	3		T86	2		T87	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	1		T162	1		T175	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	3		T13	4		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	1		T122	11		T258	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	12		T178	1		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T4	18		T13	14		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T32	12		T246	9		T237	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T26	7		T232	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T17	1		T130	1		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T18	2		T231	1		T151	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	14		T11	13		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T4	5		T18	3		T121	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	11		T2	1		T17	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	7		T7	3		T133	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	9		T11	13		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T129	1		T208	5		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T12	12		T239	1		T276	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T2	1		T323	1		T203	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16123	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T136	11		T190	1		T180	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T20	9		T122	9		T213	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T24	9		T244	14		T255	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T87	24		T242	15		T142	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	1		T175	9		T289	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T209	13		T16	4		T244	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	2		T122	12		T241	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	10		T131	12		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	14		T15	2		T209	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T32	2		T246	2		T237	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	8		T194	6		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T126	3		T73	5		T45	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T151	2		T123	13		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	13		T133	6		T134	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T16	1		T32	19		T125	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T124	7		T139	2		T293	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	2		T133	7		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T171	2		T48	5		T324	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T208	4		T209	9		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T239	8		T276	16		T157	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T325	11		T326	11		T327	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T112	2		T15	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T136	9		T190	9		T180	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	9		T234	9		T239	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	1		T32	1		T151	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T276	1		T179	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T322	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T20	8		T15	1		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	8		T136	11		T244	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T5	3		T86	2		T87	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	1		T162	1		T24	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	4		T130	1		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T175	8		T258	6		T241	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T7	12		T12	3		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	18		T7	1		T13	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T32	12		T246	9		T237	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T26	7		T128	1		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T17	1		T130	1		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T18	2		T151	5		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T10	14		T11	13		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T4	5		T121	5		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	11		T17	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	7		T7	3		T18	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T2	1		T4	9		T11	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T129	1		T208	5		T209	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T239	8		T276	16		T157	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T32	1		T151	8		T123	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T276	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T20	9		T15	1		T122	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T136	9		T244	14		T190	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T87	24		T242	15		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	1		T24	9		T289	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T209	13		T244	5		T212	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T175	9		T241	8		T273	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	10		T131	12		T16	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	2		T13	14		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T32	2		T246	2		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T26	8		T247	14		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T126	3		T45	7		T281	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T151	2		T123	13		T125	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T10	13		T133	6		T134	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T16	1		T32	19		T125	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T124	7		T139	2		T265	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	2		T243	11		T236	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T171	2		T48	5		T267	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T208	4		T209	9		T133	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T20	10		T121	1		T122	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	1		T24	10		T244	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T5	3		T86	2		T87	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	2		T162	1		T175	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	1		T13	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	3		T122	13		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	11		T178	1		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T4	1		T13	15		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T32	3		T246	8		T237	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T26	13		T232	1		T194	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T17	1		T130	1		T225	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T18	1		T231	1		T151	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T10	14		T11	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	1		T18	2		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	1		T2	1		T17	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T7	3		T133	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T4	1		T11	2		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T129	1		T208	5		T209	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T12	1		T239	9		T276	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T2	1		T323	1		T203	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16277	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T136	10		T190	10		T180	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T20	7		T121	9		T122	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	7		T24	10		T255	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T19	20		T163	22		T135	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T175	7		T289	13		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T12	2		T13	3		T16	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T122	10		T258	5		T241	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	11		T131	12		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	17		T13	13		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T32	11		T246	3		T237	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T26	2		T253	9		T79	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T73	3		T53	2		T275	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T18	1		T151	4		T258	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	13		T11	12		T133	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T4	4		T18	1		T121	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T1	10		T139	2		T267	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	6		T7	2		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T4	8		T11	11		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T208	4		T151	8		T127	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T12	11		T276	17		T157	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T325	13		T328	13		T326	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T276	15		T329	9		T74	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T136	10		T330	2		T331	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T11	1		T234	1		T239	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	1		T32	2		T151	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T276	2		T179	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T322	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T20	10		T15	2		T178	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	1		T136	10		T244	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T5	3		T86	2		T87	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	2		T162	1		T24	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	1		T130	1		T209	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T175	10		T258	1		T241	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T7	11		T12	1		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	1		T7	3		T13	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T32	3		T246	8		T237	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T26	13		T128	1		T62	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T17	1		T130	1		T126	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T18	1		T151	3		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T10	14		T11	1		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	1		T121	1		T16	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	1		T17	1		T124	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T7	3		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T2	1		T4	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T129	1		T208	5		T209	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T11	8		T234	8		T276	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T151	8		T240	8		T45	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T20	7		T121	9		T122	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	7		T136	10		T140	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T19	20		T163	22		T135	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T24	10		T289	13		T54	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T13	3		T244	2		T258	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T175	7		T258	5		T241	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	11		T12	2		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T4	17		T13	13		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T32	11		T246	3		T237	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T26	2		T247	4		T240	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T47	2		T230	10		T328	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T18	1		T151	4		T258	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	13		T11	12		T133	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T4	4		T121	4		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T1	10		T139	2		T332	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	6		T7	2		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	8		T11	3		T12	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T208	4		T133	7		T127	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13