Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21026

1

T1

11

T2

1

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3788

1

T1

7

T2

1

T4

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19250

1

T1

7

T2

2

T3

20

auto[1]

5564

1

T1

11

T4

27

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	41	1			T151	17		T239	9		T254	15
values[0]	72	1			T15	2		T140	11		T141	14
values[1]	509	1			T12	8		T20	17		T178	1
values[2]	2712	1			T5	3		T10	2		T86	2
values[3]	781	1			T13	4		T130	1		T209	14
values[4]	737	1			T4	18		T7	25		T12	3
values[5]	678	1			T26	15		T264	1		T246	11
values[6]	620	1			T4	5		T17	1		T18	2
values[7]	611	1			T10	27		T121	5		T16	3
values[8]	674	1			T1	18		T7	5		T11	13
values[9]	1190	1			T2	2		T4	9		T11	13
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	770	1			T12	8		T20	17		T15	2
values[1]	2678	1			T5	3		T10	2		T86	2
values[2]	722	1			T7	3		T12	3		T13	4
values[3]	805	1			T4	18		T7	22		T13	28
values[4]	679	1			T32	14		T26	15		T246	11
values[5]	635	1			T10	27		T17	1		T18	2
values[6]	575	1			T4	5		T11	13		T121	5
values[7]	695	1			T1	18		T2	1		T17	2
values[8]	790	1			T2	1		T4	9		T7	5
values[9]	264	1			T12	12		T211	1		T239	9
minimum	16201	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T20	8		T15	1		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	8		T136	11		T24	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T5	3		T86	2		T87	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T162	1		T175	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	3		T13	4		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	1		T122	11		T258	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	12		T178	1		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T4	18		T13	14		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T32	12		T246	9		T237	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T26	7		T232	1		T194	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T10	14		T17	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T18	2		T231	1		T151	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	13		T133	3		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	5		T121	5		T32	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	11		T2	1		T17	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	7		T18	3		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	9		T11	13		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T2	1		T7	3		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T12	12		T211	1		T239	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T296	1		T323	1		T203	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T295	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T20	9		T15	1		T122	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T136	9		T24	9		T244	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T87	24		T242	15		T142	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	1		T175	9		T289	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T209	13		T16	4		T244	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	2		T122	12		T241	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	10		T131	12		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	14		T15	2		T209	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T32	2		T246	2		T237	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T26	8		T194	6		T269	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	13		T151	5		T126	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T151	2		T123	13		T125	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T133	6		T134	9		T123	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T32	19		T125	10		T127	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T124	7		T139	2		T265	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T209	9		T16	1		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T171	2		T48	5		T324	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	2		T208	4		T32	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T239	8		T276	16		T333	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T296	11		T56	5		T329	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T295	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T239	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T151	9		T254	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T15	1		T141	7		T276	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T140	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T20	8		T178	1		T121	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	8		T136	11		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T5	3		T86	2		T87	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	1		T162	1		T24	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	4		T130	1		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T175	8		T289	14		T258	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	12		T12	3		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T4	18		T7	1		T13	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T246	9		T237	13		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T26	7		T264	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T17	1		T130	1		T32	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T4	5		T18	2		T151	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	14		T132	1		T133	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T121	5		T16	2		T32	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	11		T11	13		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	7		T7	3		T18	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T2	1		T4	9		T11	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	415	1			T2	1		T129	1		T208	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T239	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T151	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T15	1		T141	7		T276	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T20	9		T122	9		T126	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T136	9		T190	9		T155	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T87	24		T242	15		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	1		T24	9		T244	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T209	13		T244	5		T212	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T175	9		T289	3		T241	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	10		T131	12		T16	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	2		T13	14		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T246	2		T237	2		T202	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T26	8		T247	14		T240	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T32	2		T45	7		T281	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T151	2		T125	11		T194	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	13		T133	6		T134	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T16	1		T32	19		T123	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T124	7		T265	7		T332	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	2		T243	11		T236	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T139	2		T154	11		T276	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T208	4		T209	9		T32	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T20	10		T15	2		T178	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	1		T136	10		T24	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T5	3		T86	2		T87	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	2		T162	1		T175	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T13	1		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	3		T122	13		T258	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	11		T178	1		T131	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T4	1		T13	15		T15	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T32	3		T246	8		T237	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T26	13		T232	1		T194	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	14		T17	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T18	1		T231	1		T151	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	1		T133	7		T134	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T121	1		T32	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	1		T2	1		T17	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T1	1		T18	2		T209	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T4	1		T11	2		T162	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T2	1		T7	3		T129	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T12	1		T211	1		T239	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T296	12		T323	1		T203	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T295	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T20	7		T121	9		T122	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	7		T136	10		T24	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T19	20		T163	22		T135	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T175	7		T289	13		T54	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	2		T13	3		T16	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T122	10		T258	5		T241	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	11		T131	12		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	17		T13	13		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T32	11		T246	3		T237	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T26	2		T269	8		T253	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T10	13		T151	7		T270	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T18	1		T151	4		T125	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	12		T133	2		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T4	4		T121	4		T32	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T1	10		T139	2		T267	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	6		T18	1		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T4	8		T11	11		T234	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	2		T208	4		T151	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T12	11		T276	17		T174	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T56	4		T329	2		T328	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T295	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T239	9		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T151	9		T254	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T15	2		T141	8		T276	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T140	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T20	10		T178	1		T121	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	1		T136	10		T128	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T5	3		T86	2		T87	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T10	2		T162	1		T24	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	1		T130	1		T209	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T175	10		T289	4		T258	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	11		T12	1		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T4	1		T7	3		T13	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T246	8		T237	3		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T26	13		T264	1		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T17	1		T130	1		T32	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	1		T18	1		T151	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T10	14		T132	1		T133	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T121	1		T16	2		T32	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	1		T11	1		T124	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	1		T7	3		T18	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T2	1		T4	1		T11	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	451	1			T2	1		T129	1		T208	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T151	8		T254	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T141	6		T216	4		T334	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T140	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T20	7		T121	9		T122	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T12	7		T136	10		T155	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T19	20		T163	22		T135	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T24	10		T54	1		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	3		T244	2		T258	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T175	7		T289	13		T258	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	11		T12	2		T131	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T4	17		T13	13		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T246	3		T237	12		T202	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	2		T247	4		T240	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T32	11		T47	2		T335	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T4	4		T18	1		T151	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	13		T133	2		T151	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T121	4		T16	1		T32	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	10		T11	12		T332	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	6		T7	2		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T4	8		T11	11		T12	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T208	4		T133	7		T127	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13