Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24814

1

T1

18

T2

2

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21581

1

T1

7

T3

20

T4

5

auto[ADC_CTRL_FILTER_COND_OUT]

3233

1

T1

11

T2

2

T4

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19517

1

T2

2

T3

20

T4

14

auto[1]

5297

1

T1

18

T4

18

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20820

1

T1

18

T2

2

T3

20

auto[1]

3994

1

T7

14

T10

14

T13

14

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	376	1			T2	1		T12	3		T18	3
values[0]	26	1			T225	1		T336	23		T263	1
values[1]	586	1			T11	13		T121	15		T162	1
values[2]	653	1			T1	7		T2	1		T7	22
values[3]	647	1			T12	12		T17	1		T205	10
values[4]	2682	1			T5	3		T11	9		T17	1
values[5]	562	1			T4	18		T16	10		T123	7
values[6]	642	1			T7	3		T17	1		T18	2
values[7]	954	1			T178	1		T16	3		T32	2
values[8]	520	1			T1	11		T10	27		T178	1
values[9]	977	1			T4	14		T7	5		T10	2
minimum	16189	1			T3	20		T6	17		T8	192

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	501	1			T7	22		T12	8		T121	5
values[1]	810	1			T1	7		T2	1		T11	13
values[2]	522	1			T11	9		T12	12		T17	2
values[3]	2681	1			T5	3		T86	2		T87	27
values[4]	670	1			T7	3		T17	1		T16	10
values[5]	564	1			T4	18		T18	2		T178	1
values[6]	881	1			T148	15		T32	2		T132	1
values[7]	719	1			T1	11		T10	27		T178	1
values[8]	905	1			T2	1		T4	14		T7	5
values[9]	147	1			T20	17		T162	1		T26	15
minimum	16414	1			T3	20		T6	17		T8	192

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

3663

1

T1

16

T4

29

T7

13

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	8		T122	9		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	12		T121	5		T279	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	7		T13	14		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T2	1		T11	13		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	9		T17	2		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T12	12		T126	1		T212	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1436	1			T5	3		T86	2		T87	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T15	7		T24	10		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	1		T16	6		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T17	1		T244	1		T127	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T18	2		T178	1		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T4	18		T209	1		T264	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T148	1		T32	1		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T151	9		T234	9		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	14		T131	13		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	11		T178	1		T209	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T4	5		T7	3		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	1		T4	9		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T162	1		T26	7		T254	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T20	8		T155	13		T82	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16102	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T258	5		T225	1		T236	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T122	9		T267	11		T192	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	10		T127	13		T53	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	14		T209	9		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T134	9		T255	3		T239	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T205	4		T244	4		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T126	3		T212	1		T73	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T87	24		T242	15		T136	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	3		T24	11		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T7	2		T16	4		T123	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T244	10		T127	13		T240	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T16	1		T123	13		T126	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T209	13		T270	6		T141	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T148	14		T32	1		T246	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T151	8		T243	11		T124	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	13		T131	12		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T209	10		T133	6		T151	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	2		T10	1		T133	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T208	4		T175	9		T237	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T26	8		T79	7		T307	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T20	9		T155	2		T82	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T112	2		T16	1		T118	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T236	12		T273	8		T262	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T12	3		T133	8		T199	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	1		T18	3		T20	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T272	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T225	1		T336	13		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T121	10		T162	1		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	13		T121	5		T258	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	7		T12	8		T13	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	1		T7	12		T134	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T17	1		T205	6		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	12		T126	1		T212	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1401	1			T5	3		T11	9		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T15	7		T24	10		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	6		T123	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	18		T244	1		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	1		T18	2		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T17	1		T209	1		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T178	1		T16	2		T32	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T234	9		T243	1		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T10	14		T148	1		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	11		T178	1		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	357	1			T4	5		T7	3		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	9		T13	4		T208	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16052	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T133	7		T199	5		T54	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T20	9		T237	2		T247	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T336	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T267	11		T238	8		T262	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T127	13		T236	12		T273	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	14		T209	9		T122	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	10		T134	9		T255	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T205	4		T244	4		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T126	3		T212	1		T268	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T87	24		T242	15		T136	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	3		T24	11		T123	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	4		T123	6		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T244	10		T213	5		T141	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	2		T16	1		T126	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T209	13		T127	13		T240	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T16	1		T32	1		T123	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T243	11		T124	7		T125	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T10	13		T148	14		T122	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T209	10		T151	8		T125	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	2		T10	1		T131	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T208	4		T175	9		T133	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T112	2		T16	1		T118	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	1		T122	10		T264	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	11		T121	1		T279	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T13	15		T209	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	1		T11	1		T134	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	1		T17	2		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	1		T126	4		T212	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T5	3		T86	2		T87	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T15	8		T24	12		T123	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	3		T16	6		T123	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T17	1		T244	11		T127	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T18	1		T178	1		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T4	1		T209	14		T264	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T148	15		T32	2		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T151	9		T234	1		T243	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	14		T131	13		T16	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T178	1		T209	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T4	1		T7	3		T10	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	1		T4	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T162	1		T26	13		T254	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T20	10		T155	3		T82	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16262	1			T3	20		T6	17		T8	192
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T258	1		T225	1		T236	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T12	7		T122	8		T267	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	11		T121	4		T279	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	6		T13	13		T205	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	12		T255	11		T79	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	8		T205	2		T139	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T12	11		T212	1		T73	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1087	1			T19	20		T136	10		T163	22
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T15	2		T24	9		T257	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T16	4		T140	10		T276	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T127	13		T278	7		T240	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T18	1		T16	1		T277	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T4	17		T270	1		T141	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T246	3		T241	6		T54	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T151	8		T234	8		T125	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	13		T131	12		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	10		T133	2		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	4		T7	2		T11	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T4	8		T13	3		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T26	2		T254	18		T79	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T20	7		T155	12		T228	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T121	9		T238	10		T262	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T258	4		T236	11		T262	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	1		T133	8		T199	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	1		T18	2		T20	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T272	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T225	1		T336	11		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T121	1		T162	1		T264	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	1		T121	1		T258	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	1		T12	1		T13	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	1		T7	11		T134	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T17	1		T205	8		T244	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T126	4		T212	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T5	3		T11	1		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	8		T24	12		T123	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	6		T123	7		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	1		T244	11		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	3		T18	1		T16	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T17	1		T209	14		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T178	1		T16	2		T32	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T234	1		T243	12		T124	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	14		T148	15		T122	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T178	1		T209	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T4	1		T7	3		T10	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T4	1		T13	1		T208	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16189	1			T3	20		T6	17		T8	192
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T12	2		T133	7		T54	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T18	1		T20	7		T237	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T336	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T121	9		T267	12		T238	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	12		T121	4		T258	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	6		T12	7		T13	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	11		T279	6		T255	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T205	2		T139	11		T247	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	11		T212	1		T337	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T11	8		T19	20		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T15	2		T24	9		T73	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T16	4		T139	2		T276	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T4	17		T278	7		T213	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T18	1		T16	1		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T127	13		T240	9		T141	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T16	1		T246	3		T241	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T234	8		T125	2		T270	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T10	13		T122	10		T244	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	10		T151	8		T284	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T4	4		T7	2		T11	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T4	8		T13	3		T208	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21151

1

T1

2

T2

2

T3

20

auto[1]

auto[0]

3663

1

T1

16

T4

29

T7

13