Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.60 98.98 95.69 100.00 100.00 98.18 98.64 91.72


Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T27 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1187002195 Feb 29 12:56:58 PM PST 24 Feb 29 12:57:35 PM PST 24 51207311858 ps
T790 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3855147087 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:01 PM PST 24 369192695 ps
T33 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.332811815 Feb 29 12:56:50 PM PST 24 Feb 29 12:56:55 PM PST 24 4821189977 ps
T30 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2450866647 Feb 29 12:56:57 PM PST 24 Feb 29 12:57:04 PM PST 24 544421317 ps
T34 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1446689755 Feb 29 12:56:57 PM PST 24 Feb 29 12:56:59 PM PST 24 512002701 ps
T88 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4197855105 Feb 29 12:56:49 PM PST 24 Feb 29 12:56:54 PM PST 24 858452874 ps
T791 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2028210651 Feb 29 12:56:58 PM PST 24 Feb 29 12:57:00 PM PST 24 374529887 ps
T99 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3030407506 Feb 29 12:56:58 PM PST 24 Feb 29 12:57:01 PM PST 24 449687327 ps
T100 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.943202844 Feb 29 12:56:42 PM PST 24 Feb 29 12:56:44 PM PST 24 499918747 ps
T58 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1479755274 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:01 PM PST 24 326983186 ps
T104 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1042951956 Feb 29 12:57:04 PM PST 24 Feb 29 12:57:06 PM PST 24 551263883 ps
T35 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.801725971 Feb 29 12:56:47 PM PST 24 Feb 29 12:56:49 PM PST 24 572083127 ps
T106 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4226182089 Feb 29 12:56:56 PM PST 24 Feb 29 12:57:05 PM PST 24 4189840487 ps
T792 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1402663689 Feb 29 12:57:16 PM PST 24 Feb 29 12:57:17 PM PST 24 455985337 ps
T31 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3993238250 Feb 29 12:56:50 PM PST 24 Feb 29 12:56:51 PM PST 24 360551392 ps
T107 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.599375362 Feb 29 12:56:45 PM PST 24 Feb 29 12:56:53 PM PST 24 9581464921 ps
T793 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2508018071 Feb 29 12:57:05 PM PST 24 Feb 29 12:57:06 PM PST 24 400700537 ps
T794 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1533398670 Feb 29 12:57:02 PM PST 24 Feb 29 12:57:04 PM PST 24 398314703 ps
T105 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2081886690 Feb 29 12:57:34 PM PST 24 Feb 29 12:57:36 PM PST 24 812401328 ps
T795 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3613882054 Feb 29 12:57:01 PM PST 24 Feb 29 12:57:03 PM PST 24 530271943 ps
T117 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3943575559 Feb 29 12:56:50 PM PST 24 Feb 29 12:57:11 PM PST 24 9040650400 ps
T116 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.840294457 Feb 29 12:56:47 PM PST 24 Feb 29 12:56:48 PM PST 24 557032248 ps
T111 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1452404143 Feb 29 12:56:46 PM PST 24 Feb 29 12:56:48 PM PST 24 704704364 ps
T796 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4229434263 Feb 29 12:57:06 PM PST 24 Feb 29 12:57:07 PM PST 24 452506175 ps
T28 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3399833639 Feb 29 12:56:49 PM PST 24 Feb 29 12:57:17 PM PST 24 29570829752 ps
T797 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.32836493 Feb 29 12:57:07 PM PST 24 Feb 29 12:57:09 PM PST 24 528833521 ps
T108 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2082173297 Feb 29 12:56:55 PM PST 24 Feb 29 12:56:58 PM PST 24 392808851 ps
T114 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.305608341 Feb 29 12:56:57 PM PST 24 Feb 29 12:56:59 PM PST 24 439957285 ps
T798 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4153782262 Feb 29 12:56:56 PM PST 24 Feb 29 12:56:58 PM PST 24 374375974 ps
T101 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1622104910 Feb 29 12:57:29 PM PST 24 Feb 29 12:57:30 PM PST 24 453114417 ps
T799 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1688699637 Feb 29 12:56:52 PM PST 24 Feb 29 12:56:54 PM PST 24 444190989 ps
T115 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2980097529 Feb 29 12:56:56 PM PST 24 Feb 29 12:56:58 PM PST 24 766079823 ps
T109 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4155802841 Feb 29 12:56:53 PM PST 24 Feb 29 12:56:55 PM PST 24 436428169 ps
T800 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3335247156 Feb 29 12:57:02 PM PST 24 Feb 29 12:57:04 PM PST 24 495276995 ps
T801 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4000382017 Feb 29 12:56:58 PM PST 24 Feb 29 12:56:59 PM PST 24 455415381 ps
T102 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3696508014 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:03 PM PST 24 522530939 ps
T29 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1578304905 Feb 29 12:57:15 PM PST 24 Feb 29 12:57:21 PM PST 24 2520931916 ps
T802 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3503557678 Feb 29 12:56:52 PM PST 24 Feb 29 12:56:53 PM PST 24 889825151 ps
T803 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2863940379 Feb 29 12:57:15 PM PST 24 Feb 29 12:57:27 PM PST 24 4344325809 ps
T110 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2114984941 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:03 PM PST 24 467616125 ps
T103 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1719615002 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:05 PM PST 24 4734989928 ps
T804 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3060239233 Feb 29 12:56:56 PM PST 24 Feb 29 12:56:58 PM PST 24 305901374 ps
T113 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3819054541 Feb 29 12:56:57 PM PST 24 Feb 29 12:57:00 PM PST 24 614226447 ps
T805 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1250784177 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:03 PM PST 24 458527108 ps
T806 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.664178290 Feb 29 12:57:05 PM PST 24 Feb 29 12:57:07 PM PST 24 472941695 ps
T89 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2106627991 Feb 29 12:57:10 PM PST 24 Feb 29 12:57:11 PM PST 24 551540791 ps
T807 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1108291261 Feb 29 12:56:37 PM PST 24 Feb 29 12:56:38 PM PST 24 575070349 ps
T90 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4241687982 Feb 29 12:56:52 PM PST 24 Feb 29 12:56:54 PM PST 24 327118488 ps
T808 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.491969335 Feb 29 12:56:50 PM PST 24 Feb 29 12:56:52 PM PST 24 428670045 ps
T91 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1020670792 Feb 29 12:56:49 PM PST 24 Feb 29 12:56:54 PM PST 24 1012330655 ps
T809 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1724512630 Feb 29 12:57:14 PM PST 24 Feb 29 12:57:15 PM PST 24 441115570 ps
T361 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3213728824 Feb 29 12:56:57 PM PST 24 Feb 29 12:57:01 PM PST 24 9054511038 ps
T810 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4112362359 Feb 29 12:56:53 PM PST 24 Feb 29 12:56:54 PM PST 24 482099183 ps
T811 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2734960419 Feb 29 12:56:37 PM PST 24 Feb 29 12:56:38 PM PST 24 487858025 ps
T92 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3123807262 Feb 29 12:56:56 PM PST 24 Feb 29 12:56:58 PM PST 24 527769504 ps
T812 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3271561999 Feb 29 12:56:45 PM PST 24 Feb 29 12:57:06 PM PST 24 8464455088 ps
T813 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.967777219 Feb 29 12:56:48 PM PST 24 Feb 29 12:56:50 PM PST 24 374791434 ps
T814 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2757417846 Feb 29 12:56:57 PM PST 24 Feb 29 12:56:59 PM PST 24 414983410 ps
T815 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2714824666 Feb 29 12:56:53 PM PST 24 Feb 29 12:56:55 PM PST 24 393582081 ps
T816 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3293278253 Feb 29 12:56:52 PM PST 24 Feb 29 12:56:53 PM PST 24 347185355 ps
T817 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3582720399 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:02 PM PST 24 505381614 ps
T818 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1234864836 Feb 29 12:56:39 PM PST 24 Feb 29 12:56:42 PM PST 24 4599311212 ps
T819 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1775519311 Feb 29 12:56:53 PM PST 24 Feb 29 12:57:00 PM PST 24 9275750774 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1964873272 Feb 29 12:57:21 PM PST 24 Feb 29 12:57:22 PM PST 24 661035033 ps
T821 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1499938776 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:01 PM PST 24 462468328 ps
T822 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2657675077 Feb 29 12:56:56 PM PST 24 Feb 29 12:57:03 PM PST 24 364133391 ps
T823 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.376392431 Feb 29 12:57:06 PM PST 24 Feb 29 12:57:09 PM PST 24 696812737 ps
T824 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1713301014 Feb 29 12:56:41 PM PST 24 Feb 29 12:56:59 PM PST 24 7308681228 ps
T93 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3532964112 Feb 29 12:56:57 PM PST 24 Feb 29 12:56:59 PM PST 24 575090267 ps
T94 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1045461392 Feb 29 12:56:52 PM PST 24 Feb 29 12:56:55 PM PST 24 838798155 ps
T95 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2263157282 Feb 29 12:56:38 PM PST 24 Feb 29 12:56:43 PM PST 24 845323217 ps
T825 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1319484763 Feb 29 12:57:01 PM PST 24 Feb 29 12:57:04 PM PST 24 506267336 ps
T826 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.364048615 Feb 29 12:56:50 PM PST 24 Feb 29 12:57:11 PM PST 24 8558625769 ps
T827 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2051148547 Feb 29 12:57:11 PM PST 24 Feb 29 12:57:13 PM PST 24 378482216 ps
T828 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.591652039 Feb 29 12:56:45 PM PST 24 Feb 29 12:56:48 PM PST 24 4333258424 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4023234634 Feb 29 12:57:03 PM PST 24 Feb 29 12:57:06 PM PST 24 1228699430 ps
T830 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.344179023 Feb 29 12:57:07 PM PST 24 Feb 29 12:57:09 PM PST 24 495369373 ps
T831 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3571531813 Feb 29 12:56:40 PM PST 24 Feb 29 12:56:52 PM PST 24 4892136624 ps
T832 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3534615234 Feb 29 12:56:50 PM PST 24 Feb 29 12:56:55 PM PST 24 9020061160 ps
T833 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.853676235 Feb 29 12:56:53 PM PST 24 Feb 29 12:56:57 PM PST 24 601524571 ps
T834 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2841090587 Feb 29 12:56:52 PM PST 24 Feb 29 12:56:54 PM PST 24 577802273 ps
T835 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2611919750 Feb 29 12:56:49 PM PST 24 Feb 29 12:57:12 PM PST 24 8522725705 ps
T836 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3827864568 Feb 29 12:56:47 PM PST 24 Feb 29 12:56:57 PM PST 24 4494855875 ps
T837 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2734061310 Feb 29 12:57:05 PM PST 24 Feb 29 12:57:07 PM PST 24 446937271 ps
T838 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.886078973 Feb 29 12:56:55 PM PST 24 Feb 29 12:56:57 PM PST 24 450216128 ps
T839 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3258995598 Feb 29 12:56:41 PM PST 24 Feb 29 12:58:14 PM PST 24 26431362169 ps
T840 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.531295978 Feb 29 12:57:02 PM PST 24 Feb 29 12:57:08 PM PST 24 2421136607 ps
T841 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3143034046 Feb 29 12:56:55 PM PST 24 Feb 29 12:56:58 PM PST 24 580939693 ps
T842 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2345664038 Feb 29 12:57:03 PM PST 24 Feb 29 12:57:04 PM PST 24 362562069 ps
T843 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3694214964 Feb 29 12:56:37 PM PST 24 Feb 29 12:56:38 PM PST 24 660195858 ps
T844 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2700229755 Feb 29 12:56:58 PM PST 24 Feb 29 12:56:59 PM PST 24 419185295 ps
T845 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2413056149 Feb 29 12:56:58 PM PST 24 Feb 29 12:57:02 PM PST 24 2462895210 ps
T846 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2776460888 Feb 29 12:56:56 PM PST 24 Feb 29 12:56:59 PM PST 24 523123503 ps
T847 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3782542498 Feb 29 12:56:55 PM PST 24 Feb 29 12:57:17 PM PST 24 9095818302 ps
T848 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.299124160 Feb 29 12:56:50 PM PST 24 Feb 29 12:56:51 PM PST 24 526470281 ps
T849 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2538346665 Feb 29 12:57:09 PM PST 24 Feb 29 12:57:13 PM PST 24 4519998166 ps
T850 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3443110570 Feb 29 12:57:02 PM PST 24 Feb 29 12:57:04 PM PST 24 491746028 ps
T851 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3212441723 Feb 29 12:57:01 PM PST 24 Feb 29 12:57:09 PM PST 24 518678985 ps
T852 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1069380552 Feb 29 12:56:55 PM PST 24 Feb 29 12:56:58 PM PST 24 519108182 ps
T853 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.80530438 Feb 29 12:56:55 PM PST 24 Feb 29 12:56:57 PM PST 24 704232325 ps
T854 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2187154348 Feb 29 12:56:57 PM PST 24 Feb 29 12:57:00 PM PST 24 2165131389 ps
T855 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.293072054 Feb 29 12:57:01 PM PST 24 Feb 29 12:57:02 PM PST 24 425984961 ps
T856 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3664811220 Feb 29 12:56:45 PM PST 24 Feb 29 12:56:48 PM PST 24 541552441 ps
T857 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.658743837 Feb 29 12:57:22 PM PST 24 Feb 29 12:57:26 PM PST 24 536824064 ps
T858 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2425204794 Feb 29 12:57:05 PM PST 24 Feb 29 12:57:07 PM PST 24 418662439 ps
T96 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4176484483 Feb 29 12:56:52 PM PST 24 Feb 29 12:56:54 PM PST 24 956864273 ps
T859 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2384322652 Feb 29 12:56:55 PM PST 24 Feb 29 12:56:57 PM PST 24 473359759 ps
T860 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1239416417 Feb 29 12:56:42 PM PST 24 Feb 29 12:56:43 PM PST 24 407742088 ps
T861 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2729729919 Feb 29 12:57:17 PM PST 24 Feb 29 12:57:18 PM PST 24 320427418 ps
T862 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3912613360 Feb 29 12:56:54 PM PST 24 Feb 29 12:56:57 PM PST 24 4735128814 ps
T863 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.590681857 Feb 29 12:56:53 PM PST 24 Feb 29 12:56:54 PM PST 24 364449919 ps
T864 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.643264633 Feb 29 12:56:59 PM PST 24 Feb 29 12:57:01 PM PST 24 285073261 ps
T865 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3176662468 Feb 29 12:56:50 PM PST 24 Feb 29 12:56:53 PM PST 24 899458276 ps
T866 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.946961039 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:03 PM PST 24 443405987 ps
T867 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.837929309 Feb 29 12:57:18 PM PST 24 Feb 29 12:57:31 PM PST 24 5450771653 ps
T868 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3986787807 Feb 29 12:56:56 PM PST 24 Feb 29 12:56:59 PM PST 24 358045447 ps
T869 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2483042293 Feb 29 12:57:09 PM PST 24 Feb 29 12:57:10 PM PST 24 534531807 ps
T870 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2719264801 Feb 29 12:57:39 PM PST 24 Feb 29 12:57:42 PM PST 24 440336937 ps
T871 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3395380382 Feb 29 12:56:50 PM PST 24 Feb 29 12:56:52 PM PST 24 459019717 ps
T872 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2394485257 Feb 29 12:56:56 PM PST 24 Feb 29 12:57:00 PM PST 24 489329020 ps
T873 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.576529888 Feb 29 12:57:03 PM PST 24 Feb 29 12:57:04 PM PST 24 554438529 ps
T874 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4017061203 Feb 29 12:56:48 PM PST 24 Feb 29 12:56:54 PM PST 24 309555581 ps
T875 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2717364471 Feb 29 12:56:54 PM PST 24 Feb 29 12:56:59 PM PST 24 6004538364 ps
T876 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2386069467 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:01 PM PST 24 527360531 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2666959720 Feb 29 12:56:40 PM PST 24 Feb 29 12:56:41 PM PST 24 475917040 ps
T878 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.309135049 Feb 29 12:57:01 PM PST 24 Feb 29 12:57:04 PM PST 24 570797757 ps
T879 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2011923304 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:03 PM PST 24 325411780 ps
T880 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2829548277 Feb 29 12:56:55 PM PST 24 Feb 29 12:56:59 PM PST 24 2443691738 ps
T881 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.653197933 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:06 PM PST 24 5110406854 ps
T882 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3425416568 Feb 29 12:57:04 PM PST 24 Feb 29 12:57:06 PM PST 24 557353176 ps
T883 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1246853313 Feb 29 12:56:56 PM PST 24 Feb 29 12:56:58 PM PST 24 459482340 ps
T884 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3829395281 Feb 29 12:56:36 PM PST 24 Feb 29 12:56:38 PM PST 24 442635450 ps
T885 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3879574175 Feb 29 12:57:01 PM PST 24 Feb 29 12:57:04 PM PST 24 567561278 ps
T886 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2619822155 Feb 29 12:57:07 PM PST 24 Feb 29 12:57:09 PM PST 24 2446575824 ps
T887 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1571151775 Feb 29 12:56:41 PM PST 24 Feb 29 12:56:42 PM PST 24 376684960 ps
T888 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3160371566 Feb 29 12:56:40 PM PST 24 Feb 29 12:56:41 PM PST 24 402126952 ps
T889 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.580997740 Feb 29 12:56:44 PM PST 24 Feb 29 12:56:46 PM PST 24 346862212 ps
T97 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2825278614 Feb 29 12:56:45 PM PST 24 Feb 29 12:56:48 PM PST 24 397116928 ps
T890 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1059485904 Feb 29 12:56:43 PM PST 24 Feb 29 12:56:44 PM PST 24 425361205 ps
T98 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1190034212 Feb 29 12:56:35 PM PST 24 Feb 29 12:56:40 PM PST 24 1224635017 ps
T891 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2647168884 Feb 29 12:57:02 PM PST 24 Feb 29 12:57:11 PM PST 24 4025939138 ps
T892 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1145258492 Feb 29 12:56:36 PM PST 24 Feb 29 12:56:50 PM PST 24 5565272050 ps
T893 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1795147313 Feb 29 12:56:57 PM PST 24 Feb 29 12:57:00 PM PST 24 2142289355 ps
T894 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.875218326 Feb 29 12:56:50 PM PST 24 Feb 29 12:56:54 PM PST 24 4324070290 ps
T895 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1327011210 Feb 29 12:56:55 PM PST 24 Feb 29 12:56:56 PM PST 24 423752546 ps
T896 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1602681326 Feb 29 12:57:00 PM PST 24 Feb 29 12:57:06 PM PST 24 4394003997 ps
T897 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2561541325 Feb 29 12:56:44 PM PST 24 Feb 29 12:56:46 PM PST 24 458054126 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3800084566 Feb 29 12:56:51 PM PST 24 Feb 29 12:58:33 PM PST 24 47236793425 ps
T899 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3563407921 Feb 29 12:57:01 PM PST 24 Feb 29 12:57:03 PM PST 24 484015112 ps
T900 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1361244651 Feb 29 12:56:53 PM PST 24 Feb 29 12:56:54 PM PST 24 545359975 ps
T901 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4031066989 Feb 29 12:56:54 PM PST 24 Feb 29 12:56:56 PM PST 24 637123717 ps
T902 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.460212706 Feb 29 12:56:56 PM PST 24 Feb 29 12:57:00 PM PST 24 553949300 ps
T903 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3974584077 Feb 29 12:56:38 PM PST 24 Feb 29 12:56:49 PM PST 24 3943670667 ps
T904 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3173944598 Feb 29 12:56:50 PM PST 24 Feb 29 12:57:02 PM PST 24 4801549086 ps
T905 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.646717325 Feb 29 12:56:45 PM PST 24 Feb 29 12:56:51 PM PST 24 4464609268 ps
T906 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2882425009 Feb 29 12:56:57 PM PST 24 Feb 29 12:57:00 PM PST 24 506459568 ps
T907 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1604381180 Feb 29 12:56:44 PM PST 24 Feb 29 12:56:47 PM PST 24 517886956 ps
T908 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4208498164 Feb 29 12:56:52 PM PST 24 Feb 29 12:56:53 PM PST 24 396977008 ps
T909 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2550568583 Feb 29 12:57:01 PM PST 24 Feb 29 12:57:11 PM PST 24 2265380974 ps
T910 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2408985593 Feb 29 12:56:35 PM PST 24 Feb 29 12:56:38 PM PST 24 2098251731 ps
T911 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.671732571 Feb 29 12:56:42 PM PST 24 Feb 29 12:56:47 PM PST 24 943973357 ps
T912 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2162596403 Feb 29 12:56:49 PM PST 24 Feb 29 12:56:51 PM PST 24 512390787 ps
T913 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2013995235 Feb 29 12:56:52 PM PST 24 Feb 29 12:57:00 PM PST 24 8408399145 ps
T914 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.789985548 Feb 29 12:56:57 PM PST 24 Feb 29 12:57:09 PM PST 24 5411557451 ps

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1587857864
Short name T7
Test name
Test status
Simulation time 502574754558 ps
CPU time 480.14 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:21:18 PM PST 24
Peak memory 201408 kb
Host smart-97c3ba43-8f71-495b-bf93-61e2ac531a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587857864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1587857864
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2811859699
Short name T18
Test name
Test status
Simulation time 74758399568 ps
CPU time 265.83 seconds
Started Feb 29 01:13:28 PM PST 24
Finished Feb 29 01:17:54 PM PST 24
Peak memory 210024 kb
Host smart-daefb2c6-3d3f-4f31-a8e7-950f85d67943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811859699 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2811859699
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2893551490
Short name T205
Test name
Test status
Simulation time 214939877078 ps
CPU time 397.21 seconds
Started Feb 29 01:14:03 PM PST 24
Finished Feb 29 01:20:40 PM PST 24
Peak memory 210104 kb
Host smart-71e1ecf7-48bd-4b63-8a12-4967aeec2bad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893551490 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2893551490
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3190328814
Short name T12
Test name
Test status
Simulation time 487991815067 ps
CPU time 221.6 seconds
Started Feb 29 01:13:05 PM PST 24
Finished Feb 29 01:16:47 PM PST 24
Peak memory 201400 kb
Host smart-ed2480a6-28ed-4e92-aea1-caf045db5e94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190328814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3190328814
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3226188318
Short name T24
Test name
Test status
Simulation time 401629035494 ps
CPU time 367.24 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:20:17 PM PST 24
Peak memory 201692 kb
Host smart-0edd9b38-bd98-4b8f-80b7-3bbd8891d474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226188318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3226188318
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3092530710
Short name T127
Test name
Test status
Simulation time 481855809900 ps
CPU time 843.06 seconds
Started Feb 29 01:13:16 PM PST 24
Finished Feb 29 01:27:19 PM PST 24
Peak memory 201356 kb
Host smart-3c1317b2-13f6-4934-be39-79c95a1fbb85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092530710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3092530710
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.1176353390
Short name T125
Test name
Test status
Simulation time 495253463170 ps
CPU time 1105.36 seconds
Started Feb 29 01:14:28 PM PST 24
Finished Feb 29 01:32:53 PM PST 24
Peak memory 201480 kb
Host smart-ff8a7f07-f889-4d72-8852-a9c9fc93ad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176353390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.1176353390
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.4277182057
Short name T126
Test name
Test status
Simulation time 481852763956 ps
CPU time 263.82 seconds
Started Feb 29 01:15:04 PM PST 24
Finished Feb 29 01:19:28 PM PST 24
Peak memory 201468 kb
Host smart-32353c88-9ec5-4275-b6bc-e564b9a0a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277182057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4277182057
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3941405987
Short name T79
Test name
Test status
Simulation time 515165273363 ps
CPU time 250.64 seconds
Started Feb 29 01:13:35 PM PST 24
Finished Feb 29 01:17:46 PM PST 24
Peak memory 201372 kb
Host smart-ac37a774-4f87-462e-905d-f92e7a93065d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941405987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3941405987
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1609368446
Short name T155
Test name
Test status
Simulation time 496048954278 ps
CPU time 487.8 seconds
Started Feb 29 01:17:04 PM PST 24
Finished Feb 29 01:25:12 PM PST 24
Peak memory 201376 kb
Host smart-e4e5e711-6ab5-475a-ae56-aa50933a01ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609368446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1609368446
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1446689755
Short name T34
Test name
Test status
Simulation time 512002701 ps
CPU time 1.42 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 201208 kb
Host smart-62f74c5e-29a8-41e1-9911-0bd8f658d868
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446689755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1446689755
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3781148788
Short name T151
Test name
Test status
Simulation time 507670690624 ps
CPU time 1214.17 seconds
Started Feb 29 01:16:15 PM PST 24
Finished Feb 29 01:36:31 PM PST 24
Peak memory 201412 kb
Host smart-d5366beb-560e-431f-8f41-ea65f1b5835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781148788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3781148788
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3003361045
Short name T276
Test name
Test status
Simulation time 496512747006 ps
CPU time 161.98 seconds
Started Feb 29 01:14:26 PM PST 24
Finished Feb 29 01:17:08 PM PST 24
Peak memory 201396 kb
Host smart-638add76-1274-4e41-a8e9-c51a02f3542b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003361045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3003361045
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1267006861
Short name T19
Test name
Test status
Simulation time 331777124517 ps
CPU time 339.63 seconds
Started Feb 29 01:16:34 PM PST 24
Finished Feb 29 01:22:14 PM PST 24
Peak memory 201460 kb
Host smart-39bfab71-640f-4746-be2d-9fcdecf3caac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267006861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1267006861
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.93302928
Short name T141
Test name
Test status
Simulation time 497300390820 ps
CPU time 439.89 seconds
Started Feb 29 01:13:00 PM PST 24
Finished Feb 29 01:20:20 PM PST 24
Peak memory 201448 kb
Host smart-d4a42ba5-de29-43c2-b4e2-c6bd49718fd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93302928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gating
.93302928
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.858675973
Short name T14
Test name
Test status
Simulation time 438788137 ps
CPU time 1.57 seconds
Started Feb 29 01:13:57 PM PST 24
Finished Feb 29 01:13:59 PM PST 24
Peak memory 200996 kb
Host smart-f41599e3-56f6-45c8-84b1-47124f2a9a81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858675973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.858675973
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3399833639
Short name T28
Test name
Test status
Simulation time 29570829752 ps
CPU time 26.92 seconds
Started Feb 29 12:56:49 PM PST 24
Finished Feb 29 12:57:17 PM PST 24
Peak memory 201244 kb
Host smart-cd1c2a47-5283-4f4b-a105-501231463e79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399833639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3399833639
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1568043266
Short name T32
Test name
Test status
Simulation time 489975436339 ps
CPU time 178.39 seconds
Started Feb 29 01:14:13 PM PST 24
Finished Feb 29 01:17:11 PM PST 24
Peak memory 201368 kb
Host smart-2b0ff7c9-6b8f-44f4-a595-9b268f559acc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568043266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1568043266
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2819497717
Short name T1
Test name
Test status
Simulation time 325825505693 ps
CPU time 320.33 seconds
Started Feb 29 01:16:19 PM PST 24
Finished Feb 29 01:21:39 PM PST 24
Peak memory 201472 kb
Host smart-affaeeac-75b6-458d-9985-a61c3d53b033
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819497717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2819497717
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1462137095
Short name T40
Test name
Test status
Simulation time 8119033063 ps
CPU time 3.65 seconds
Started Feb 29 01:12:23 PM PST 24
Finished Feb 29 01:12:27 PM PST 24
Peak memory 217368 kb
Host smart-5fa72240-7422-4376-9bc3-e35c98179819
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462137095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1462137095
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1981628728
Short name T4
Test name
Test status
Simulation time 510601203668 ps
CPU time 1121.79 seconds
Started Feb 29 01:13:29 PM PST 24
Finished Feb 29 01:32:11 PM PST 24
Peak memory 201440 kb
Host smart-b080f251-65d9-4580-a38d-36ef9e190b0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981628728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1981628728
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.294617263
Short name T13
Test name
Test status
Simulation time 325776779336 ps
CPU time 786.25 seconds
Started Feb 29 01:13:27 PM PST 24
Finished Feb 29 01:26:33 PM PST 24
Peak memory 201504 kb
Host smart-152d987a-463b-4202-9d68-5c3716d3a5a2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294617263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.294617263
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.231122521
Short name T238
Test name
Test status
Simulation time 500645906876 ps
CPU time 560.42 seconds
Started Feb 29 01:13:49 PM PST 24
Finished Feb 29 01:23:10 PM PST 24
Peak memory 201472 kb
Host smart-744601a9-0b66-4881-89ec-98d54a81f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231122521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.231122521
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2878922024
Short name T136
Test name
Test status
Simulation time 164797878450 ps
CPU time 51.9 seconds
Started Feb 29 01:13:20 PM PST 24
Finished Feb 29 01:14:13 PM PST 24
Peak memory 201356 kb
Host smart-81feb0fb-ef77-414a-99e0-785543dafa66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878922024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2878922024
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1246351171
Short name T161
Test name
Test status
Simulation time 661809052025 ps
CPU time 332.81 seconds
Started Feb 29 01:12:45 PM PST 24
Finished Feb 29 01:18:18 PM PST 24
Peak memory 201440 kb
Host smart-5760dc82-085d-4dc6-aadf-9d8f25d7d024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246351171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1246351171
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2121925805
Short name T15
Test name
Test status
Simulation time 242817950590 ps
CPU time 169.33 seconds
Started Feb 29 01:15:05 PM PST 24
Finished Feb 29 01:17:55 PM PST 24
Peak memory 209624 kb
Host smart-630dd74c-f27b-438a-8de8-855d89dc99bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121925805 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2121925805
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2081886690
Short name T105
Test name
Test status
Simulation time 812401328 ps
CPU time 2.33 seconds
Started Feb 29 12:57:34 PM PST 24
Finished Feb 29 12:57:36 PM PST 24
Peak memory 201248 kb
Host smart-82ba5bdb-e1e1-4fcc-9483-8b8e148cb00c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081886690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2081886690
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.591673786
Short name T265
Test name
Test status
Simulation time 497506572148 ps
CPU time 1063.66 seconds
Started Feb 29 01:13:16 PM PST 24
Finished Feb 29 01:31:01 PM PST 24
Peak memory 201668 kb
Host smart-5daefa21-951c-442d-b626-3f1d430d5caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591673786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.591673786
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3394818416
Short name T16
Test name
Test status
Simulation time 167003460544 ps
CPU time 163.68 seconds
Started Feb 29 01:14:35 PM PST 24
Finished Feb 29 01:17:18 PM PST 24
Peak memory 210304 kb
Host smart-d7d5d690-8942-4a2a-9090-d9935f3d3258
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394818416 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3394818416
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.970099654
Short name T56
Test name
Test status
Simulation time 126236409318 ps
CPU time 322.82 seconds
Started Feb 29 01:16:01 PM PST 24
Finished Feb 29 01:21:24 PM PST 24
Peak memory 210048 kb
Host smart-7bec17f9-5ada-45d7-8045-3522f6347da0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970099654 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.970099654
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.1169824085
Short name T277
Test name
Test status
Simulation time 491644276326 ps
CPU time 557.35 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:22:04 PM PST 24
Peak memory 201432 kb
Host smart-aa96f9ba-b525-4d20-80ac-632e4558363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169824085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.1169824085
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3023731249
Short name T262
Test name
Test status
Simulation time 329787893595 ps
CPU time 170.67 seconds
Started Feb 29 01:14:03 PM PST 24
Finished Feb 29 01:16:54 PM PST 24
Peak memory 201376 kb
Host smart-a5fe2115-b340-4f30-8388-509b13d30e7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023731249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3023731249
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3213728824
Short name T361
Test name
Test status
Simulation time 9054511038 ps
CPU time 3.5 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:57:01 PM PST 24
Peak memory 201224 kb
Host smart-010904a8-69db-40f0-9ba3-c18ddcf26490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213728824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3213728824
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.935967412
Short name T82
Test name
Test status
Simulation time 327662025356 ps
CPU time 80.26 seconds
Started Feb 29 01:14:22 PM PST 24
Finished Feb 29 01:15:42 PM PST 24
Peak memory 201368 kb
Host smart-21fbe70a-2a0e-4f75-894b-b63ec8db852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935967412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.935967412
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1033724965
Short name T256
Test name
Test status
Simulation time 325539968111 ps
CPU time 713.24 seconds
Started Feb 29 01:14:08 PM PST 24
Finished Feb 29 01:26:01 PM PST 24
Peak memory 201480 kb
Host smart-f210d20c-c6a2-4e8d-b268-8e9960d72031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033724965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1033724965
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.173847503
Short name T10
Test name
Test status
Simulation time 330380693501 ps
CPU time 459.05 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:20:43 PM PST 24
Peak memory 201384 kb
Host smart-e33ca27b-b69f-4a43-b305-4209ac5af7ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173847503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.173847503
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1410806090
Short name T191
Test name
Test status
Simulation time 499002712542 ps
CPU time 319.58 seconds
Started Feb 29 01:12:27 PM PST 24
Finished Feb 29 01:17:47 PM PST 24
Peak memory 201364 kb
Host smart-289d596f-c29d-4312-836b-2122245bff99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410806090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1410806090
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3922910796
Short name T250
Test name
Test status
Simulation time 491790614027 ps
CPU time 1076.42 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:30:25 PM PST 24
Peak memory 201392 kb
Host smart-5a5a4a21-c2b7-4fb2-b873-2f447efc5446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922910796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3922910796
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2604603838
Short name T360
Test name
Test status
Simulation time 495219210371 ps
CPU time 705.34 seconds
Started Feb 29 01:13:58 PM PST 24
Finished Feb 29 01:25:44 PM PST 24
Peak memory 201468 kb
Host smart-9e0471f9-097a-4c88-941a-1e227320d083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604603838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2604603838
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2856550952
Short name T311
Test name
Test status
Simulation time 330501232706 ps
CPU time 259.67 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:17:27 PM PST 24
Peak memory 201508 kb
Host smart-ff84ef9a-b3ed-48c8-8229-cd3af9adbb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856550952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2856550952
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.136178699
Short name T778
Test name
Test status
Simulation time 1440407248974 ps
CPU time 435.63 seconds
Started Feb 29 01:13:11 PM PST 24
Finished Feb 29 01:20:26 PM PST 24
Peak memory 210052 kb
Host smart-146b5ddc-4c67-4308-a916-8b03190b83bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136178699 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.136178699
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3230558334
Short name T139
Test name
Test status
Simulation time 332582712641 ps
CPU time 845.16 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:26:52 PM PST 24
Peak memory 201464 kb
Host smart-0d7a81ee-3711-4fcd-a911-b9345e947c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230558334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3230558334
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1094469137
Short name T167
Test name
Test status
Simulation time 494513919070 ps
CPU time 223.91 seconds
Started Feb 29 01:13:00 PM PST 24
Finished Feb 29 01:16:45 PM PST 24
Peak memory 201348 kb
Host smart-5877e142-8af5-4c2f-9356-f2423784a5c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094469137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1094469137
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.781686256
Short name T295
Test name
Test status
Simulation time 167997027211 ps
CPU time 371.85 seconds
Started Feb 29 01:13:36 PM PST 24
Finished Feb 29 01:19:48 PM PST 24
Peak memory 201284 kb
Host smart-3e8e2b13-c0e6-44d9-b4af-8ccd33be3e7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781686256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.781686256
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.4204563058
Short name T172
Test name
Test status
Simulation time 333109937820 ps
CPU time 114.52 seconds
Started Feb 29 01:15:59 PM PST 24
Finished Feb 29 01:17:53 PM PST 24
Peak memory 201396 kb
Host smart-4f5a0068-05b6-4e90-8511-26e371f7dd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204563058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.4204563058
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3993238250
Short name T31
Test name
Test status
Simulation time 360551392 ps
CPU time 1.2 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:56:51 PM PST 24
Peak memory 200800 kb
Host smart-370959b5-0cb1-4d6b-9e26-df9da19a005a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993238250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3993238250
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.766484593
Short name T73
Test name
Test status
Simulation time 163090563544 ps
CPU time 377.83 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:19:25 PM PST 24
Peak memory 209716 kb
Host smart-f1f1bc61-14e2-4cf7-bd5b-7aa86e4d47a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766484593 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.766484593
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.963752679
Short name T347
Test name
Test status
Simulation time 488227897497 ps
CPU time 1128.51 seconds
Started Feb 29 01:13:20 PM PST 24
Finished Feb 29 01:32:09 PM PST 24
Peak memory 201456 kb
Host smart-af14bb59-72a6-43a9-9383-963f0185379d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963752679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.963752679
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3746457252
Short name T225
Test name
Test status
Simulation time 508223283030 ps
CPU time 1069.17 seconds
Started Feb 29 01:13:30 PM PST 24
Finished Feb 29 01:31:20 PM PST 24
Peak memory 209808 kb
Host smart-60ed33f3-ddc9-4e8d-87cf-b611453a9b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746457252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3746457252
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3520971560
Short name T340
Test name
Test status
Simulation time 326180337382 ps
CPU time 85.16 seconds
Started Feb 29 01:13:56 PM PST 24
Finished Feb 29 01:15:22 PM PST 24
Peak memory 201452 kb
Host smart-49cbcc26-fd2f-403e-9ad4-3cd72e191a0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520971560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3520971560
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.443831395
Short name T121
Test name
Test status
Simulation time 331272282512 ps
CPU time 762.25 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:25:11 PM PST 24
Peak memory 201384 kb
Host smart-eaa84c89-262b-40bd-a24d-a16019412812
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443831395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.443831395
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3441259696
Short name T228
Test name
Test status
Simulation time 160058475891 ps
CPU time 101.23 seconds
Started Feb 29 01:15:16 PM PST 24
Finished Feb 29 01:16:57 PM PST 24
Peak memory 201544 kb
Host smart-6f141529-7fa0-41d0-807f-996a3a9585f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441259696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3441259696
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4155802841
Short name T109
Test name
Test status
Simulation time 436428169 ps
CPU time 1.99 seconds
Started Feb 29 12:56:53 PM PST 24
Finished Feb 29 12:56:55 PM PST 24
Peak memory 201192 kb
Host smart-0fe683b3-f43f-4435-95c4-3e2c774a9721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155802841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4155802841
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.70041751
Short name T223
Test name
Test status
Simulation time 76861429494 ps
CPU time 237.5 seconds
Started Feb 29 01:13:18 PM PST 24
Finished Feb 29 01:17:17 PM PST 24
Peak memory 201756 kb
Host smart-7701e723-2909-45a8-b815-91eb61fe0be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70041751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.70041751
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.157670826
Short name T290
Test name
Test status
Simulation time 326229280815 ps
CPU time 767.72 seconds
Started Feb 29 01:13:25 PM PST 24
Finished Feb 29 01:26:13 PM PST 24
Peak memory 201396 kb
Host smart-34aab209-87a4-4c89-b95e-13626a7526a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157670826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.157670826
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3586984456
Short name T338
Test name
Test status
Simulation time 138314218879 ps
CPU time 193.94 seconds
Started Feb 29 01:15:14 PM PST 24
Finished Feb 29 01:18:28 PM PST 24
Peak memory 209768 kb
Host smart-de053645-e963-496e-b49f-c04c30fe47af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586984456 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3586984456
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2563547326
Short name T327
Test name
Test status
Simulation time 494961192129 ps
CPU time 617.54 seconds
Started Feb 29 01:15:44 PM PST 24
Finished Feb 29 01:26:01 PM PST 24
Peak memory 201440 kb
Host smart-2251adf0-693b-45c4-a040-2bf8aad56c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563547326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2563547326
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3975270362
Short name T240
Test name
Test status
Simulation time 505726871309 ps
CPU time 309.98 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:17:39 PM PST 24
Peak memory 201396 kb
Host smart-0236eb04-78ec-4d28-b756-3e83039d74ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975270362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3975270362
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3624952906
Short name T315
Test name
Test status
Simulation time 336162911508 ps
CPU time 571.12 seconds
Started Feb 29 01:14:09 PM PST 24
Finished Feb 29 01:23:41 PM PST 24
Peak memory 201340 kb
Host smart-a8584492-c469-41b4-bf8e-3eeb4ee7fc89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624952906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3624952906
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2572338001
Short name T341
Test name
Test status
Simulation time 340149711435 ps
CPU time 654.36 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:23:23 PM PST 24
Peak memory 201664 kb
Host smart-2f087613-eb45-4ebd-9add-9ad4bff10f53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572338001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2572338001
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1230505379
Short name T261
Test name
Test status
Simulation time 167211628553 ps
CPU time 412.36 seconds
Started Feb 29 01:13:05 PM PST 24
Finished Feb 29 01:19:58 PM PST 24
Peak memory 201308 kb
Host smart-4a3192de-5efb-4d2d-83d2-eaffe29a62e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230505379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1230505379
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2815537686
Short name T286
Test name
Test status
Simulation time 521052083814 ps
CPU time 356.7 seconds
Started Feb 29 01:12:33 PM PST 24
Finished Feb 29 01:18:29 PM PST 24
Peak memory 201364 kb
Host smart-49b1a5f1-02b5-4ad2-a504-dff2f734b5b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815537686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2815537686
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1977625478
Short name T249
Test name
Test status
Simulation time 486530806160 ps
CPU time 604.72 seconds
Started Feb 29 01:13:26 PM PST 24
Finished Feb 29 01:23:31 PM PST 24
Peak memory 201464 kb
Host smart-a102217b-a081-4685-af7b-352f1c1e275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977625478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1977625478
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1447122183
Short name T138
Test name
Test status
Simulation time 325650386239 ps
CPU time 753.07 seconds
Started Feb 29 01:13:57 PM PST 24
Finished Feb 29 01:26:31 PM PST 24
Peak memory 201384 kb
Host smart-32f82490-fc01-47ad-bb9e-d8c259eddaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447122183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1447122183
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2944179923
Short name T317
Test name
Test status
Simulation time 165437693079 ps
CPU time 362.76 seconds
Started Feb 29 01:14:28 PM PST 24
Finished Feb 29 01:20:31 PM PST 24
Peak memory 201404 kb
Host smart-63264cbf-8f21-4190-987a-3d41bd359f14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944179923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2944179923
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1356761572
Short name T140
Test name
Test status
Simulation time 336751211782 ps
CPU time 200.31 seconds
Started Feb 29 01:15:05 PM PST 24
Finished Feb 29 01:18:25 PM PST 24
Peak memory 201416 kb
Host smart-f66731b0-051e-4f78-8870-2eb75f65178a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356761572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1356761572
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.995911219
Short name T281
Test name
Test status
Simulation time 332197760612 ps
CPU time 419.92 seconds
Started Feb 29 01:15:25 PM PST 24
Finished Feb 29 01:22:25 PM PST 24
Peak memory 201576 kb
Host smart-1d9fde38-ab14-4a00-a10a-b1370b814033
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995911219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.995911219
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.216146697
Short name T72
Test name
Test status
Simulation time 75294461343 ps
CPU time 372.46 seconds
Started Feb 29 01:16:01 PM PST 24
Finished Feb 29 01:22:14 PM PST 24
Peak memory 201724 kb
Host smart-fbe9a766-fcc6-47c8-97f0-89fb0d6407f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216146697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.216146697
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2872955521
Short name T239
Test name
Test status
Simulation time 323078067426 ps
CPU time 701.76 seconds
Started Feb 29 01:16:15 PM PST 24
Finished Feb 29 01:27:57 PM PST 24
Peak memory 201468 kb
Host smart-09e8cd1b-fd86-49e4-88b5-0e99c1edcb8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872955521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2872955521
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3399401217
Short name T45
Test name
Test status
Simulation time 491871721890 ps
CPU time 1187.04 seconds
Started Feb 29 01:13:12 PM PST 24
Finished Feb 29 01:32:59 PM PST 24
Peak memory 201416 kb
Host smart-3208f6e4-59f4-433b-a81c-b2f400e24bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399401217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3399401217
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.81083294
Short name T324
Test name
Test status
Simulation time 326473218822 ps
CPU time 346.35 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:18:49 PM PST 24
Peak memory 201408 kb
Host smart-851ca7d8-72fe-440a-9bb9-4d5c7d567597
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81083294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gatin
g.81083294
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.579725143
Short name T280
Test name
Test status
Simulation time 328227385127 ps
CPU time 405.89 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:19:49 PM PST 24
Peak memory 201340 kb
Host smart-7597120e-736e-4f09-9a0b-2d2698be1bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579725143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.579725143
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1753506538
Short name T294
Test name
Test status
Simulation time 497088708528 ps
CPU time 1077.71 seconds
Started Feb 29 01:13:02 PM PST 24
Finished Feb 29 01:31:00 PM PST 24
Peak memory 201388 kb
Host smart-f3562a0e-2b01-498a-81ff-6429a5046ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753506538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1753506538
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2173564803
Short name T322
Test name
Test status
Simulation time 362997804116 ps
CPU time 434.52 seconds
Started Feb 29 01:13:26 PM PST 24
Finished Feb 29 01:20:41 PM PST 24
Peak memory 201256 kb
Host smart-3c5de5c5-eee6-445c-9d44-6d62b684984a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173564803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2173564803
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.143895711
Short name T336
Test name
Test status
Simulation time 487692274254 ps
CPU time 1146.24 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:32:52 PM PST 24
Peak memory 201484 kb
Host smart-02af3698-eac0-441f-9080-30f4300c2309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143895711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.143895711
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1014389284
Short name T272
Test name
Test status
Simulation time 495455914952 ps
CPU time 1182.91 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:32:11 PM PST 24
Peak memory 201444 kb
Host smart-2ae3a84b-1962-4b86-8e45-ee5188a5ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014389284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1014389284
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1030673568
Short name T309
Test name
Test status
Simulation time 323154209712 ps
CPU time 90.59 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:16:32 PM PST 24
Peak memory 201444 kb
Host smart-675d39de-ab25-4c71-94b4-6370b1eef934
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030673568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1030673568
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2611919750
Short name T835
Test name
Test status
Simulation time 8522725705 ps
CPU time 22.13 seconds
Started Feb 29 12:56:49 PM PST 24
Finished Feb 29 12:57:12 PM PST 24
Peak memory 201180 kb
Host smart-1734d4bc-ec75-493c-b616-8559455ad7ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611919750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2611919750
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2284705293
Short name T215
Test name
Test status
Simulation time 94631089389 ps
CPU time 68.98 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:14:16 PM PST 24
Peak memory 209700 kb
Host smart-85cef40a-1efc-4292-8543-b2150740db28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284705293 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2284705293
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.891778512
Short name T325
Test name
Test status
Simulation time 166707881244 ps
CPU time 91.89 seconds
Started Feb 29 01:13:05 PM PST 24
Finished Feb 29 01:14:37 PM PST 24
Peak memory 201392 kb
Host smart-f2d1cc83-7bc1-4573-afcf-08a5fb7f19ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891778512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.891778512
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3337326370
Short name T298
Test name
Test status
Simulation time 328107988586 ps
CPU time 80.68 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:14:25 PM PST 24
Peak memory 201392 kb
Host smart-35f32d64-3bb5-4878-8157-1fe6797dd3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337326370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3337326370
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2837692399
Short name T70
Test name
Test status
Simulation time 91494731373 ps
CPU time 337.89 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:18:41 PM PST 24
Peak memory 201724 kb
Host smart-ca09df0e-82a1-4e47-9b94-a0d9cffc319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837692399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2837692399
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2524786821
Short name T364
Test name
Test status
Simulation time 120170788307 ps
CPU time 655.78 seconds
Started Feb 29 01:13:08 PM PST 24
Finished Feb 29 01:24:04 PM PST 24
Peak memory 201768 kb
Host smart-9481a7c8-e7e1-43b6-8487-830832cef410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524786821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2524786821
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.688814527
Short name T304
Test name
Test status
Simulation time 331325403920 ps
CPU time 213.6 seconds
Started Feb 29 01:13:14 PM PST 24
Finished Feb 29 01:16:48 PM PST 24
Peak memory 201448 kb
Host smart-bbf57fc6-4b12-4de0-8afc-7f8b3b49dbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688814527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.688814527
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3545698033
Short name T369
Test name
Test status
Simulation time 71851911777 ps
CPU time 256.17 seconds
Started Feb 29 01:13:30 PM PST 24
Finished Feb 29 01:17:47 PM PST 24
Peak memory 201776 kb
Host smart-864f778f-4328-4248-af27-50d19ab898da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545698033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3545698033
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3613782461
Short name T174
Test name
Test status
Simulation time 500060426544 ps
CPU time 197.14 seconds
Started Feb 29 01:13:56 PM PST 24
Finished Feb 29 01:17:14 PM PST 24
Peak memory 201488 kb
Host smart-42d636fb-cd05-4e95-9930-c61ad5f0596c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613782461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3613782461
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3993040418
Short name T158
Test name
Test status
Simulation time 330622675723 ps
CPU time 80.42 seconds
Started Feb 29 01:14:13 PM PST 24
Finished Feb 29 01:15:34 PM PST 24
Peak memory 201352 kb
Host smart-bc3865cb-259f-4ab2-a886-19357b56884a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993040418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3993040418
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2333824448
Short name T370
Test name
Test status
Simulation time 138480284086 ps
CPU time 715.76 seconds
Started Feb 29 01:15:03 PM PST 24
Finished Feb 29 01:26:59 PM PST 24
Peak memory 201964 kb
Host smart-c8f29b46-6d92-4107-8e91-cb237f740c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333824448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2333824448
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1407093075
Short name T216
Test name
Test status
Simulation time 95928228157 ps
CPU time 201.43 seconds
Started Feb 29 01:16:56 PM PST 24
Finished Feb 29 01:20:18 PM PST 24
Peak memory 218108 kb
Host smart-2339dc1d-4abb-440b-a801-a6c3266a9d55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407093075 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1407093075
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3728764504
Short name T60
Test name
Test status
Simulation time 107824974833 ps
CPU time 550.69 seconds
Started Feb 29 01:17:05 PM PST 24
Finished Feb 29 01:26:15 PM PST 24
Peak memory 201692 kb
Host smart-f16cc268-b886-493d-a0a7-96006db102fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728764504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3728764504
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.2263157282
Short name T95
Test name
Test status
Simulation time 845323217 ps
CPU time 4.4 seconds
Started Feb 29 12:56:38 PM PST 24
Finished Feb 29 12:56:43 PM PST 24
Peak memory 201052 kb
Host smart-1b862bb3-9c2f-4adb-995d-ee3998df4177
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263157282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.2263157282
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.3800084566
Short name T898
Test name
Test status
Simulation time 47236793425 ps
CPU time 101.59 seconds
Started Feb 29 12:56:51 PM PST 24
Finished Feb 29 12:58:33 PM PST 24
Peak memory 201204 kb
Host smart-460ef2e0-b4a0-4f1c-9f67-3145558ef679
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800084566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.3800084566
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4176484483
Short name T96
Test name
Test status
Simulation time 956864273 ps
CPU time 1.22 seconds
Started Feb 29 12:56:52 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 200600 kb
Host smart-25cb84b3-ac9e-4ff8-8200-b93d10986381
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176484483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.4176484483
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2734960419
Short name T811
Test name
Test status
Simulation time 487858025 ps
CPU time 1.21 seconds
Started Feb 29 12:56:37 PM PST 24
Finished Feb 29 12:56:38 PM PST 24
Peak memory 201012 kb
Host smart-f05abcaf-5286-47a5-a236-d0496fc2eae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734960419 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2734960419
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1571151775
Short name T887
Test name
Test status
Simulation time 376684960 ps
CPU time 0.78 seconds
Started Feb 29 12:56:41 PM PST 24
Finished Feb 29 12:56:42 PM PST 24
Peak memory 200616 kb
Host smart-6962480b-2a14-4110-9870-577ba9ab2196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571151775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1571151775
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2408985593
Short name T910
Test name
Test status
Simulation time 2098251731 ps
CPU time 1.68 seconds
Started Feb 29 12:56:35 PM PST 24
Finished Feb 29 12:56:38 PM PST 24
Peak memory 200952 kb
Host smart-ae36277b-2a18-4abf-afe3-87207a008451
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408985593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2408985593
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2394485257
Short name T872
Test name
Test status
Simulation time 489329020 ps
CPU time 2.98 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:57:00 PM PST 24
Peak memory 217380 kb
Host smart-31a5d7a6-ea76-48fc-8e6f-837af545e348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394485257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2394485257
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.364048615
Short name T826
Test name
Test status
Simulation time 8558625769 ps
CPU time 20.63 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:57:11 PM PST 24
Peak memory 201056 kb
Host smart-87fd89e3-cb79-483c-b0b8-8ee02d0f9a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364048615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.364048615
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.671732571
Short name T911
Test name
Test status
Simulation time 943973357 ps
CPU time 4.2 seconds
Started Feb 29 12:56:42 PM PST 24
Finished Feb 29 12:56:47 PM PST 24
Peak memory 201080 kb
Host smart-28ecba5c-7383-4a10-b1d4-b02b5e49dec6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671732571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.671732571
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3258995598
Short name T839
Test name
Test status
Simulation time 26431362169 ps
CPU time 92.89 seconds
Started Feb 29 12:56:41 PM PST 24
Finished Feb 29 12:58:14 PM PST 24
Peak memory 201204 kb
Host smart-b426c9b1-19a6-465c-a7b1-0db5b97dffb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258995598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3258995598
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3694214964
Short name T843
Test name
Test status
Simulation time 660195858 ps
CPU time 1.43 seconds
Started Feb 29 12:56:37 PM PST 24
Finished Feb 29 12:56:38 PM PST 24
Peak memory 200948 kb
Host smart-caa7ab6d-98ab-4439-a429-b211ed8fdffb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694214964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3694214964
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1108291261
Short name T807
Test name
Test status
Simulation time 575070349 ps
CPU time 1.7 seconds
Started Feb 29 12:56:37 PM PST 24
Finished Feb 29 12:56:38 PM PST 24
Peak memory 200992 kb
Host smart-43162267-07ff-4944-92a3-9a92524f8d20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108291261 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1108291261
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.943202844
Short name T100
Test name
Test status
Simulation time 499918747 ps
CPU time 1.91 seconds
Started Feb 29 12:56:42 PM PST 24
Finished Feb 29 12:56:44 PM PST 24
Peak memory 200912 kb
Host smart-4fb338f0-5bcb-4b37-a30d-78df22e09088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943202844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.943202844
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3829395281
Short name T884
Test name
Test status
Simulation time 442635450 ps
CPU time 1.57 seconds
Started Feb 29 12:56:36 PM PST 24
Finished Feb 29 12:56:38 PM PST 24
Peak memory 200872 kb
Host smart-6f6b2dbb-2dec-4087-b201-7b51dea75e43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829395281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3829395281
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1234864836
Short name T818
Test name
Test status
Simulation time 4599311212 ps
CPU time 3.28 seconds
Started Feb 29 12:56:39 PM PST 24
Finished Feb 29 12:56:42 PM PST 24
Peak memory 201240 kb
Host smart-7004dc0f-207d-414f-b42f-56e786b291f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234864836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1234864836
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3160371566
Short name T888
Test name
Test status
Simulation time 402126952 ps
CPU time 1.69 seconds
Started Feb 29 12:56:40 PM PST 24
Finished Feb 29 12:56:41 PM PST 24
Peak memory 201120 kb
Host smart-f8bd2dfe-19cf-4731-866a-0fb4026739fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160371566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3160371566
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.646717325
Short name T905
Test name
Test status
Simulation time 4464609268 ps
CPU time 5.13 seconds
Started Feb 29 12:56:45 PM PST 24
Finished Feb 29 12:56:51 PM PST 24
Peak memory 201176 kb
Host smart-dcab51f6-b6ba-4469-9d82-9e1fe9786bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646717325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.646717325
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2384322652
Short name T859
Test name
Test status
Simulation time 473359759 ps
CPU time 1.83 seconds
Started Feb 29 12:56:55 PM PST 24
Finished Feb 29 12:56:57 PM PST 24
Peak memory 200976 kb
Host smart-daf7ae84-0034-4068-806d-4ca2baa271ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384322652 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2384322652
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2450866647
Short name T30
Test name
Test status
Simulation time 544421317 ps
CPU time 1.43 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 200928 kb
Host smart-1abd1b58-7ba0-4a91-8dd3-0278bb0bd426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450866647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2450866647
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.293072054
Short name T855
Test name
Test status
Simulation time 425984961 ps
CPU time 0.7 seconds
Started Feb 29 12:57:01 PM PST 24
Finished Feb 29 12:57:02 PM PST 24
Peak memory 200632 kb
Host smart-2780e532-513d-4b56-b787-a04c22d45706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293072054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.293072054
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3827864568
Short name T836
Test name
Test status
Simulation time 4494855875 ps
CPU time 10.44 seconds
Started Feb 29 12:56:47 PM PST 24
Finished Feb 29 12:56:57 PM PST 24
Peak memory 201208 kb
Host smart-6839a45a-b365-411a-8a3d-8d5b711a5b1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827864568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3827864568
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2719264801
Short name T870
Test name
Test status
Simulation time 440336937 ps
CPU time 2.57 seconds
Started Feb 29 12:57:39 PM PST 24
Finished Feb 29 12:57:42 PM PST 24
Peak memory 201260 kb
Host smart-ec958cc2-14e7-4a0d-b02e-098bb8098955
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719264801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2719264801
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1479755274
Short name T58
Test name
Test status
Simulation time 326983186 ps
CPU time 1.15 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:01 PM PST 24
Peak memory 201016 kb
Host smart-983d29ac-628e-4ecb-90ac-7566c9b3f48c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479755274 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1479755274
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3123807262
Short name T92
Test name
Test status
Simulation time 527769504 ps
CPU time 0.84 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:56:58 PM PST 24
Peak memory 200940 kb
Host smart-953ba0a7-88db-4946-b107-f243dc206a9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123807262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3123807262
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2776460888
Short name T846
Test name
Test status
Simulation time 523123503 ps
CPU time 1.76 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 200700 kb
Host smart-5c6ea0c9-982a-40aa-ac26-950a177c1021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776460888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2776460888
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2550568583
Short name T909
Test name
Test status
Simulation time 2265380974 ps
CPU time 9.33 seconds
Started Feb 29 12:57:01 PM PST 24
Finished Feb 29 12:57:11 PM PST 24
Peak memory 200916 kb
Host smart-7d090e55-8c52-4ab8-889d-055564471d05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550568583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2550568583
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.801725971
Short name T35
Test name
Test status
Simulation time 572083127 ps
CPU time 1.67 seconds
Started Feb 29 12:56:47 PM PST 24
Finished Feb 29 12:56:49 PM PST 24
Peak memory 201312 kb
Host smart-38a982a7-7ffe-475c-a06f-f4da388c69a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801725971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.801725971
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1964873272
Short name T820
Test name
Test status
Simulation time 661035033 ps
CPU time 1.52 seconds
Started Feb 29 12:57:21 PM PST 24
Finished Feb 29 12:57:22 PM PST 24
Peak memory 209452 kb
Host smart-763dc515-6622-4b31-ad82-1d95fcfa6736
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964873272 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1964873272
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3696508014
Short name T102
Test name
Test status
Simulation time 522530939 ps
CPU time 1.66 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:03 PM PST 24
Peak memory 200936 kb
Host smart-890e6461-5e22-4c55-a460-7bbdd02b659d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696508014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3696508014
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1239416417
Short name T860
Test name
Test status
Simulation time 407742088 ps
CPU time 0.85 seconds
Started Feb 29 12:56:42 PM PST 24
Finished Feb 29 12:56:43 PM PST 24
Peak memory 200728 kb
Host smart-95c2dbb5-5575-4e87-8d83-bdb712fb4a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239416417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1239416417
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.531295978
Short name T840
Test name
Test status
Simulation time 2421136607 ps
CPU time 5.51 seconds
Started Feb 29 12:57:02 PM PST 24
Finished Feb 29 12:57:08 PM PST 24
Peak memory 201024 kb
Host smart-77665ca1-afc2-4f3f-8e4b-9a32c5b3d456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531295978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.531295978
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3912613360
Short name T862
Test name
Test status
Simulation time 4735128814 ps
CPU time 2.65 seconds
Started Feb 29 12:56:54 PM PST 24
Finished Feb 29 12:56:57 PM PST 24
Peak memory 201292 kb
Host smart-32cb876b-40cd-4baa-89ec-b89d28fc90a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912613360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3912613360
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3143034046
Short name T841
Test name
Test status
Simulation time 580939693 ps
CPU time 2.11 seconds
Started Feb 29 12:56:55 PM PST 24
Finished Feb 29 12:56:58 PM PST 24
Peak memory 200920 kb
Host smart-c369966c-eb7d-4524-a7fa-97dce135fddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143034046 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3143034046
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.886078973
Short name T838
Test name
Test status
Simulation time 450216128 ps
CPU time 1.74 seconds
Started Feb 29 12:56:55 PM PST 24
Finished Feb 29 12:56:57 PM PST 24
Peak memory 200908 kb
Host smart-81f2f727-e06a-4f69-8662-6da138c9ac01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886078973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.886078973
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2386069467
Short name T876
Test name
Test status
Simulation time 527360531 ps
CPU time 1.23 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:01 PM PST 24
Peak memory 200836 kb
Host smart-ee43ba89-340d-428d-9507-fe87faa867bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386069467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2386069467
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.837929309
Short name T867
Test name
Test status
Simulation time 5450771653 ps
CPU time 12.84 seconds
Started Feb 29 12:57:18 PM PST 24
Finished Feb 29 12:57:31 PM PST 24
Peak memory 201264 kb
Host smart-a3d5189c-739a-481f-b643-03b2d051952b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837929309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.837929309
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3879574175
Short name T885
Test name
Test status
Simulation time 567561278 ps
CPU time 2.41 seconds
Started Feb 29 12:57:01 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 201204 kb
Host smart-013c35bc-d172-426b-aee3-ed729a53e945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879574175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3879574175
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3782542498
Short name T847
Test name
Test status
Simulation time 9095818302 ps
CPU time 21.9 seconds
Started Feb 29 12:56:55 PM PST 24
Finished Feb 29 12:57:17 PM PST 24
Peak memory 201220 kb
Host smart-b4854208-1f98-410a-b61f-5f3fe12915c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782542498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3782542498
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4031066989
Short name T901
Test name
Test status
Simulation time 637123717 ps
CPU time 1.74 seconds
Started Feb 29 12:56:54 PM PST 24
Finished Feb 29 12:56:56 PM PST 24
Peak memory 200988 kb
Host smart-175df9c2-4e6a-4c07-8bd0-6b21d29899f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031066989 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4031066989
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3563407921
Short name T899
Test name
Test status
Simulation time 484015112 ps
CPU time 0.98 seconds
Started Feb 29 12:57:01 PM PST 24
Finished Feb 29 12:57:03 PM PST 24
Peak memory 200960 kb
Host smart-ad3f5b93-c215-4b7c-8248-e2dc2554e825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563407921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3563407921
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3443110570
Short name T850
Test name
Test status
Simulation time 491746028 ps
CPU time 1.78 seconds
Started Feb 29 12:57:02 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 200664 kb
Host smart-9b00bb2e-4ae9-42fa-868a-23e368c093b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443110570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3443110570
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2187154348
Short name T854
Test name
Test status
Simulation time 2165131389 ps
CPU time 1.98 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:57:00 PM PST 24
Peak memory 201012 kb
Host smart-1c1eadd4-3fa7-4979-b346-670aa7558b41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187154348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2187154348
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2714824666
Short name T815
Test name
Test status
Simulation time 393582081 ps
CPU time 1.99 seconds
Started Feb 29 12:56:53 PM PST 24
Finished Feb 29 12:56:55 PM PST 24
Peak memory 201224 kb
Host smart-74655c48-4415-4422-af53-25ea4612daef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714824666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2714824666
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.332811815
Short name T33
Test name
Test status
Simulation time 4821189977 ps
CPU time 4.28 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:56:55 PM PST 24
Peak memory 201192 kb
Host smart-79f1f2f7-01dd-46bd-9082-7ad92c2a54cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332811815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.332811815
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1724512630
Short name T809
Test name
Test status
Simulation time 441115570 ps
CPU time 1.05 seconds
Started Feb 29 12:57:14 PM PST 24
Finished Feb 29 12:57:15 PM PST 24
Peak memory 201028 kb
Host smart-f6e22e06-bd77-464a-a5fd-1340e2d637a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724512630 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1724512630
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2425204794
Short name T858
Test name
Test status
Simulation time 418662439 ps
CPU time 1.02 seconds
Started Feb 29 12:57:05 PM PST 24
Finished Feb 29 12:57:07 PM PST 24
Peak memory 200952 kb
Host smart-686d2b84-feaa-4aa6-90f8-d16cea2125d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425204794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2425204794
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3613882054
Short name T795
Test name
Test status
Simulation time 530271943 ps
CPU time 1.23 seconds
Started Feb 29 12:57:01 PM PST 24
Finished Feb 29 12:57:03 PM PST 24
Peak memory 200620 kb
Host smart-b7b2a45c-2e2d-49be-8d9e-1f5fe806e2f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613882054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3613882054
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1602681326
Short name T896
Test name
Test status
Simulation time 4394003997 ps
CPU time 6 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:06 PM PST 24
Peak memory 201296 kb
Host smart-3322700f-eb88-4434-b550-f0b140ca66db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602681326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1602681326
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.376392431
Short name T823
Test name
Test status
Simulation time 696812737 ps
CPU time 1.63 seconds
Started Feb 29 12:57:06 PM PST 24
Finished Feb 29 12:57:09 PM PST 24
Peak memory 201312 kb
Host smart-097a0b2c-94fe-4997-928c-9786d3849d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376392431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.376392431
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4226182089
Short name T106
Test name
Test status
Simulation time 4189840487 ps
CPU time 6.93 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:57:05 PM PST 24
Peak memory 201232 kb
Host smart-4757c5e7-b911-44a9-a6c3-4760af4ad9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226182089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4226182089
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1319484763
Short name T825
Test name
Test status
Simulation time 506267336 ps
CPU time 1.94 seconds
Started Feb 29 12:57:01 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 200968 kb
Host smart-075fe631-3a1f-4978-ac24-c75e95ac6da7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319484763 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1319484763
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3532964112
Short name T93
Test name
Test status
Simulation time 575090267 ps
CPU time 1.08 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 200852 kb
Host smart-df45fc99-fab0-41ab-b3e1-d4e585451e01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532964112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3532964112
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.643264633
Short name T864
Test name
Test status
Simulation time 285073261 ps
CPU time 1.09 seconds
Started Feb 29 12:56:59 PM PST 24
Finished Feb 29 12:57:01 PM PST 24
Peak memory 200784 kb
Host smart-d8615f56-85a3-470a-a9e4-eab2590827bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643264633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.643264633
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1719615002
Short name T103
Test name
Test status
Simulation time 4734989928 ps
CPU time 3.26 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:05 PM PST 24
Peak memory 201260 kb
Host smart-df18920d-667a-4542-84c9-ee34aef19fcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719615002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1719615002
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.658743837
Short name T857
Test name
Test status
Simulation time 536824064 ps
CPU time 3.44 seconds
Started Feb 29 12:57:22 PM PST 24
Finished Feb 29 12:57:26 PM PST 24
Peak memory 201300 kb
Host smart-52ff2347-f537-4492-8409-31c0e16b4c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658743837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.658743837
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2538346665
Short name T849
Test name
Test status
Simulation time 4519998166 ps
CPU time 3.77 seconds
Started Feb 29 12:57:09 PM PST 24
Finished Feb 29 12:57:13 PM PST 24
Peak memory 201156 kb
Host smart-2792ae38-8afc-4781-b382-da5d1ae758bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538346665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2538346665
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3212441723
Short name T851
Test name
Test status
Simulation time 518678985 ps
CPU time 2.27 seconds
Started Feb 29 12:57:01 PM PST 24
Finished Feb 29 12:57:09 PM PST 24
Peak memory 200968 kb
Host smart-9f3bdeee-cf28-4eb9-8621-1e7c6263fc8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212441723 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3212441723
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2106627991
Short name T89
Test name
Test status
Simulation time 551540791 ps
CPU time 1.44 seconds
Started Feb 29 12:57:10 PM PST 24
Finished Feb 29 12:57:11 PM PST 24
Peak memory 200904 kb
Host smart-ab9a97d4-0c4f-4486-be99-5654a74851e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106627991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2106627991
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.32836493
Short name T797
Test name
Test status
Simulation time 528833521 ps
CPU time 1.82 seconds
Started Feb 29 12:57:07 PM PST 24
Finished Feb 29 12:57:09 PM PST 24
Peak memory 200616 kb
Host smart-6ab866ce-25ad-4d9c-9bd3-a62123e1c590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32836493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.32836493
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1795147313
Short name T893
Test name
Test status
Simulation time 2142289355 ps
CPU time 2 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:57:00 PM PST 24
Peak memory 200860 kb
Host smart-792abb97-2901-4f1b-8ccd-c69318d3e948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795147313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1795147313
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.305608341
Short name T114
Test name
Test status
Simulation time 439957285 ps
CPU time 2.21 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 201228 kb
Host smart-b6fbda91-c482-4c01-9bb2-818dd9dc3524
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305608341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.305608341
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3534615234
Short name T832
Test name
Test status
Simulation time 9020061160 ps
CPU time 4.77 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:56:55 PM PST 24
Peak memory 201264 kb
Host smart-2f713259-76b4-48b5-a1a4-4d260747deb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534615234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3534615234
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2980097529
Short name T115
Test name
Test status
Simulation time 766079823 ps
CPU time 1.19 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:56:58 PM PST 24
Peak memory 200992 kb
Host smart-8de78752-f3fe-4985-840f-b4683c29034f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980097529 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2980097529
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2882425009
Short name T906
Test name
Test status
Simulation time 506459568 ps
CPU time 1.99 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:57:00 PM PST 24
Peak memory 200936 kb
Host smart-a81d81b6-181f-442f-bedc-0d4cd02e52d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882425009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2882425009
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2657675077
Short name T822
Test name
Test status
Simulation time 364133391 ps
CPU time 1.12 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:57:03 PM PST 24
Peak memory 200804 kb
Host smart-0b933515-800a-4d21-9c02-2d3cb5213b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657675077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2657675077
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1578304905
Short name T29
Test name
Test status
Simulation time 2520931916 ps
CPU time 6.2 seconds
Started Feb 29 12:57:15 PM PST 24
Finished Feb 29 12:57:21 PM PST 24
Peak memory 201024 kb
Host smart-09351280-27fb-4dbf-a9ba-a948c54d4d39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578304905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1578304905
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2013995235
Short name T913
Test name
Test status
Simulation time 8408399145 ps
CPU time 7.71 seconds
Started Feb 29 12:56:52 PM PST 24
Finished Feb 29 12:57:00 PM PST 24
Peak memory 200832 kb
Host smart-144ca927-a2be-4102-bcbb-22b64fce7b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013995235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2013995235
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.309135049
Short name T878
Test name
Test status
Simulation time 570797757 ps
CPU time 2.2 seconds
Started Feb 29 12:57:01 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 201016 kb
Host smart-a4a80dd4-74ce-4b81-9669-de2180632a9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309135049 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.309135049
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1042951956
Short name T104
Test name
Test status
Simulation time 551263883 ps
CPU time 1.88 seconds
Started Feb 29 12:57:04 PM PST 24
Finished Feb 29 12:57:06 PM PST 24
Peak memory 200992 kb
Host smart-a7df4301-3b3d-4feb-9055-2adb290d6bd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042951956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1042951956
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.576529888
Short name T873
Test name
Test status
Simulation time 554438529 ps
CPU time 0.93 seconds
Started Feb 29 12:57:03 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 200740 kb
Host smart-deb11d21-d29d-4b17-be00-70b5316e7bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576529888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.576529888
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2619822155
Short name T886
Test name
Test status
Simulation time 2446575824 ps
CPU time 2.26 seconds
Started Feb 29 12:57:07 PM PST 24
Finished Feb 29 12:57:09 PM PST 24
Peak memory 201004 kb
Host smart-2d303dc6-42c8-4169-9272-775d10b5a0e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619822155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2619822155
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4023234634
Short name T829
Test name
Test status
Simulation time 1228699430 ps
CPU time 2.28 seconds
Started Feb 29 12:57:03 PM PST 24
Finished Feb 29 12:57:06 PM PST 24
Peak memory 209508 kb
Host smart-781b1b71-1855-48eb-816d-a9c6fe04943b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023234634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4023234634
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2863940379
Short name T803
Test name
Test status
Simulation time 4344325809 ps
CPU time 10.74 seconds
Started Feb 29 12:57:15 PM PST 24
Finished Feb 29 12:57:27 PM PST 24
Peak memory 201284 kb
Host smart-b830bb57-6243-4014-9f84-2f6ae59d685e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863940379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2863940379
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.4197855105
Short name T88
Test name
Test status
Simulation time 858452874 ps
CPU time 4.33 seconds
Started Feb 29 12:56:49 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 201196 kb
Host smart-31f7200f-26ec-4e6f-b2e4-dcbfea186d24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197855105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.4197855105
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3974584077
Short name T903
Test name
Test status
Simulation time 3943670667 ps
CPU time 11.21 seconds
Started Feb 29 12:56:38 PM PST 24
Finished Feb 29 12:56:49 PM PST 24
Peak memory 201148 kb
Host smart-aef53adb-bf22-4684-bd76-5f8df6a2d58a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974584077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3974584077
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1190034212
Short name T98
Test name
Test status
Simulation time 1224635017 ps
CPU time 3.47 seconds
Started Feb 29 12:56:35 PM PST 24
Finished Feb 29 12:56:40 PM PST 24
Peak memory 201116 kb
Host smart-dfc1537b-7813-426f-8676-0eb0a3d634c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190034212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1190034212
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1604381180
Short name T907
Test name
Test status
Simulation time 517886956 ps
CPU time 2.18 seconds
Started Feb 29 12:56:44 PM PST 24
Finished Feb 29 12:56:47 PM PST 24
Peak memory 200860 kb
Host smart-d5784b0a-5256-4d0c-9012-b6fa55bc6b6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604381180 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1604381180
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4241687982
Short name T90
Test name
Test status
Simulation time 327118488 ps
CPU time 1.6 seconds
Started Feb 29 12:56:52 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 200940 kb
Host smart-5dc82fed-acc6-4029-b1f4-174fefb54e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241687982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.4241687982
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1059485904
Short name T890
Test name
Test status
Simulation time 425361205 ps
CPU time 1.63 seconds
Started Feb 29 12:56:43 PM PST 24
Finished Feb 29 12:56:44 PM PST 24
Peak memory 200872 kb
Host smart-f617afb2-0b1f-4dbb-a65a-1116890aa590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059485904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1059485904
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1145258492
Short name T892
Test name
Test status
Simulation time 5565272050 ps
CPU time 13.38 seconds
Started Feb 29 12:56:36 PM PST 24
Finished Feb 29 12:56:50 PM PST 24
Peak memory 201280 kb
Host smart-877f7b4b-dce5-475b-88e7-83a0a9cbe5e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145258492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1145258492
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.853676235
Short name T833
Test name
Test status
Simulation time 601524571 ps
CPU time 3.56 seconds
Started Feb 29 12:56:53 PM PST 24
Finished Feb 29 12:56:57 PM PST 24
Peak memory 217588 kb
Host smart-cb275493-4991-4303-857e-7c903f84b995
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853676235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.853676235
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2717364471
Short name T875
Test name
Test status
Simulation time 6004538364 ps
CPU time 3.91 seconds
Started Feb 29 12:56:54 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 201192 kb
Host smart-5328f6ed-313d-460c-b922-7cf069b59b15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717364471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2717364471
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2028210651
Short name T791
Test name
Test status
Simulation time 374529887 ps
CPU time 1.53 seconds
Started Feb 29 12:56:58 PM PST 24
Finished Feb 29 12:57:00 PM PST 24
Peak memory 200880 kb
Host smart-ff153789-eebd-49b1-8196-e8f5c155ab5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028210651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2028210651
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.967777219
Short name T813
Test name
Test status
Simulation time 374791434 ps
CPU time 1.12 seconds
Started Feb 29 12:56:48 PM PST 24
Finished Feb 29 12:56:50 PM PST 24
Peak memory 200752 kb
Host smart-d698dbce-8835-4149-9b17-cdfe411122ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967777219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.967777219
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.590681857
Short name T863
Test name
Test status
Simulation time 364449919 ps
CPU time 0.82 seconds
Started Feb 29 12:56:53 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 200868 kb
Host smart-43f0998f-8f44-4f1a-a647-f0a0a3af0774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590681857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.590681857
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2345664038
Short name T842
Test name
Test status
Simulation time 362562069 ps
CPU time 1.01 seconds
Started Feb 29 12:57:03 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 200844 kb
Host smart-b7d492e4-193e-4f76-b61a-c2f4d7af8ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345664038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2345664038
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3582720399
Short name T817
Test name
Test status
Simulation time 505381614 ps
CPU time 0.89 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:02 PM PST 24
Peak memory 200856 kb
Host smart-bc5374bf-752a-4331-95fe-6ca4dd4f0919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582720399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3582720399
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2729729919
Short name T861
Test name
Test status
Simulation time 320427418 ps
CPU time 1.35 seconds
Started Feb 29 12:57:17 PM PST 24
Finished Feb 29 12:57:18 PM PST 24
Peak memory 200896 kb
Host smart-773ef68f-8a00-4579-a8cd-b52d6710b2d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729729919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2729729919
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1533398670
Short name T794
Test name
Test status
Simulation time 398314703 ps
CPU time 1.44 seconds
Started Feb 29 12:57:02 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 200788 kb
Host smart-c578a0ed-7879-4f26-aa5f-4744f3a369c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533398670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1533398670
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.4112362359
Short name T810
Test name
Test status
Simulation time 482099183 ps
CPU time 0.87 seconds
Started Feb 29 12:56:53 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 200732 kb
Host smart-a91d1ba2-3033-4bc7-8192-d3c831a92ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112362359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.4112362359
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1688699637
Short name T799
Test name
Test status
Simulation time 444190989 ps
CPU time 1.32 seconds
Started Feb 29 12:56:52 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 200768 kb
Host smart-7f1cc117-da0a-4bf1-9b77-c339dc4d31e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688699637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1688699637
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4208498164
Short name T908
Test name
Test status
Simulation time 396977008 ps
CPU time 0.84 seconds
Started Feb 29 12:56:52 PM PST 24
Finished Feb 29 12:56:53 PM PST 24
Peak memory 201040 kb
Host smart-7738727c-f02f-4ca2-8a5a-25b5008b5430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208498164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4208498164
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1020670792
Short name T91
Test name
Test status
Simulation time 1012330655 ps
CPU time 4.1 seconds
Started Feb 29 12:56:49 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 201156 kb
Host smart-ba886569-a48e-4b10-9301-d3f5a65d65ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020670792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1020670792
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1045461392
Short name T94
Test name
Test status
Simulation time 838798155 ps
CPU time 2.56 seconds
Started Feb 29 12:56:52 PM PST 24
Finished Feb 29 12:56:55 PM PST 24
Peak memory 200808 kb
Host smart-cf59ff79-8524-4ad7-901d-79f992ff7cc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045461392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1045461392
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1499938776
Short name T821
Test name
Test status
Simulation time 462468328 ps
CPU time 1.06 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:01 PM PST 24
Peak memory 201056 kb
Host smart-e7224ce5-4ee8-4b4b-a712-ea516539281a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499938776 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1499938776
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3986787807
Short name T868
Test name
Test status
Simulation time 358045447 ps
CPU time 1.42 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 200920 kb
Host smart-13b089a2-b09e-44a1-af34-203890468269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986787807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3986787807
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2666959720
Short name T877
Test name
Test status
Simulation time 475917040 ps
CPU time 0.89 seconds
Started Feb 29 12:56:40 PM PST 24
Finished Feb 29 12:56:41 PM PST 24
Peak memory 200736 kb
Host smart-c2ac875b-b05a-44b7-ad46-2256065c0a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666959720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2666959720
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2647168884
Short name T891
Test name
Test status
Simulation time 4025939138 ps
CPU time 9.19 seconds
Started Feb 29 12:57:02 PM PST 24
Finished Feb 29 12:57:11 PM PST 24
Peak memory 201308 kb
Host smart-035e1eba-c51b-49ba-9806-532d1a3f2b8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647168884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2647168884
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3176662468
Short name T865
Test name
Test status
Simulation time 899458276 ps
CPU time 2.97 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:56:53 PM PST 24
Peak memory 209520 kb
Host smart-4293b1c6-b20a-4e18-8aae-b26c9b780947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176662468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3176662468
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3571531813
Short name T831
Test name
Test status
Simulation time 4892136624 ps
CPU time 12.5 seconds
Started Feb 29 12:56:40 PM PST 24
Finished Feb 29 12:56:52 PM PST 24
Peak memory 201216 kb
Host smart-8fb4e474-e3ed-46f8-b217-08d13d2a4184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571531813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3571531813
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3855147087
Short name T790
Test name
Test status
Simulation time 369192695 ps
CPU time 0.79 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:01 PM PST 24
Peak memory 200756 kb
Host smart-bc481d55-0768-45c3-9d85-706dd4ed338e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855147087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3855147087
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3060239233
Short name T804
Test name
Test status
Simulation time 305901374 ps
CPU time 1.34 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:56:58 PM PST 24
Peak memory 201068 kb
Host smart-4045e3f2-3a71-49fe-812e-ed3c84180953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060239233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3060239233
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1250784177
Short name T805
Test name
Test status
Simulation time 458527108 ps
CPU time 1.13 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:03 PM PST 24
Peak memory 200880 kb
Host smart-71d5f61b-3a6f-42b2-a178-a0b82ce5531d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250784177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1250784177
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1402663689
Short name T792
Test name
Test status
Simulation time 455985337 ps
CPU time 0.8 seconds
Started Feb 29 12:57:16 PM PST 24
Finished Feb 29 12:57:17 PM PST 24
Peak memory 200704 kb
Host smart-9b5990c8-c0b2-45f3-b32d-c03651eeb5b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402663689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1402663689
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.344179023
Short name T830
Test name
Test status
Simulation time 495369373 ps
CPU time 1.14 seconds
Started Feb 29 12:57:07 PM PST 24
Finished Feb 29 12:57:09 PM PST 24
Peak memory 200912 kb
Host smart-cc13cf66-a08c-41eb-812f-5753d6ebef41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344179023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.344179023
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.580997740
Short name T889
Test name
Test status
Simulation time 346862212 ps
CPU time 1.35 seconds
Started Feb 29 12:56:44 PM PST 24
Finished Feb 29 12:56:46 PM PST 24
Peak memory 200904 kb
Host smart-81032ea1-f73d-45d3-a694-dadf5be5c4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580997740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.580997740
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3335247156
Short name T800
Test name
Test status
Simulation time 495276995 ps
CPU time 1.2 seconds
Started Feb 29 12:57:02 PM PST 24
Finished Feb 29 12:57:04 PM PST 24
Peak memory 200728 kb
Host smart-46d51cd8-6341-40d0-a26b-88e80b15403e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335247156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3335247156
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.4017061203
Short name T874
Test name
Test status
Simulation time 309555581 ps
CPU time 0.78 seconds
Started Feb 29 12:56:48 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 200776 kb
Host smart-b38e8c5e-d015-40c2-b2b7-2334c7ba359c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017061203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.4017061203
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2051148547
Short name T827
Test name
Test status
Simulation time 378482216 ps
CPU time 1.49 seconds
Started Feb 29 12:57:11 PM PST 24
Finished Feb 29 12:57:13 PM PST 24
Peak memory 200884 kb
Host smart-fd0cc7de-d251-4518-95f9-b32b402f0798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051148547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2051148547
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.664178290
Short name T806
Test name
Test status
Simulation time 472941695 ps
CPU time 1.64 seconds
Started Feb 29 12:57:05 PM PST 24
Finished Feb 29 12:57:07 PM PST 24
Peak memory 200760 kb
Host smart-cd3c99c9-1479-4837-9745-50050933edbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664178290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.664178290
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.460212706
Short name T902
Test name
Test status
Simulation time 553949300 ps
CPU time 3.34 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:57:00 PM PST 24
Peak memory 201184 kb
Host smart-f82c8cdc-2bae-40c7-880d-2dbb715a93be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460212706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.460212706
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1187002195
Short name T27
Test name
Test status
Simulation time 51207311858 ps
CPU time 36.42 seconds
Started Feb 29 12:56:58 PM PST 24
Finished Feb 29 12:57:35 PM PST 24
Peak memory 201248 kb
Host smart-2c0340ee-16ef-4a77-9009-a6880f5be0be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187002195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1187002195
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3503557678
Short name T802
Test name
Test status
Simulation time 889825151 ps
CPU time 1.25 seconds
Started Feb 29 12:56:52 PM PST 24
Finished Feb 29 12:56:53 PM PST 24
Peak memory 200964 kb
Host smart-c2fca000-3b87-44b4-b59d-024bf2b9e6fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503557678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3503557678
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.171615886
Short name T36
Test name
Test status
Simulation time 745568544 ps
CPU time 1.16 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:56:58 PM PST 24
Peak memory 200980 kb
Host smart-fb31246a-8d28-4bc8-b636-87e5f33a6037
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171615886 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.171615886
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3664811220
Short name T856
Test name
Test status
Simulation time 541552441 ps
CPU time 1.98 seconds
Started Feb 29 12:56:45 PM PST 24
Finished Feb 29 12:56:48 PM PST 24
Peak memory 200952 kb
Host smart-9772a438-18b1-4e40-8569-d14b6567edd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664811220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3664811220
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.491969335
Short name T808
Test name
Test status
Simulation time 428670045 ps
CPU time 1.69 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:56:52 PM PST 24
Peak memory 200912 kb
Host smart-e42338ba-b1b4-4f1d-8a3a-1f7b7f327d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491969335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.491969335
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2413056149
Short name T845
Test name
Test status
Simulation time 2462895210 ps
CPU time 3.33 seconds
Started Feb 29 12:56:58 PM PST 24
Finished Feb 29 12:57:02 PM PST 24
Peak memory 200864 kb
Host smart-05fcbdb6-c6aa-40c0-a92e-bf5ad5cb4f29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413056149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2413056149
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3819054541
Short name T113
Test name
Test status
Simulation time 614226447 ps
CPU time 2.25 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:57:00 PM PST 24
Peak memory 201092 kb
Host smart-9a195953-5bff-46c7-b989-89ddc9d5343c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819054541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3819054541
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.875218326
Short name T894
Test name
Test status
Simulation time 4324070290 ps
CPU time 3.77 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 201256 kb
Host smart-302d9eb4-8c7d-4b06-98da-1a6cdd3aab72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875218326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.875218326
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.4229434263
Short name T796
Test name
Test status
Simulation time 452506175 ps
CPU time 1.13 seconds
Started Feb 29 12:57:06 PM PST 24
Finished Feb 29 12:57:07 PM PST 24
Peak memory 200740 kb
Host smart-5c8dfac7-4b4a-4bf4-ab8c-93cf0174e6ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229434263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.4229434263
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1069380552
Short name T852
Test name
Test status
Simulation time 519108182 ps
CPU time 1.68 seconds
Started Feb 29 12:56:55 PM PST 24
Finished Feb 29 12:56:58 PM PST 24
Peak memory 200928 kb
Host smart-6db5f3c4-cf9e-4a74-adb3-ed5a4ae5c371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069380552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1069380552
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2700229755
Short name T844
Test name
Test status
Simulation time 419185295 ps
CPU time 0.79 seconds
Started Feb 29 12:56:58 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 200756 kb
Host smart-8ed0665b-ff88-42bc-a5c2-ad78f112c270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700229755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2700229755
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4000382017
Short name T801
Test name
Test status
Simulation time 455415381 ps
CPU time 1.1 seconds
Started Feb 29 12:56:58 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 200912 kb
Host smart-0003690e-3859-4dd7-8bcb-c0c0a47a0d23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000382017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4000382017
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2734061310
Short name T837
Test name
Test status
Simulation time 446937271 ps
CPU time 1.51 seconds
Started Feb 29 12:57:05 PM PST 24
Finished Feb 29 12:57:07 PM PST 24
Peak memory 200584 kb
Host smart-ff545d34-c2f0-4b70-a5a9-51fe7474f542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734061310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2734061310
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2757417846
Short name T814
Test name
Test status
Simulation time 414983410 ps
CPU time 1.05 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 200800 kb
Host smart-aeeb8f05-6df5-4f20-adfe-61b8bb882052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757417846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2757417846
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.4153782262
Short name T798
Test name
Test status
Simulation time 374375974 ps
CPU time 0.99 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:56:58 PM PST 24
Peak memory 200708 kb
Host smart-c817a856-e286-4f99-aebf-0a8520a73df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153782262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.4153782262
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2483042293
Short name T869
Test name
Test status
Simulation time 534531807 ps
CPU time 0.71 seconds
Started Feb 29 12:57:09 PM PST 24
Finished Feb 29 12:57:10 PM PST 24
Peak memory 200820 kb
Host smart-5397696e-37b9-48c4-acb9-f02227ca3eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483042293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2483042293
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2011923304
Short name T879
Test name
Test status
Simulation time 325411780 ps
CPU time 1.28 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:03 PM PST 24
Peak memory 200568 kb
Host smart-03b7ff5c-d505-482b-a047-f7ab8834ac70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011923304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2011923304
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2508018071
Short name T793
Test name
Test status
Simulation time 400700537 ps
CPU time 0.83 seconds
Started Feb 29 12:57:05 PM PST 24
Finished Feb 29 12:57:06 PM PST 24
Peak memory 200676 kb
Host smart-9eaf87e0-c06b-4dd7-b005-6c122b05dd81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508018071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2508018071
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1452404143
Short name T111
Test name
Test status
Simulation time 704704364 ps
CPU time 1.32 seconds
Started Feb 29 12:56:46 PM PST 24
Finished Feb 29 12:56:48 PM PST 24
Peak memory 200916 kb
Host smart-9f538d70-0af9-4c49-a4ae-550091c65e76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452404143 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1452404143
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.3030407506
Short name T99
Test name
Test status
Simulation time 449687327 ps
CPU time 1.75 seconds
Started Feb 29 12:56:58 PM PST 24
Finished Feb 29 12:57:01 PM PST 24
Peak memory 200940 kb
Host smart-68121b39-c79d-4eff-a1e8-fea76131eb12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030407506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.3030407506
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1246853313
Short name T883
Test name
Test status
Simulation time 459482340 ps
CPU time 0.93 seconds
Started Feb 29 12:56:56 PM PST 24
Finished Feb 29 12:56:58 PM PST 24
Peak memory 200788 kb
Host smart-bf2008bf-fd62-4e68-b076-019a25c4dfb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246853313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1246853313
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.591652039
Short name T828
Test name
Test status
Simulation time 4333258424 ps
CPU time 2.61 seconds
Started Feb 29 12:56:45 PM PST 24
Finished Feb 29 12:56:48 PM PST 24
Peak memory 201264 kb
Host smart-9fdbf0d4-3ea1-4bfd-863a-ad64f97fbd25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591652039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.591652039
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3943575559
Short name T117
Test name
Test status
Simulation time 9040650400 ps
CPU time 21.41 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:57:11 PM PST 24
Peak memory 201396 kb
Host smart-e2019584-765d-4fbe-bf1c-1bbb167ef574
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943575559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3943575559
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.946961039
Short name T866
Test name
Test status
Simulation time 443405987 ps
CPU time 1.11 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:03 PM PST 24
Peak memory 201044 kb
Host smart-8528404c-d793-4277-bc57-4bdf2485f892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946961039 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.946961039
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2162596403
Short name T912
Test name
Test status
Simulation time 512390787 ps
CPU time 1.08 seconds
Started Feb 29 12:56:49 PM PST 24
Finished Feb 29 12:56:51 PM PST 24
Peak memory 200932 kb
Host smart-50c8a006-4eb1-4ece-94a6-785e54177a60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162596403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2162596403
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2561541325
Short name T897
Test name
Test status
Simulation time 458054126 ps
CPU time 1.6 seconds
Started Feb 29 12:56:44 PM PST 24
Finished Feb 29 12:56:46 PM PST 24
Peak memory 200676 kb
Host smart-8fe76906-6990-48c1-bf47-22b865a3f3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561541325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2561541325
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.653197933
Short name T881
Test name
Test status
Simulation time 5110406854 ps
CPU time 5.15 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:06 PM PST 24
Peak memory 201260 kb
Host smart-c156c7d8-1334-45bb-8013-c143e45fe6a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653197933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.653197933
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2114984941
Short name T110
Test name
Test status
Simulation time 467616125 ps
CPU time 2.59 seconds
Started Feb 29 12:57:00 PM PST 24
Finished Feb 29 12:57:03 PM PST 24
Peak memory 201248 kb
Host smart-46e03981-d26d-4000-860b-583616609d82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114984941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2114984941
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3271561999
Short name T812
Test name
Test status
Simulation time 8464455088 ps
CPU time 20.58 seconds
Started Feb 29 12:56:45 PM PST 24
Finished Feb 29 12:57:06 PM PST 24
Peak memory 201144 kb
Host smart-bea4fcae-59a2-4b93-b0c1-5617ef786155
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271561999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3271561999
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3395380382
Short name T871
Test name
Test status
Simulation time 459019717 ps
CPU time 1.38 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:56:52 PM PST 24
Peak memory 200984 kb
Host smart-dfee4dea-6892-48f1-b97f-83061df9e0d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395380382 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3395380382
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1327011210
Short name T895
Test name
Test status
Simulation time 423752546 ps
CPU time 0.9 seconds
Started Feb 29 12:56:55 PM PST 24
Finished Feb 29 12:56:56 PM PST 24
Peak memory 201004 kb
Host smart-0aff572e-450b-4202-89ce-fd202a9342af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327011210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1327011210
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1361244651
Short name T900
Test name
Test status
Simulation time 545359975 ps
CPU time 0.92 seconds
Started Feb 29 12:56:53 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 200680 kb
Host smart-f2f8b11c-6bb1-4d28-8411-687fc933162c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361244651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1361244651
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3173944598
Short name T904
Test name
Test status
Simulation time 4801549086 ps
CPU time 11.87 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:57:02 PM PST 24
Peak memory 201192 kb
Host smart-a52769a1-57a1-4f5d-8033-f464399a94c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173944598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3173944598
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2082173297
Short name T108
Test name
Test status
Simulation time 392808851 ps
CPU time 1.64 seconds
Started Feb 29 12:56:55 PM PST 24
Finished Feb 29 12:56:58 PM PST 24
Peak memory 201252 kb
Host smart-3d5772ae-212c-4d6f-a96f-4e044da6a0e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082173297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2082173297
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1775519311
Short name T819
Test name
Test status
Simulation time 9275750774 ps
CPU time 6.91 seconds
Started Feb 29 12:56:53 PM PST 24
Finished Feb 29 12:57:00 PM PST 24
Peak memory 201272 kb
Host smart-91ff73b9-ce9d-4610-af46-d656b31d531b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775519311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1775519311
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.840294457
Short name T116
Test name
Test status
Simulation time 557032248 ps
CPU time 1.56 seconds
Started Feb 29 12:56:47 PM PST 24
Finished Feb 29 12:56:48 PM PST 24
Peak memory 200996 kb
Host smart-dcd4c100-64bd-4eaf-abc1-929ea7e54683
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840294457 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.840294457
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2825278614
Short name T97
Test name
Test status
Simulation time 397116928 ps
CPU time 1.65 seconds
Started Feb 29 12:56:45 PM PST 24
Finished Feb 29 12:56:48 PM PST 24
Peak memory 200904 kb
Host smart-818fd6f3-1df0-48dd-9309-adf747c64bf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825278614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2825278614
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3293278253
Short name T816
Test name
Test status
Simulation time 347185355 ps
CPU time 1.42 seconds
Started Feb 29 12:56:52 PM PST 24
Finished Feb 29 12:56:53 PM PST 24
Peak memory 200840 kb
Host smart-a1053a3d-89f7-45bc-bfb0-72204baa7171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293278253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3293278253
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.789985548
Short name T914
Test name
Test status
Simulation time 5411557451 ps
CPU time 11.34 seconds
Started Feb 29 12:56:57 PM PST 24
Finished Feb 29 12:57:09 PM PST 24
Peak memory 201236 kb
Host smart-3685af3e-8aee-4e6e-bcaa-c5074a72db41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789985548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.789985548
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2841090587
Short name T834
Test name
Test status
Simulation time 577802273 ps
CPU time 2.66 seconds
Started Feb 29 12:56:52 PM PST 24
Finished Feb 29 12:56:54 PM PST 24
Peak memory 201320 kb
Host smart-e7264b8c-da2a-4386-a0e0-783efb075d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841090587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2841090587
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1713301014
Short name T824
Test name
Test status
Simulation time 7308681228 ps
CPU time 17.83 seconds
Started Feb 29 12:56:41 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 201176 kb
Host smart-14e07a9a-9543-4dca-a21a-3f4a216dc13b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713301014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1713301014
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3425416568
Short name T882
Test name
Test status
Simulation time 557353176 ps
CPU time 1.32 seconds
Started Feb 29 12:57:04 PM PST 24
Finished Feb 29 12:57:06 PM PST 24
Peak memory 201032 kb
Host smart-c13bc380-7f97-4345-87e4-e602ae9ba101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425416568 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3425416568
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1622104910
Short name T101
Test name
Test status
Simulation time 453114417 ps
CPU time 0.89 seconds
Started Feb 29 12:57:29 PM PST 24
Finished Feb 29 12:57:30 PM PST 24
Peak memory 200948 kb
Host smart-2620404e-0b0d-4be6-8004-8f8df952d112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622104910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1622104910
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.299124160
Short name T848
Test name
Test status
Simulation time 526470281 ps
CPU time 0.7 seconds
Started Feb 29 12:56:50 PM PST 24
Finished Feb 29 12:56:51 PM PST 24
Peak memory 200640 kb
Host smart-7d2b9502-3e82-4ac3-838f-3a4def19b2bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299124160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.299124160
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2829548277
Short name T880
Test name
Test status
Simulation time 2443691738 ps
CPU time 2.83 seconds
Started Feb 29 12:56:55 PM PST 24
Finished Feb 29 12:56:59 PM PST 24
Peak memory 200860 kb
Host smart-101eed42-5d39-44b1-abcb-059a2e8d4a56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829548277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2829548277
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.80530438
Short name T853
Test name
Test status
Simulation time 704232325 ps
CPU time 2.22 seconds
Started Feb 29 12:56:55 PM PST 24
Finished Feb 29 12:56:57 PM PST 24
Peak memory 201308 kb
Host smart-a4710ef1-7764-45f2-8268-798620882f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80530438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.80530438
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.599375362
Short name T107
Test name
Test status
Simulation time 9581464921 ps
CPU time 7.21 seconds
Started Feb 29 12:56:45 PM PST 24
Finished Feb 29 12:56:53 PM PST 24
Peak memory 201212 kb
Host smart-d8f9ce7d-3677-4304-b51c-c5e350a203b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599375362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.599375362
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2152201888
Short name T453
Test name
Test status
Simulation time 431518490 ps
CPU time 1.61 seconds
Started Feb 29 01:12:24 PM PST 24
Finished Feb 29 01:12:26 PM PST 24
Peak memory 201104 kb
Host smart-6b976d0c-3547-4499-a35e-778181130f13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152201888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2152201888
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.464670794
Short name T187
Test name
Test status
Simulation time 163785255334 ps
CPU time 266.12 seconds
Started Feb 29 01:12:16 PM PST 24
Finished Feb 29 01:16:42 PM PST 24
Peak memory 201376 kb
Host smart-6c20ed5e-f749-4d68-95d7-39c38aceb381
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464670794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.464670794
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2493068523
Short name T686
Test name
Test status
Simulation time 167276885690 ps
CPU time 369.33 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:18:38 PM PST 24
Peak memory 201392 kb
Host smart-e215210c-5576-4c5e-9031-6a3f468c544b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493068523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2493068523
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1873658547
Short name T51
Test name
Test status
Simulation time 323095902398 ps
CPU time 124.69 seconds
Started Feb 29 01:12:24 PM PST 24
Finished Feb 29 01:14:28 PM PST 24
Peak memory 201372 kb
Host smart-556ff101-0f96-45ed-8159-eee7353ceb38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873658547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1873658547
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.404428590
Short name T551
Test name
Test status
Simulation time 494635718675 ps
CPU time 528.6 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:21:18 PM PST 24
Peak memory 201340 kb
Host smart-8ba978c7-eb22-4598-b2ba-0d54b0bd06aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404428590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.404428590
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1117664258
Short name T540
Test name
Test status
Simulation time 165525072536 ps
CPU time 186.55 seconds
Started Feb 29 01:12:21 PM PST 24
Finished Feb 29 01:15:28 PM PST 24
Peak memory 201304 kb
Host smart-8f62f446-d911-47ca-ab94-f43346a79b51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117664258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1117664258
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2322204715
Short name T479
Test name
Test status
Simulation time 485901673554 ps
CPU time 600.79 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:22:30 PM PST 24
Peak memory 201320 kb
Host smart-f4084932-9133-4630-9b71-ab29ea2b3493
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322204715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2322204715
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1401548696
Short name T505
Test name
Test status
Simulation time 63834281486 ps
CPU time 273.07 seconds
Started Feb 29 01:12:24 PM PST 24
Finished Feb 29 01:16:57 PM PST 24
Peak memory 201692 kb
Host smart-51b879e5-8bc5-49bb-a0d4-6d7671c19512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401548696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1401548696
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2606234987
Short name T566
Test name
Test status
Simulation time 34038660693 ps
CPU time 11.42 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:12:41 PM PST 24
Peak memory 201400 kb
Host smart-facf253f-2bd8-456f-b9c4-b4640d70e615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606234987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2606234987
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1216335496
Short name T618
Test name
Test status
Simulation time 5045277245 ps
CPU time 2.04 seconds
Started Feb 29 01:12:24 PM PST 24
Finished Feb 29 01:12:27 PM PST 24
Peak memory 201196 kb
Host smart-bacfc883-e7ae-411f-8c0f-dd74b16d3503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216335496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1216335496
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2561641045
Short name T509
Test name
Test status
Simulation time 5756623067 ps
CPU time 14.65 seconds
Started Feb 29 01:12:22 PM PST 24
Finished Feb 29 01:12:37 PM PST 24
Peak memory 201056 kb
Host smart-f3471847-3bc1-46bf-98a5-8d2f9dcc9f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561641045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2561641045
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1664976002
Short name T497
Test name
Test status
Simulation time 105464394316 ps
CPU time 316.35 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:17:45 PM PST 24
Peak memory 201668 kb
Host smart-4b24b4d4-0be6-4052-97a7-87c4211c4060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664976002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1664976002
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2794639651
Short name T610
Test name
Test status
Simulation time 116573522229 ps
CPU time 397.59 seconds
Started Feb 29 01:12:17 PM PST 24
Finished Feb 29 01:18:55 PM PST 24
Peak memory 210096 kb
Host smart-ab26f57e-00ec-4e87-bc95-1001d8f735c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794639651 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2794639651
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2535835540
Short name T78
Test name
Test status
Simulation time 478974463 ps
CPU time 1.64 seconds
Started Feb 29 01:12:25 PM PST 24
Finished Feb 29 01:12:26 PM PST 24
Peak memory 201128 kb
Host smart-22116d47-5468-4ed5-bea0-ad74ce6466d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535835540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2535835540
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1450751389
Short name T329
Test name
Test status
Simulation time 500511055877 ps
CPU time 363.86 seconds
Started Feb 29 01:12:16 PM PST 24
Finished Feb 29 01:18:20 PM PST 24
Peak memory 201396 kb
Host smart-673f37f5-9c50-4e88-ae9a-7d3dacf35ede
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450751389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1450751389
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1983352557
Short name T349
Test name
Test status
Simulation time 494980125565 ps
CPU time 286.83 seconds
Started Feb 29 01:12:30 PM PST 24
Finished Feb 29 01:17:17 PM PST 24
Peak memory 201328 kb
Host smart-fe974885-3fde-44c7-a65d-178a6c18104d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983352557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1983352557
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3969624276
Short name T443
Test name
Test status
Simulation time 486090749303 ps
CPU time 1087.96 seconds
Started Feb 29 01:12:15 PM PST 24
Finished Feb 29 01:30:23 PM PST 24
Peak memory 201396 kb
Host smart-a778f159-a073-4a08-9671-4388ae00e56b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969624276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3969624276
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.498140026
Short name T129
Test name
Test status
Simulation time 167024614240 ps
CPU time 387.88 seconds
Started Feb 29 01:12:23 PM PST 24
Finished Feb 29 01:18:51 PM PST 24
Peak memory 201384 kb
Host smart-a2e44266-0cb1-4ae4-89c3-dbe1e6478190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498140026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.498140026
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.805604608
Short name T415
Test name
Test status
Simulation time 328016950155 ps
CPU time 408.92 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:19:17 PM PST 24
Peak memory 201316 kb
Host smart-09511cd9-c492-4350-9d88-c1df6c157009
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=805604608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.805604608
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3126788576
Short name T137
Test name
Test status
Simulation time 162156963596 ps
CPU time 390.8 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:19:00 PM PST 24
Peak memory 201604 kb
Host smart-cc6ef79b-8274-4785-a7e4-583019af094e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126788576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3126788576
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.355575545
Short name T584
Test name
Test status
Simulation time 161084980498 ps
CPU time 83.48 seconds
Started Feb 29 01:12:16 PM PST 24
Finished Feb 29 01:13:40 PM PST 24
Peak memory 201404 kb
Host smart-dba44b89-072c-40de-9490-1f68ccbe00b4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355575545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.355575545
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1538052726
Short name T642
Test name
Test status
Simulation time 101585409167 ps
CPU time 336.28 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:18:05 PM PST 24
Peak memory 201668 kb
Host smart-1d0110ae-e75a-4f42-b204-4b4c3b640b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538052726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1538052726
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.16601941
Short name T219
Test name
Test status
Simulation time 46349156938 ps
CPU time 27.84 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:12:57 PM PST 24
Peak memory 201396 kb
Host smart-7a3e4e87-4d0c-4bbd-835f-7eaa9c855a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16601941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.16601941
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2766924901
Short name T652
Test name
Test status
Simulation time 3113243326 ps
CPU time 2.6 seconds
Started Feb 29 01:12:17 PM PST 24
Finished Feb 29 01:12:20 PM PST 24
Peak memory 201224 kb
Host smart-a4f89bac-e4c8-4d8c-898c-bf7c94667add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766924901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2766924901
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.361296376
Short name T44
Test name
Test status
Simulation time 7646534420 ps
CPU time 19.87 seconds
Started Feb 29 01:12:23 PM PST 24
Finished Feb 29 01:12:43 PM PST 24
Peak memory 217300 kb
Host smart-80979ef1-10e9-4e8a-94e9-0c8f6e2cf41a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361296376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.361296376
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3613926148
Short name T377
Test name
Test status
Simulation time 5908612778 ps
CPU time 4.86 seconds
Started Feb 29 01:12:20 PM PST 24
Finished Feb 29 01:12:26 PM PST 24
Peak memory 201120 kb
Host smart-8ae2800e-618a-476f-b22c-4b7331396ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613926148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3613926148
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1522444030
Short name T722
Test name
Test status
Simulation time 658712152886 ps
CPU time 1228.39 seconds
Started Feb 29 01:12:27 PM PST 24
Finished Feb 29 01:32:56 PM PST 24
Peak memory 201600 kb
Host smart-b5507963-c38f-4473-aa59-4f3d628ec7b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522444030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1522444030
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.856989623
Short name T53
Test name
Test status
Simulation time 16596107762 ps
CPU time 42.24 seconds
Started Feb 29 01:12:20 PM PST 24
Finished Feb 29 01:13:03 PM PST 24
Peak memory 218112 kb
Host smart-dddfbe15-4907-4a20-8048-bcc8f94c4d30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856989623 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.856989623
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.126483051
Short name T201
Test name
Test status
Simulation time 490234186 ps
CPU time 1.18 seconds
Started Feb 29 01:13:06 PM PST 24
Finished Feb 29 01:13:08 PM PST 24
Peak memory 201120 kb
Host smart-3c2f998a-3fb8-43b4-8f0e-4e2981dea089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126483051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.126483051
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2745147099
Short name T159
Test name
Test status
Simulation time 497693036828 ps
CPU time 50.13 seconds
Started Feb 29 01:13:08 PM PST 24
Finished Feb 29 01:13:58 PM PST 24
Peak memory 201476 kb
Host smart-ecea6a04-4c40-4fd2-8901-4247fccaff69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745147099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2745147099
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2557711585
Short name T597
Test name
Test status
Simulation time 487519461479 ps
CPU time 1214.56 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:33:19 PM PST 24
Peak memory 201440 kb
Host smart-fa13de6e-cdd4-4610-be69-2306b2b0efa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557711585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2557711585
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.187266775
Short name T574
Test name
Test status
Simulation time 320180543690 ps
CPU time 58.66 seconds
Started Feb 29 01:13:06 PM PST 24
Finished Feb 29 01:14:05 PM PST 24
Peak memory 201356 kb
Host smart-59d7673b-4c40-49db-a282-46aff987fb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187266775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.187266775
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.314652876
Short name T627
Test name
Test status
Simulation time 492164494056 ps
CPU time 1113.57 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:31:38 PM PST 24
Peak memory 201428 kb
Host smart-31622856-31ef-4bc4-8a3c-241e3ec131a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=314652876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.314652876
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2611871933
Short name T169
Test name
Test status
Simulation time 333881897053 ps
CPU time 170.62 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:15:55 PM PST 24
Peak memory 201404 kb
Host smart-c9d49c59-58d1-4d62-b08d-891042c8d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611871933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2611871933
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.917849367
Short name T734
Test name
Test status
Simulation time 160656580299 ps
CPU time 191.74 seconds
Started Feb 29 01:13:09 PM PST 24
Finished Feb 29 01:16:21 PM PST 24
Peak memory 201384 kb
Host smart-feff81a4-0c5e-428b-99c4-05e69036c0af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=917849367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.917849367
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1815022305
Short name T313
Test name
Test status
Simulation time 518404397145 ps
CPU time 322.27 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:18:29 PM PST 24
Peak memory 201444 kb
Host smart-ee9ae343-5cda-4fce-8219-46b8a38d4758
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815022305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1815022305
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.683240099
Short name T402
Test name
Test status
Simulation time 327314352183 ps
CPU time 422.85 seconds
Started Feb 29 01:13:10 PM PST 24
Finished Feb 29 01:20:13 PM PST 24
Peak memory 201384 kb
Host smart-3d8b8f69-747f-4efa-80be-3f84081df853
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683240099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.683240099
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2937954627
Short name T748
Test name
Test status
Simulation time 123605780738 ps
CPU time 504.24 seconds
Started Feb 29 01:13:08 PM PST 24
Finished Feb 29 01:21:33 PM PST 24
Peak memory 201744 kb
Host smart-a89dc3ac-490c-4c81-9e08-f3e0e4403398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937954627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2937954627
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2501102718
Short name T493
Test name
Test status
Simulation time 23381241836 ps
CPU time 28.67 seconds
Started Feb 29 01:13:12 PM PST 24
Finished Feb 29 01:13:40 PM PST 24
Peak memory 201048 kb
Host smart-c11ea065-ad6b-4b4f-aa6e-cdfe860dc910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501102718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2501102718
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.538628767
Short name T382
Test name
Test status
Simulation time 4003636417 ps
CPU time 2.81 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:13:10 PM PST 24
Peak memory 201276 kb
Host smart-fa6e2b6d-1800-4f2e-baef-e36206778804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538628767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.538628767
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3669534406
Short name T496
Test name
Test status
Simulation time 5627293476 ps
CPU time 7.35 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:13:10 PM PST 24
Peak memory 201156 kb
Host smart-31a12b86-b4bf-4ddf-87f5-10b3e4e72512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669534406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3669534406
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3407342669
Short name T395
Test name
Test status
Simulation time 349636361 ps
CPU time 0.73 seconds
Started Feb 29 01:13:02 PM PST 24
Finished Feb 29 01:13:03 PM PST 24
Peak memory 201088 kb
Host smart-07a1a40d-00b1-4ded-9280-7e54d68cbd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407342669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3407342669
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1385609229
Short name T638
Test name
Test status
Simulation time 331663363726 ps
CPU time 836.83 seconds
Started Feb 29 01:13:01 PM PST 24
Finished Feb 29 01:26:58 PM PST 24
Peak memory 201376 kb
Host smart-2903ee07-a4af-4ff2-993a-d53ee85ecaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385609229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1385609229
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.4080077973
Short name T546
Test name
Test status
Simulation time 158193529644 ps
CPU time 140.88 seconds
Started Feb 29 01:12:58 PM PST 24
Finished Feb 29 01:15:19 PM PST 24
Peak memory 201392 kb
Host smart-8fd10953-766c-4088-9ed4-0edf65229aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080077973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.4080077973
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.4034369812
Short name T763
Test name
Test status
Simulation time 324239101330 ps
CPU time 344.03 seconds
Started Feb 29 01:13:08 PM PST 24
Finished Feb 29 01:18:52 PM PST 24
Peak memory 201468 kb
Host smart-f63afe83-e266-47a0-bf55-96cb03f44d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034369812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4034369812
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1759190691
Short name T680
Test name
Test status
Simulation time 161981481629 ps
CPU time 312.57 seconds
Started Feb 29 01:13:08 PM PST 24
Finished Feb 29 01:18:21 PM PST 24
Peak memory 201472 kb
Host smart-a4c59261-70bb-4ec0-b62b-1d53774c97e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759190691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1759190691
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2477101407
Short name T348
Test name
Test status
Simulation time 170530244936 ps
CPU time 393.31 seconds
Started Feb 29 01:13:01 PM PST 24
Finished Feb 29 01:19:35 PM PST 24
Peak memory 201312 kb
Host smart-28a7738d-3485-4f10-bd36-be3cac208ae5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477101407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2477101407
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1242454550
Short name T163
Test name
Test status
Simulation time 491405443260 ps
CPU time 266.98 seconds
Started Feb 29 01:13:02 PM PST 24
Finished Feb 29 01:17:29 PM PST 24
Peak memory 201324 kb
Host smart-68f8abca-50bb-4078-86d0-fe6c72ef6551
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242454550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1242454550
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.1059460915
Short name T706
Test name
Test status
Simulation time 126902095580 ps
CPU time 709.23 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:24:52 PM PST 24
Peak memory 201696 kb
Host smart-c35f1296-d031-4d50-848b-73072925cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059460915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.1059460915
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2076030850
Short name T753
Test name
Test status
Simulation time 28831452264 ps
CPU time 18.91 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:13:22 PM PST 24
Peak memory 201184 kb
Host smart-17f6d415-6b8d-4833-961f-7a4f48b5a852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076030850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2076030850
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.4135510096
Short name T543
Test name
Test status
Simulation time 4870386810 ps
CPU time 11.83 seconds
Started Feb 29 01:13:00 PM PST 24
Finished Feb 29 01:13:12 PM PST 24
Peak memory 201208 kb
Host smart-c7de7015-e576-4339-bca9-05b657292e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135510096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.4135510096
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.391225043
Short name T498
Test name
Test status
Simulation time 5956006749 ps
CPU time 7.29 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:13:10 PM PST 24
Peak memory 201156 kb
Host smart-4aa7a3ea-a25e-48dc-bc65-d8e5e2db5da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391225043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.391225043
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.39388243
Short name T118
Test name
Test status
Simulation time 4605378005 ps
CPU time 5.36 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:13:08 PM PST 24
Peak memory 201116 kb
Host smart-896ee0ab-efb4-44d7-8279-265654c046e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39388243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.39388243
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2542023542
Short name T640
Test name
Test status
Simulation time 59930100181 ps
CPU time 123.39 seconds
Started Feb 29 01:13:02 PM PST 24
Finished Feb 29 01:15:06 PM PST 24
Peak memory 201508 kb
Host smart-4ea6664c-3854-4ddf-87eb-1b7dbdbc594e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542023542 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2542023542
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1791845125
Short name T548
Test name
Test status
Simulation time 532057930 ps
CPU time 1.77 seconds
Started Feb 29 01:13:06 PM PST 24
Finished Feb 29 01:13:08 PM PST 24
Peak memory 201204 kb
Host smart-beb4e983-89fd-4f05-915b-38e605326761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791845125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1791845125
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2609974932
Short name T676
Test name
Test status
Simulation time 334543362741 ps
CPU time 802.92 seconds
Started Feb 29 01:13:05 PM PST 24
Finished Feb 29 01:26:28 PM PST 24
Peak memory 201408 kb
Host smart-8786f554-836c-4efe-92ad-a3eaa86e6fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609974932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2609974932
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1013102618
Short name T608
Test name
Test status
Simulation time 496258987940 ps
CPU time 1206.01 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:33:09 PM PST 24
Peak memory 201396 kb
Host smart-cbe7b9d3-bc33-4fe4-934b-c4d782451abb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013102618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1013102618
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1450236800
Short name T466
Test name
Test status
Simulation time 484696659125 ps
CPU time 1116.98 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:31:40 PM PST 24
Peak memory 201396 kb
Host smart-20362d02-286d-4ea4-9870-ba5bb812f7b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450236800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1450236800
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.219582472
Short name T736
Test name
Test status
Simulation time 330155755498 ps
CPU time 518.16 seconds
Started Feb 29 01:13:06 PM PST 24
Finished Feb 29 01:21:45 PM PST 24
Peak memory 201296 kb
Host smart-f376b039-d0ee-4af0-b16a-c26719b465ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219582472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.219582472
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.292432808
Short name T768
Test name
Test status
Simulation time 36362490113 ps
CPU time 21.7 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:13:26 PM PST 24
Peak memory 201212 kb
Host smart-e0dcd932-5d12-4b19-9763-520f5b479489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292432808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.292432808
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1421261402
Short name T721
Test name
Test status
Simulation time 4806537168 ps
CPU time 12.01 seconds
Started Feb 29 01:13:05 PM PST 24
Finished Feb 29 01:13:17 PM PST 24
Peak memory 201104 kb
Host smart-efbfee37-ed11-4277-8f55-677a53e3d36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421261402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1421261402
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3182320892
Short name T442
Test name
Test status
Simulation time 5826799129 ps
CPU time 3.9 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:13:07 PM PST 24
Peak memory 201208 kb
Host smart-f7f53090-05ff-4828-a421-70140020c6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182320892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3182320892
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2380931643
Short name T214
Test name
Test status
Simulation time 63404239422 ps
CPU time 65.33 seconds
Started Feb 29 01:13:06 PM PST 24
Finished Feb 29 01:14:12 PM PST 24
Peak memory 201576 kb
Host smart-dfc6e6b5-9a40-4e42-a70c-2d7e2ec283a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380931643 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2380931643
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.818066228
Short name T572
Test name
Test status
Simulation time 393507445 ps
CPU time 1.47 seconds
Started Feb 29 01:13:12 PM PST 24
Finished Feb 29 01:13:13 PM PST 24
Peak memory 200932 kb
Host smart-cc6bec6b-d532-4951-be08-48d6171f1b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818066228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.818066228
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.837636039
Short name T689
Test name
Test status
Simulation time 325469431009 ps
CPU time 408.97 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:19:56 PM PST 24
Peak memory 201448 kb
Host smart-e4d75f4a-5f9e-4094-a513-db2398ade1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837636039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.837636039
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2091827905
Short name T589
Test name
Test status
Simulation time 168694059832 ps
CPU time 408.08 seconds
Started Feb 29 01:13:10 PM PST 24
Finished Feb 29 01:19:58 PM PST 24
Peak memory 201480 kb
Host smart-e8700b84-a59b-438a-ae2c-1565e86c7b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091827905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2091827905
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3315598438
Short name T471
Test name
Test status
Simulation time 167607716618 ps
CPU time 379.88 seconds
Started Feb 29 01:13:05 PM PST 24
Finished Feb 29 01:19:26 PM PST 24
Peak memory 201388 kb
Host smart-386fc1db-dd77-4e0a-88d0-8f6675e6f727
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315598438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3315598438
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2166831244
Short name T17
Test name
Test status
Simulation time 493783020487 ps
CPU time 1127.75 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:31:51 PM PST 24
Peak memory 201412 kb
Host smart-cff5cb03-10f2-4a31-8f8e-dc13fdd989e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166831244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2166831244
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3194504903
Short name T625
Test name
Test status
Simulation time 328349018683 ps
CPU time 740.69 seconds
Started Feb 29 01:13:08 PM PST 24
Finished Feb 29 01:25:29 PM PST 24
Peak memory 201464 kb
Host smart-fd958b04-a74b-4aa1-8869-3b8bc44366f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194504903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3194504903
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1875331477
Short name T473
Test name
Test status
Simulation time 490191481748 ps
CPU time 1113.2 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:31:40 PM PST 24
Peak memory 201460 kb
Host smart-947a7d46-0804-4656-bcba-ce4f0bb7b2dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875331477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1875331477
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2891518077
Short name T708
Test name
Test status
Simulation time 22190291268 ps
CPU time 26.89 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:13:34 PM PST 24
Peak memory 201180 kb
Host smart-a1262fe0-a9d7-4218-9aba-6f3ffed3a151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891518077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2891518077
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2952366371
Short name T447
Test name
Test status
Simulation time 5039354056 ps
CPU time 12.15 seconds
Started Feb 29 01:13:08 PM PST 24
Finished Feb 29 01:13:20 PM PST 24
Peak memory 201272 kb
Host smart-40dee28b-65c3-4a9d-898f-ad58a7bdc629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952366371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2952366371
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.4115993463
Short name T440
Test name
Test status
Simulation time 5878062905 ps
CPU time 7.48 seconds
Started Feb 29 01:13:06 PM PST 24
Finished Feb 29 01:13:14 PM PST 24
Peak memory 201260 kb
Host smart-c2510835-e608-4ca1-80d0-121f3de27a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115993463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.4115993463
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1377957503
Short name T658
Test name
Test status
Simulation time 173647578750 ps
CPU time 202.85 seconds
Started Feb 29 01:13:09 PM PST 24
Finished Feb 29 01:16:32 PM PST 24
Peak memory 201376 kb
Host smart-53da99f6-c9f6-4656-b9fa-cbeb4b0ed819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377957503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1377957503
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4263848794
Short name T781
Test name
Test status
Simulation time 345852423 ps
CPU time 0.79 seconds
Started Feb 29 01:13:15 PM PST 24
Finished Feb 29 01:13:16 PM PST 24
Peak memory 201160 kb
Host smart-bc6d679d-3198-472c-87f1-5f999c724241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263848794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4263848794
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1501949903
Short name T273
Test name
Test status
Simulation time 164061563029 ps
CPU time 25.34 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:13:32 PM PST 24
Peak memory 201460 kb
Host smart-32a4f4cd-d810-447c-83cc-c4ebbea0fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501949903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1501949903
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.631308286
Short name T142
Test name
Test status
Simulation time 162086422767 ps
CPU time 366.72 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:19:11 PM PST 24
Peak memory 201340 kb
Host smart-d9c629d3-ddbb-4ef9-a48d-30d48a86f15b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=631308286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.631308286
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1801024604
Short name T2
Test name
Test status
Simulation time 327678689922 ps
CPU time 376.88 seconds
Started Feb 29 01:13:11 PM PST 24
Finished Feb 29 01:19:28 PM PST 24
Peak memory 201424 kb
Host smart-25af8cec-24fb-46fd-bd7f-b2bfc5dbf016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801024604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1801024604
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.1803543139
Short name T153
Test name
Test status
Simulation time 487656824679 ps
CPU time 146 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:15:33 PM PST 24
Peak memory 201452 kb
Host smart-865f07f7-fb97-4f87-81ea-1aa8177f45c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803543139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.1803543139
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.726929194
Short name T784
Test name
Test status
Simulation time 504997725244 ps
CPU time 563.55 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:22:28 PM PST 24
Peak memory 201384 kb
Host smart-b30e7ed8-2bdd-42f1-9187-033d380d5d68
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726929194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.726929194
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1809981542
Short name T602
Test name
Test status
Simulation time 167597797117 ps
CPU time 103.02 seconds
Started Feb 29 01:13:05 PM PST 24
Finished Feb 29 01:14:48 PM PST 24
Peak memory 201640 kb
Host smart-89e1e355-6a63-4c3d-8b31-0512e7c0171e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809981542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1809981542
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1983333598
Short name T487
Test name
Test status
Simulation time 131167017167 ps
CPU time 429.68 seconds
Started Feb 29 01:13:18 PM PST 24
Finished Feb 29 01:20:29 PM PST 24
Peak memory 201732 kb
Host smart-28b98de1-e3f2-4564-b2d1-cbab80061ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983333598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1983333598
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1134300189
Short name T634
Test name
Test status
Simulation time 24441941389 ps
CPU time 13.6 seconds
Started Feb 29 01:13:12 PM PST 24
Finished Feb 29 01:13:25 PM PST 24
Peak memory 201048 kb
Host smart-5bdc7827-5e5c-4f98-934a-4ecea2efa5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134300189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1134300189
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.941039478
Short name T607
Test name
Test status
Simulation time 4026099068 ps
CPU time 9.77 seconds
Started Feb 29 01:13:09 PM PST 24
Finished Feb 29 01:13:19 PM PST 24
Peak memory 201200 kb
Host smart-15fb49ba-77f4-4625-9bce-ffcd12a0a1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941039478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.941039478
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3544449066
Short name T752
Test name
Test status
Simulation time 5994016971 ps
CPU time 4.77 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:13:09 PM PST 24
Peak memory 201200 kb
Host smart-740bfb24-fde7-4b3b-8d1a-bc4964713fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544449066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3544449066
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1360160311
Short name T744
Test name
Test status
Simulation time 469379650 ps
CPU time 1.47 seconds
Started Feb 29 01:13:14 PM PST 24
Finished Feb 29 01:13:15 PM PST 24
Peak memory 201088 kb
Host smart-835195c2-3bbb-43b2-94b5-afac2132b46d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360160311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1360160311
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3089087033
Short name T357
Test name
Test status
Simulation time 476437827276 ps
CPU time 371.82 seconds
Started Feb 29 01:13:11 PM PST 24
Finished Feb 29 01:19:23 PM PST 24
Peak memory 201320 kb
Host smart-06d5ff7a-8b13-4a69-bfb3-89f5bd96d061
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089087033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3089087033
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3770113459
Short name T334
Test name
Test status
Simulation time 329227167378 ps
CPU time 766.25 seconds
Started Feb 29 01:13:13 PM PST 24
Finished Feb 29 01:25:59 PM PST 24
Peak memory 201460 kb
Host smart-00e64b82-513a-4535-837a-aaefa60913c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770113459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3770113459
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.477652073
Short name T308
Test name
Test status
Simulation time 331208515287 ps
CPU time 781.96 seconds
Started Feb 29 01:13:15 PM PST 24
Finished Feb 29 01:26:17 PM PST 24
Peak memory 201520 kb
Host smart-3e8f421c-68e9-41ed-8758-47745903f937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477652073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.477652073
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3738241346
Short name T580
Test name
Test status
Simulation time 331251393037 ps
CPU time 646.85 seconds
Started Feb 29 01:13:11 PM PST 24
Finished Feb 29 01:23:58 PM PST 24
Peak memory 201388 kb
Host smart-ad66b3a1-ad35-4a0f-af26-7d7479ddc521
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738241346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3738241346
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3265732552
Short name T132
Test name
Test status
Simulation time 327133959385 ps
CPU time 359.99 seconds
Started Feb 29 01:13:11 PM PST 24
Finished Feb 29 01:19:11 PM PST 24
Peak memory 201488 kb
Host smart-120c9320-190f-4536-ae1d-114d39116d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265732552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3265732552
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2446684447
Short name T578
Test name
Test status
Simulation time 497537921903 ps
CPU time 581.18 seconds
Started Feb 29 01:13:12 PM PST 24
Finished Feb 29 01:22:53 PM PST 24
Peak memory 201484 kb
Host smart-51bc7ad6-3f4d-430f-98b1-7570f90ea942
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446684447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2446684447
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.738411564
Short name T278
Test name
Test status
Simulation time 337100809967 ps
CPU time 734.16 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:25:33 PM PST 24
Peak memory 201292 kb
Host smart-9e588932-be78-41f5-a095-0387747d9fa0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738411564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.738411564
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2232439964
Short name T745
Test name
Test status
Simulation time 489320254083 ps
CPU time 276.8 seconds
Started Feb 29 01:13:18 PM PST 24
Finished Feb 29 01:17:56 PM PST 24
Peak memory 201372 kb
Host smart-38bdcae1-afb2-4fb3-9b4f-07d49ce9b376
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232439964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2232439964
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2822152117
Short name T506
Test name
Test status
Simulation time 119567684246 ps
CPU time 394.58 seconds
Started Feb 29 01:13:18 PM PST 24
Finished Feb 29 01:19:54 PM PST 24
Peak memory 201668 kb
Host smart-453c9823-a5fa-4df6-9e09-d74054c78d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822152117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2822152117
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2232187580
Short name T373
Test name
Test status
Simulation time 46402352798 ps
CPU time 105.73 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:15:04 PM PST 24
Peak memory 201400 kb
Host smart-4eeceea6-b97c-44c0-8321-64deb014f3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232187580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2232187580
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1043041977
Short name T599
Test name
Test status
Simulation time 3016513808 ps
CPU time 8.19 seconds
Started Feb 29 01:13:19 PM PST 24
Finished Feb 29 01:13:28 PM PST 24
Peak memory 201200 kb
Host smart-d5ffdc86-42ee-4260-a1ed-07644c4f6ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043041977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1043041977
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3525421444
Short name T380
Test name
Test status
Simulation time 5628047102 ps
CPU time 2.6 seconds
Started Feb 29 01:13:18 PM PST 24
Finished Feb 29 01:13:21 PM PST 24
Peak memory 201196 kb
Host smart-273c53ee-6177-4b3b-b12e-47586c2cc59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525421444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3525421444
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2118313286
Short name T332
Test name
Test status
Simulation time 167952457696 ps
CPU time 237.47 seconds
Started Feb 29 01:13:13 PM PST 24
Finished Feb 29 01:17:11 PM PST 24
Peak memory 201448 kb
Host smart-19cc98fa-19da-48a7-acee-0c6928328030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118313286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2118313286
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4221831673
Short name T494
Test name
Test status
Simulation time 104320483947 ps
CPU time 387.97 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:19:46 PM PST 24
Peak memory 210012 kb
Host smart-f626bf64-ae1d-4df2-8679-6eacec2f8807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221831673 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4221831673
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1588125222
Short name T38
Test name
Test status
Simulation time 409719454 ps
CPU time 0.73 seconds
Started Feb 29 01:13:20 PM PST 24
Finished Feb 29 01:13:21 PM PST 24
Peak memory 201116 kb
Host smart-e7da0dca-c10a-4b2f-bcc2-b19a9646172f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588125222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1588125222
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2920575910
Short name T783
Test name
Test status
Simulation time 160691527372 ps
CPU time 183.55 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:16:22 PM PST 24
Peak memory 201600 kb
Host smart-57cad7f5-06ad-48db-a6a8-e8db23f6e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920575910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2920575910
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1432687965
Short name T703
Test name
Test status
Simulation time 326918396899 ps
CPU time 762.16 seconds
Started Feb 29 01:13:14 PM PST 24
Finished Feb 29 01:25:56 PM PST 24
Peak memory 201448 kb
Host smart-c5e1f101-2f2b-40b6-8e24-cfd2d7f070a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432687965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1432687965
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3830320966
Short name T573
Test name
Test status
Simulation time 492393934644 ps
CPU time 1034.62 seconds
Started Feb 29 01:13:18 PM PST 24
Finished Feb 29 01:30:34 PM PST 24
Peak memory 201420 kb
Host smart-b73f9e27-4ea4-4364-a02a-6da1a61a5868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830320966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3830320966
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.576292166
Short name T210
Test name
Test status
Simulation time 163097311801 ps
CPU time 358.98 seconds
Started Feb 29 01:13:13 PM PST 24
Finished Feb 29 01:19:12 PM PST 24
Peak memory 201380 kb
Host smart-52e42ba3-92f9-48de-a883-d581fce756a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=576292166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.576292166
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1314192366
Short name T352
Test name
Test status
Simulation time 326108961777 ps
CPU time 200.03 seconds
Started Feb 29 01:13:20 PM PST 24
Finished Feb 29 01:16:41 PM PST 24
Peak memory 201304 kb
Host smart-02ed4611-f0bd-4176-b98f-6ec85fc4e8c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314192366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1314192366
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3399280233
Short name T733
Test name
Test status
Simulation time 325751164526 ps
CPU time 193.71 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:16:31 PM PST 24
Peak memory 201452 kb
Host smart-1210fd8f-ab0c-420f-b586-0a2580028b76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399280233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3399280233
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.780797787
Short name T478
Test name
Test status
Simulation time 92130946198 ps
CPU time 463.69 seconds
Started Feb 29 01:13:16 PM PST 24
Finished Feb 29 01:21:01 PM PST 24
Peak memory 201932 kb
Host smart-b34572b0-1c76-40a9-a10c-4ccb675ccbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780797787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.780797787
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2394707678
Short name T560
Test name
Test status
Simulation time 23673348712 ps
CPU time 13.81 seconds
Started Feb 29 01:13:15 PM PST 24
Finished Feb 29 01:13:29 PM PST 24
Peak memory 201176 kb
Host smart-75bc73de-6423-40d7-a0a3-0ea4b8ebb3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394707678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2394707678
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1079014172
Short name T481
Test name
Test status
Simulation time 3834482694 ps
CPU time 9.56 seconds
Started Feb 29 01:13:16 PM PST 24
Finished Feb 29 01:13:26 PM PST 24
Peak memory 201404 kb
Host smart-5195b187-1c7f-4812-a82e-42c8ae0b9722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079014172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1079014172
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.526997699
Short name T426
Test name
Test status
Simulation time 6197222253 ps
CPU time 2.56 seconds
Started Feb 29 01:13:13 PM PST 24
Finished Feb 29 01:13:16 PM PST 24
Peak memory 201136 kb
Host smart-25df14f2-75e9-45bd-a882-55fc1cf3bb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526997699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.526997699
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.271358264
Short name T112
Test name
Test status
Simulation time 5515679089 ps
CPU time 3.64 seconds
Started Feb 29 01:13:14 PM PST 24
Finished Feb 29 01:13:18 PM PST 24
Peak memory 201148 kb
Host smart-8bf9ce13-5b7f-4b41-be68-fa2359668c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271358264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
271358264
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.4121253493
Short name T571
Test name
Test status
Simulation time 34216453237 ps
CPU time 119.73 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:15:17 PM PST 24
Peak memory 210288 kb
Host smart-5368fc6b-e22c-4694-9f8b-e773507a8718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121253493 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.4121253493
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2914365559
Short name T647
Test name
Test status
Simulation time 469734689 ps
CPU time 1.69 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:13:20 PM PST 24
Peak memory 201112 kb
Host smart-5e45c848-7834-477f-9eb9-e031dd2adc0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914365559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2914365559
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.985059594
Short name T314
Test name
Test status
Simulation time 171619599823 ps
CPU time 220.29 seconds
Started Feb 29 01:13:16 PM PST 24
Finished Feb 29 01:16:57 PM PST 24
Peak memory 201456 kb
Host smart-894e88a4-660f-4278-a31a-ddf43789b1b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985059594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.985059594
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3478983178
Short name T693
Test name
Test status
Simulation time 163127594780 ps
CPU time 372.98 seconds
Started Feb 29 01:13:15 PM PST 24
Finished Feb 29 01:19:29 PM PST 24
Peak memory 201448 kb
Host smart-a7ca92c1-ba7f-4046-9dd1-c8c08d4e0f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478983178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3478983178
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1525868613
Short name T436
Test name
Test status
Simulation time 318808209953 ps
CPU time 721.85 seconds
Started Feb 29 01:13:18 PM PST 24
Finished Feb 29 01:25:21 PM PST 24
Peak memory 201388 kb
Host smart-02230bd4-a357-4bf7-b68f-33f9211394f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525868613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1525868613
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1861810487
Short name T179
Test name
Test status
Simulation time 495967725707 ps
CPU time 153.72 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:15:52 PM PST 24
Peak memory 201416 kb
Host smart-e04b65f9-7823-45d9-b045-a3cd3ef570d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861810487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1861810487
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.336731041
Short name T558
Test name
Test status
Simulation time 165999504006 ps
CPU time 197.21 seconds
Started Feb 29 01:13:14 PM PST 24
Finished Feb 29 01:16:31 PM PST 24
Peak memory 201364 kb
Host smart-76de9a80-1d94-4e01-8d5f-cd399435644e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=336731041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.336731041
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.838287218
Short name T342
Test name
Test status
Simulation time 538562539338 ps
CPU time 1094.17 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:31:33 PM PST 24
Peak memory 201380 kb
Host smart-c4b38019-72a4-49ee-8330-b016258d782f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838287218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_
wakeup.838287218
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.391678202
Short name T568
Test name
Test status
Simulation time 162408562569 ps
CPU time 87.96 seconds
Started Feb 29 01:13:18 PM PST 24
Finished Feb 29 01:14:47 PM PST 24
Peak memory 201292 kb
Host smart-6037284f-af68-4764-8679-b1f6f7092ec1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391678202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.391678202
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2942090952
Short name T587
Test name
Test status
Simulation time 120176411924 ps
CPU time 453.66 seconds
Started Feb 29 01:13:15 PM PST 24
Finished Feb 29 01:20:49 PM PST 24
Peak memory 201760 kb
Host smart-c6c208f7-8cd2-4a75-842c-749b1fe4ceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942090952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2942090952
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1928577424
Short name T437
Test name
Test status
Simulation time 24535821898 ps
CPU time 26.19 seconds
Started Feb 29 01:13:20 PM PST 24
Finished Feb 29 01:13:47 PM PST 24
Peak memory 201188 kb
Host smart-464be7b9-934b-4179-8138-0cd9f2828f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928577424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1928577424
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3334334081
Short name T198
Test name
Test status
Simulation time 4906002727 ps
CPU time 3.53 seconds
Started Feb 29 01:13:16 PM PST 24
Finished Feb 29 01:13:20 PM PST 24
Peak memory 201124 kb
Host smart-3184edde-99f2-471d-a710-a2192c9e73cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334334081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3334334081
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1780407214
Short name T562
Test name
Test status
Simulation time 5617499475 ps
CPU time 7.66 seconds
Started Feb 29 01:13:14 PM PST 24
Finished Feb 29 01:13:22 PM PST 24
Peak memory 201112 kb
Host smart-279742b6-9031-49db-9564-8dab371143e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780407214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1780407214
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1660569771
Short name T513
Test name
Test status
Simulation time 170400733980 ps
CPU time 103.04 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:15:01 PM PST 24
Peak memory 201396 kb
Host smart-3c52ebd8-dcb8-48b1-954e-5b94f76ece82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660569771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1660569771
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.11032693
Short name T69
Test name
Test status
Simulation time 3270614638 ps
CPU time 9.12 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:13:27 PM PST 24
Peak memory 201520 kb
Host smart-e4271d80-26b6-4318-8f1e-68ae905e3746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11032693 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.11032693
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3974156438
Short name T707
Test name
Test status
Simulation time 607796339 ps
CPU time 0.75 seconds
Started Feb 29 01:13:22 PM PST 24
Finished Feb 29 01:13:23 PM PST 24
Peak memory 201076 kb
Host smart-e6d03e6d-807d-4d42-9b1a-e42f4fc71d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974156438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3974156438
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2540262723
Short name T202
Test name
Test status
Simulation time 327946512666 ps
CPU time 119.17 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:15:16 PM PST 24
Peak memory 201444 kb
Host smart-fffcd82a-9ee5-4342-a80b-e6f249b507ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540262723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2540262723
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2977967232
Short name T330
Test name
Test status
Simulation time 165626549260 ps
CPU time 385.07 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:19:43 PM PST 24
Peak memory 201484 kb
Host smart-72f3d766-1e01-4cc1-9186-774723affc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977967232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2977967232
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1207461358
Short name T425
Test name
Test status
Simulation time 334370647961 ps
CPU time 363.76 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:19:22 PM PST 24
Peak memory 201652 kb
Host smart-b5439ef7-de4b-456e-affa-eda769612c4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207461358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1207461358
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.791219983
Short name T233
Test name
Test status
Simulation time 325637163406 ps
CPU time 742.34 seconds
Started Feb 29 01:13:17 PM PST 24
Finished Feb 29 01:25:41 PM PST 24
Peak memory 201384 kb
Host smart-69307be5-b06b-4f88-90c0-b2f0177f90ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791219983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.791219983
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.3903022312
Short name T454
Test name
Test status
Simulation time 333399984110 ps
CPU time 247.66 seconds
Started Feb 29 01:13:15 PM PST 24
Finished Feb 29 01:17:23 PM PST 24
Peak memory 201396 kb
Host smart-300e8e3e-ccde-438d-9c14-a4c36532e0d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903022312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.3903022312
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1760082940
Short name T522
Test name
Test status
Simulation time 520444447038 ps
CPU time 1271.66 seconds
Started Feb 29 01:13:16 PM PST 24
Finished Feb 29 01:34:28 PM PST 24
Peak memory 201444 kb
Host smart-149db8fe-a512-4882-84d4-d4d783b9a0ad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760082940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1760082940
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3244178564
Short name T591
Test name
Test status
Simulation time 332456104288 ps
CPU time 385.87 seconds
Started Feb 29 01:13:15 PM PST 24
Finished Feb 29 01:19:41 PM PST 24
Peak memory 201416 kb
Host smart-c77199d1-b824-4286-98d1-ef9ef43a408a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244178564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3244178564
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1239337121
Short name T615
Test name
Test status
Simulation time 37064243789 ps
CPU time 23.82 seconds
Started Feb 29 01:13:14 PM PST 24
Finished Feb 29 01:13:38 PM PST 24
Peak memory 201076 kb
Host smart-c80fcd4b-d09c-411a-9db0-301037f47460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239337121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1239337121
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.4106968682
Short name T533
Test name
Test status
Simulation time 4445960111 ps
CPU time 2.62 seconds
Started Feb 29 01:13:19 PM PST 24
Finished Feb 29 01:13:23 PM PST 24
Peak memory 201200 kb
Host smart-23367792-84a1-4fbc-ac23-bf441cd03a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106968682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.4106968682
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1622387130
Short name T149
Test name
Test status
Simulation time 5867912010 ps
CPU time 14.83 seconds
Started Feb 29 01:13:15 PM PST 24
Finished Feb 29 01:13:30 PM PST 24
Peak memory 201180 kb
Host smart-ee824b00-b77b-43a3-a153-698dd8d417bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622387130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1622387130
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3828111566
Short name T331
Test name
Test status
Simulation time 399724630203 ps
CPU time 835.42 seconds
Started Feb 29 01:13:13 PM PST 24
Finished Feb 29 01:27:09 PM PST 24
Peak memory 211976 kb
Host smart-7e09107e-7930-44ca-9689-50c81161b98d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828111566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3828111566
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.440806684
Short name T675
Test name
Test status
Simulation time 54666380959 ps
CPU time 154.9 seconds
Started Feb 29 01:13:13 PM PST 24
Finished Feb 29 01:15:48 PM PST 24
Peak memory 209976 kb
Host smart-1fbb25cb-e551-4243-a484-18bc09d83ebd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440806684 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.440806684
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.488321860
Short name T530
Test name
Test status
Simulation time 407330589 ps
CPU time 0.84 seconds
Started Feb 29 01:13:25 PM PST 24
Finished Feb 29 01:13:26 PM PST 24
Peak memory 201120 kb
Host smart-994e271d-3660-45dc-8459-816ec2bb76e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488321860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.488321860
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3000715099
Short name T629
Test name
Test status
Simulation time 159817324160 ps
CPU time 335.79 seconds
Started Feb 29 01:13:31 PM PST 24
Finished Feb 29 01:19:07 PM PST 24
Peak memory 201440 kb
Host smart-57d9ef27-d0f4-46f9-b083-b33703511615
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000715099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3000715099
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.544344827
Short name T285
Test name
Test status
Simulation time 487755391050 ps
CPU time 585.04 seconds
Started Feb 29 01:13:30 PM PST 24
Finished Feb 29 01:23:16 PM PST 24
Peak memory 201372 kb
Host smart-6e222225-eab9-4f47-acd0-f03cf0e5ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544344827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.544344827
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.690959665
Short name T190
Test name
Test status
Simulation time 483940538338 ps
CPU time 287.85 seconds
Started Feb 29 01:13:19 PM PST 24
Finished Feb 29 01:18:08 PM PST 24
Peak memory 201352 kb
Host smart-aa0fe249-abb4-4916-8e0b-a9d0788b0924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690959665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.690959665
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.4108113557
Short name T735
Test name
Test status
Simulation time 488355935665 ps
CPU time 1043.86 seconds
Started Feb 29 01:13:21 PM PST 24
Finished Feb 29 01:30:45 PM PST 24
Peak memory 201428 kb
Host smart-3bd555c1-4ee6-4379-bc87-4098b59d96bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108113557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.4108113557
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.3541900939
Short name T248
Test name
Test status
Simulation time 491429647007 ps
CPU time 260.55 seconds
Started Feb 29 01:13:23 PM PST 24
Finished Feb 29 01:17:44 PM PST 24
Peak memory 201480 kb
Host smart-db673915-4b6a-4708-b17a-54e345fb7f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541900939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.3541900939
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3218743752
Short name T787
Test name
Test status
Simulation time 500954758704 ps
CPU time 183.02 seconds
Started Feb 29 01:13:19 PM PST 24
Finished Feb 29 01:16:23 PM PST 24
Peak memory 201432 kb
Host smart-0786bf60-88ca-4f08-b03f-59ae43f63b12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218743752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3218743752
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.751906056
Short name T258
Test name
Test status
Simulation time 489579389891 ps
CPU time 548.83 seconds
Started Feb 29 01:13:27 PM PST 24
Finished Feb 29 01:22:36 PM PST 24
Peak memory 201508 kb
Host smart-b2c84d65-e2e8-4294-895d-c02058e966d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751906056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.751906056
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4184853176
Short name T713
Test name
Test status
Simulation time 332481129270 ps
CPU time 180.63 seconds
Started Feb 29 01:13:27 PM PST 24
Finished Feb 29 01:16:28 PM PST 24
Peak memory 201436 kb
Host smart-081027ac-3d38-4560-b43e-4b1f6d3577f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184853176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.4184853176
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4226285143
Short name T363
Test name
Test status
Simulation time 100045454489 ps
CPU time 530.84 seconds
Started Feb 29 01:13:21 PM PST 24
Finished Feb 29 01:22:12 PM PST 24
Peak memory 201652 kb
Host smart-6dad1d7a-843f-49f8-8a45-d843e2293d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226285143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4226285143
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2118788793
Short name T6
Test name
Test status
Simulation time 39670201055 ps
CPU time 42.64 seconds
Started Feb 29 01:13:25 PM PST 24
Finished Feb 29 01:14:08 PM PST 24
Peak memory 201076 kb
Host smart-138fed3e-13ce-4fc6-9aec-4732b5394f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118788793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2118788793
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.4007550458
Short name T381
Test name
Test status
Simulation time 5476204383 ps
CPU time 3.92 seconds
Started Feb 29 01:13:25 PM PST 24
Finished Feb 29 01:13:29 PM PST 24
Peak memory 201192 kb
Host smart-cfc8416a-4c49-4fba-b858-7848f65f8cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007550458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.4007550458
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1957099816
Short name T400
Test name
Test status
Simulation time 5617598994 ps
CPU time 14.23 seconds
Started Feb 29 01:13:24 PM PST 24
Finished Feb 29 01:13:38 PM PST 24
Peak memory 201352 kb
Host smart-7efd188e-d217-4b30-80f8-afc82076b077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957099816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1957099816
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3098245433
Short name T74
Test name
Test status
Simulation time 638947569562 ps
CPU time 311.84 seconds
Started Feb 29 01:13:23 PM PST 24
Finished Feb 29 01:18:35 PM PST 24
Peak memory 210144 kb
Host smart-e746ebb0-ac4a-4c3d-9251-10851c97926b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098245433 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3098245433
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.970321180
Short name T764
Test name
Test status
Simulation time 461697615 ps
CPU time 0.85 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:12:30 PM PST 24
Peak memory 201096 kb
Host smart-a400af8f-2a18-45a7-800c-818a665f8ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970321180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.970321180
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3976257243
Short name T134
Test name
Test status
Simulation time 167296130086 ps
CPU time 394.16 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:19:02 PM PST 24
Peak memory 201344 kb
Host smart-39599361-afb3-483f-8a92-e095eb3deb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976257243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3976257243
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3948525056
Short name T448
Test name
Test status
Simulation time 333766743935 ps
CPU time 149.17 seconds
Started Feb 29 01:12:26 PM PST 24
Finished Feb 29 01:14:55 PM PST 24
Peak memory 201400 kb
Host smart-8cd3af61-3fde-49ca-b52e-40d0db235e70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948525056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3948525056
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1841646489
Short name T501
Test name
Test status
Simulation time 325600901669 ps
CPU time 208.8 seconds
Started Feb 29 01:12:20 PM PST 24
Finished Feb 29 01:15:50 PM PST 24
Peak memory 201368 kb
Host smart-6aa2208a-dd5b-4870-a635-4dbf63b3a544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841646489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1841646489
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2318418603
Short name T576
Test name
Test status
Simulation time 333792787174 ps
CPU time 193.25 seconds
Started Feb 29 01:12:26 PM PST 24
Finished Feb 29 01:15:39 PM PST 24
Peak memory 201456 kb
Host smart-f579605f-7f75-4284-b199-c77d38368527
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318418603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2318418603
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2815953377
Short name T594
Test name
Test status
Simulation time 338454848440 ps
CPU time 806.64 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:25:56 PM PST 24
Peak memory 201460 kb
Host smart-b60d1569-4e48-4900-a038-9a0d259c1218
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815953377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2815953377
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.436314139
Short name T732
Test name
Test status
Simulation time 169815562206 ps
CPU time 103.08 seconds
Started Feb 29 01:12:27 PM PST 24
Finished Feb 29 01:14:11 PM PST 24
Peak memory 201600 kb
Host smart-fe1d193e-a038-4c05-bd65-9933bf4c881a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436314139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.436314139
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2748792949
Short name T623
Test name
Test status
Simulation time 108494239634 ps
CPU time 557.96 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:21:46 PM PST 24
Peak memory 201708 kb
Host smart-98631fe5-a50e-4565-8b67-04247feb16df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748792949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2748792949
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1009246775
Short name T456
Test name
Test status
Simulation time 37469334171 ps
CPU time 18.13 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:12:46 PM PST 24
Peak memory 201208 kb
Host smart-0fdf13b5-22a5-4457-8719-c61ddabe3255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009246775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1009246775
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3729653541
Short name T120
Test name
Test status
Simulation time 4297608525 ps
CPU time 10.48 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:12:39 PM PST 24
Peak memory 201188 kb
Host smart-79a56be7-5a86-4623-ab38-4f130565c0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729653541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3729653541
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2760246031
Short name T42
Test name
Test status
Simulation time 8184723871 ps
CPU time 20.61 seconds
Started Feb 29 01:12:26 PM PST 24
Finished Feb 29 01:12:47 PM PST 24
Peak memory 217308 kb
Host smart-88fb258e-efd1-43c4-8068-d7d5a12bb2f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760246031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2760246031
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2529334646
Short name T457
Test name
Test status
Simulation time 5953403427 ps
CPU time 15.57 seconds
Started Feb 29 01:12:21 PM PST 24
Finished Feb 29 01:12:37 PM PST 24
Peak memory 201072 kb
Host smart-680db55b-3761-4f07-901a-997b9809bfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529334646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2529334646
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3405493652
Short name T271
Test name
Test status
Simulation time 515803996065 ps
CPU time 469.73 seconds
Started Feb 29 01:12:30 PM PST 24
Finished Feb 29 01:20:20 PM PST 24
Peak memory 209976 kb
Host smart-eec69193-e4d1-4f11-be55-3703c7c05e39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405493652 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3405493652
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.4256776999
Short name T417
Test name
Test status
Simulation time 387222796 ps
CPU time 0.8 seconds
Started Feb 29 01:13:22 PM PST 24
Finished Feb 29 01:13:23 PM PST 24
Peak memory 201056 kb
Host smart-b665ffe8-a042-4b92-82a8-b86b39da8a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256776999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.4256776999
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2202260250
Short name T237
Test name
Test status
Simulation time 158315467827 ps
CPU time 374.26 seconds
Started Feb 29 01:13:25 PM PST 24
Finished Feb 29 01:19:39 PM PST 24
Peak memory 201496 kb
Host smart-4746f12c-e622-4a30-92f0-b00a2659cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202260250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2202260250
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1134473407
Short name T251
Test name
Test status
Simulation time 493066087893 ps
CPU time 1188.77 seconds
Started Feb 29 01:13:22 PM PST 24
Finished Feb 29 01:33:11 PM PST 24
Peak memory 201460 kb
Host smart-105a7aec-1624-4a9c-aed6-01bb861699f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134473407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1134473407
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3278222112
Short name T428
Test name
Test status
Simulation time 163559542582 ps
CPU time 78 seconds
Started Feb 29 01:13:26 PM PST 24
Finished Feb 29 01:14:44 PM PST 24
Peak memory 201332 kb
Host smart-0ddbff3c-4dde-468b-90db-b3ff7599683c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278222112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3278222112
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3740904759
Short name T354
Test name
Test status
Simulation time 160395373371 ps
CPU time 99.74 seconds
Started Feb 29 01:13:23 PM PST 24
Finished Feb 29 01:15:03 PM PST 24
Peak memory 201360 kb
Host smart-279c030c-8a72-4e59-a744-7bb380803d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740904759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3740904759
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.381045636
Short name T554
Test name
Test status
Simulation time 491898685898 ps
CPU time 1005.81 seconds
Started Feb 29 01:13:27 PM PST 24
Finished Feb 29 01:30:13 PM PST 24
Peak memory 201440 kb
Host smart-d8b86258-7fad-46d5-8535-818d8761ebfb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=381045636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixe
d.381045636
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.4030409897
Short name T337
Test name
Test status
Simulation time 504983116322 ps
CPU time 1174.72 seconds
Started Feb 29 01:13:29 PM PST 24
Finished Feb 29 01:33:04 PM PST 24
Peak memory 201400 kb
Host smart-8992d028-a2aa-4178-9963-3f5b375ed129
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030409897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.4030409897
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3234583581
Short name T609
Test name
Test status
Simulation time 493699041103 ps
CPU time 1006.43 seconds
Started Feb 29 01:13:30 PM PST 24
Finished Feb 29 01:30:16 PM PST 24
Peak memory 201384 kb
Host smart-abd4013b-9c10-4504-80ac-e90ff545873e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234583581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3234583581
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.424582683
Short name T84
Test name
Test status
Simulation time 124696806053 ps
CPU time 671.94 seconds
Started Feb 29 01:13:31 PM PST 24
Finished Feb 29 01:24:43 PM PST 24
Peak memory 201812 kb
Host smart-a46c43fa-3ecb-45ff-8c48-d4c2e78ef17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424582683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.424582683
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1077992491
Short name T433
Test name
Test status
Simulation time 41347263864 ps
CPU time 22.7 seconds
Started Feb 29 01:13:24 PM PST 24
Finished Feb 29 01:13:46 PM PST 24
Peak memory 201392 kb
Host smart-59a84cb9-84ee-43b8-a967-e8eba297cccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077992491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1077992491
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2589176235
Short name T614
Test name
Test status
Simulation time 3022647128 ps
CPU time 7 seconds
Started Feb 29 01:13:23 PM PST 24
Finished Feb 29 01:13:30 PM PST 24
Peak memory 201104 kb
Host smart-a139a076-332f-41a8-bf25-826bb688abe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589176235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2589176235
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.261427265
Short name T612
Test name
Test status
Simulation time 5773751025 ps
CPU time 4.16 seconds
Started Feb 29 01:13:29 PM PST 24
Finished Feb 29 01:13:33 PM PST 24
Peak memory 201144 kb
Host smart-ec099e70-05ac-42c5-87e3-64c7163bd65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261427265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.261427265
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3429658386
Short name T659
Test name
Test status
Simulation time 476122798 ps
CPU time 0.87 seconds
Started Feb 29 01:13:30 PM PST 24
Finished Feb 29 01:13:32 PM PST 24
Peak memory 201120 kb
Host smart-cb5b25aa-b778-4122-a225-2afab7cb383f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429658386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3429658386
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2438209828
Short name T339
Test name
Test status
Simulation time 314096738605 ps
CPU time 277.25 seconds
Started Feb 29 01:13:27 PM PST 24
Finished Feb 29 01:18:06 PM PST 24
Peak memory 201408 kb
Host smart-f457b51d-f642-4c41-81d4-71378875eab9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438209828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2438209828
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2443516173
Short name T516
Test name
Test status
Simulation time 165772636438 ps
CPU time 368.03 seconds
Started Feb 29 01:13:30 PM PST 24
Finished Feb 29 01:19:39 PM PST 24
Peak memory 201452 kb
Host smart-c7a56f53-113b-445f-8e16-24923ec051e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443516173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2443516173
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1607385439
Short name T422
Test name
Test status
Simulation time 164008833621 ps
CPU time 359.85 seconds
Started Feb 29 01:13:22 PM PST 24
Finished Feb 29 01:19:22 PM PST 24
Peak memory 201324 kb
Host smart-aac14a46-98c8-4895-a080-db388af2e2e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607385439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1607385439
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1100245374
Short name T170
Test name
Test status
Simulation time 331945093815 ps
CPU time 69.41 seconds
Started Feb 29 01:13:28 PM PST 24
Finished Feb 29 01:14:37 PM PST 24
Peak memory 201448 kb
Host smart-18fcda1e-c479-474e-ba63-3dc85af5683c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100245374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1100245374
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3231192798
Short name T697
Test name
Test status
Simulation time 500084715374 ps
CPU time 303.06 seconds
Started Feb 29 01:13:26 PM PST 24
Finished Feb 29 01:18:29 PM PST 24
Peak memory 201340 kb
Host smart-3f089062-9e29-46a1-9fd4-70b0e906de26
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231192798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3231192798
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4262603804
Short name T711
Test name
Test status
Simulation time 90502435279 ps
CPU time 342.2 seconds
Started Feb 29 01:13:27 PM PST 24
Finished Feb 29 01:19:10 PM PST 24
Peak memory 201764 kb
Host smart-407d8cbe-70d0-4b5e-adc1-81804d0945f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262603804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4262603804
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.3550557822
Short name T773
Test name
Test status
Simulation time 29200520903 ps
CPU time 5.88 seconds
Started Feb 29 01:13:27 PM PST 24
Finished Feb 29 01:13:34 PM PST 24
Peak memory 201128 kb
Host smart-58b1519c-7493-44f8-bd8e-612d1f1be48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550557822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.3550557822
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.415620012
Short name T537
Test name
Test status
Simulation time 4790360380 ps
CPU time 3.82 seconds
Started Feb 29 01:13:27 PM PST 24
Finished Feb 29 01:13:32 PM PST 24
Peak memory 201212 kb
Host smart-cd6fb6c2-37a4-44de-b845-aeefa61d15a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415620012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.415620012
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2804801312
Short name T386
Test name
Test status
Simulation time 6054976496 ps
CPU time 3.83 seconds
Started Feb 29 01:13:24 PM PST 24
Finished Feb 29 01:13:28 PM PST 24
Peak memory 201396 kb
Host smart-05a83dd8-5b97-4f2c-bc9e-9d137e2bd1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804801312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2804801312
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4267111369
Short name T85
Test name
Test status
Simulation time 118073475428 ps
CPU time 132.1 seconds
Started Feb 29 01:13:28 PM PST 24
Finished Feb 29 01:15:41 PM PST 24
Peak memory 209996 kb
Host smart-1df859dc-d6eb-4e73-a6ca-b65c011b80a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267111369 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4267111369
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1639136436
Short name T67
Test name
Test status
Simulation time 322926198 ps
CPU time 0.75 seconds
Started Feb 29 01:13:36 PM PST 24
Finished Feb 29 01:13:37 PM PST 24
Peak memory 201348 kb
Host smart-53a3f329-2dfa-4479-86a1-c2ea96c99fb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639136436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1639136436
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3740544984
Short name T702
Test name
Test status
Simulation time 165670594684 ps
CPU time 374.67 seconds
Started Feb 29 01:13:30 PM PST 24
Finished Feb 29 01:19:46 PM PST 24
Peak memory 201384 kb
Host smart-112c5cec-e756-4c5f-8fc1-09004f388c77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740544984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3740544984
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.218055440
Short name T570
Test name
Test status
Simulation time 349915095387 ps
CPU time 360.76 seconds
Started Feb 29 01:13:28 PM PST 24
Finished Feb 29 01:19:29 PM PST 24
Peak memory 201336 kb
Host smart-0f00eac9-241e-4cc7-a935-a8db2cf5e9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218055440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.218055440
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1757866095
Short name T148
Test name
Test status
Simulation time 163807978527 ps
CPU time 115.06 seconds
Started Feb 29 01:13:29 PM PST 24
Finished Feb 29 01:15:25 PM PST 24
Peak memory 201452 kb
Host smart-88873ae7-55c7-448c-b9cc-2d6f24a291cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757866095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1757866095
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3613161220
Short name T644
Test name
Test status
Simulation time 320321660269 ps
CPU time 183.65 seconds
Started Feb 29 01:13:29 PM PST 24
Finished Feb 29 01:16:33 PM PST 24
Peak memory 201352 kb
Host smart-9d5aa484-9bc3-4f0b-8a1e-87334d7011eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613161220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3613161220
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2791688752
Short name T168
Test name
Test status
Simulation time 166079361731 ps
CPU time 39.85 seconds
Started Feb 29 01:13:29 PM PST 24
Finished Feb 29 01:14:09 PM PST 24
Peak memory 201500 kb
Host smart-8dcd5aa4-94ff-4af0-98cd-bc6ddd059320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791688752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2791688752
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1501874974
Short name T145
Test name
Test status
Simulation time 333264112392 ps
CPU time 372.91 seconds
Started Feb 29 01:13:33 PM PST 24
Finished Feb 29 01:19:46 PM PST 24
Peak memory 201384 kb
Host smart-cb0f81cd-cd93-4f1c-b8c6-ce2015feb4a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501874974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1501874974
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2240946965
Short name T532
Test name
Test status
Simulation time 325106090211 ps
CPU time 280.98 seconds
Started Feb 29 01:13:31 PM PST 24
Finished Feb 29 01:18:12 PM PST 24
Peak memory 201380 kb
Host smart-4b4e065b-3964-4afd-9166-e500ed553b5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240946965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2240946965
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2157416008
Short name T135
Test name
Test status
Simulation time 489667363040 ps
CPU time 122.34 seconds
Started Feb 29 01:13:29 PM PST 24
Finished Feb 29 01:15:32 PM PST 24
Peak memory 201376 kb
Host smart-1f7ff6e8-814d-42c0-bc54-f2aa3478c56f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157416008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2157416008
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.4031164185
Short name T527
Test name
Test status
Simulation time 43463321603 ps
CPU time 90.92 seconds
Started Feb 29 01:13:33 PM PST 24
Finished Feb 29 01:15:04 PM PST 24
Peak memory 201176 kb
Host smart-1fa020ee-429e-4213-a47f-2b2e01fb92bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031164185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.4031164185
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3783143297
Short name T427
Test name
Test status
Simulation time 2703584730 ps
CPU time 2.57 seconds
Started Feb 29 01:13:32 PM PST 24
Finished Feb 29 01:13:35 PM PST 24
Peak memory 201208 kb
Host smart-7e0cea80-5f6e-4dce-b415-c086a9a3d72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783143297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3783143297
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2355174478
Short name T511
Test name
Test status
Simulation time 5869286410 ps
CPU time 12.94 seconds
Started Feb 29 01:13:26 PM PST 24
Finished Feb 29 01:13:39 PM PST 24
Peak memory 201152 kb
Host smart-c252c60c-1d52-4343-9959-634da9abbdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355174478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2355174478
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.4256085546
Short name T655
Test name
Test status
Simulation time 327448240723 ps
CPU time 199.89 seconds
Started Feb 29 01:13:30 PM PST 24
Finished Feb 29 01:16:50 PM PST 24
Peak memory 201396 kb
Host smart-ac8ae31a-3346-4b5d-902f-fb1aed3f0751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256085546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.4256085546
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2485402080
Short name T217
Test name
Test status
Simulation time 43061427438 ps
CPU time 45.09 seconds
Started Feb 29 01:13:29 PM PST 24
Finished Feb 29 01:14:14 PM PST 24
Peak memory 201568 kb
Host smart-320e78d6-5256-4adc-b1bf-1a040f9ee4ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485402080 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2485402080
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.156060372
Short name T657
Test name
Test status
Simulation time 421253883 ps
CPU time 1.46 seconds
Started Feb 29 01:13:37 PM PST 24
Finished Feb 29 01:13:39 PM PST 24
Peak memory 201144 kb
Host smart-b8d79533-fe51-4b28-b7d6-7842e25fcd65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156060372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.156060372
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.77478975
Short name T492
Test name
Test status
Simulation time 167244235204 ps
CPU time 124.45 seconds
Started Feb 29 01:13:37 PM PST 24
Finished Feb 29 01:15:42 PM PST 24
Peak memory 201504 kb
Host smart-c7b94bf7-a608-47b8-86e6-e06f6947545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77478975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.77478975
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3109179327
Short name T171
Test name
Test status
Simulation time 333526651416 ps
CPU time 260.53 seconds
Started Feb 29 01:13:33 PM PST 24
Finished Feb 29 01:17:54 PM PST 24
Peak memory 201392 kb
Host smart-3f969b66-77cf-4236-a3da-bba354507ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109179327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3109179327
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.553174808
Short name T754
Test name
Test status
Simulation time 167659168736 ps
CPU time 376.36 seconds
Started Feb 29 01:13:36 PM PST 24
Finished Feb 29 01:19:52 PM PST 24
Peak memory 201592 kb
Host smart-8396bd6e-748d-41c9-a4f3-553094b7cf93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=553174808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.553174808
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.515837033
Short name T316
Test name
Test status
Simulation time 160586193248 ps
CPU time 185.14 seconds
Started Feb 29 01:13:37 PM PST 24
Finished Feb 29 01:16:42 PM PST 24
Peak memory 201472 kb
Host smart-b633df78-1eb0-4cd4-a99d-ccce551bd137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515837033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.515837033
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1785554620
Short name T729
Test name
Test status
Simulation time 502348569606 ps
CPU time 177.79 seconds
Started Feb 29 01:13:38 PM PST 24
Finished Feb 29 01:16:36 PM PST 24
Peak memory 201408 kb
Host smart-04197e6e-4ca1-4b17-b144-703b398072f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785554620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1785554620
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.796944661
Short name T254
Test name
Test status
Simulation time 493160126927 ps
CPU time 311.11 seconds
Started Feb 29 01:13:34 PM PST 24
Finished Feb 29 01:18:46 PM PST 24
Peak memory 201332 kb
Host smart-5a9bc215-b842-4694-8fdc-65ca6ec0543f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796944661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.796944661
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3834901299
Short name T514
Test name
Test status
Simulation time 324443508514 ps
CPU time 709.1 seconds
Started Feb 29 01:13:31 PM PST 24
Finished Feb 29 01:25:21 PM PST 24
Peak memory 201336 kb
Host smart-4f9b5bec-48d5-4060-9d55-75162d6ef046
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834901299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3834901299
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1992509198
Short name T617
Test name
Test status
Simulation time 82000701510 ps
CPU time 319.92 seconds
Started Feb 29 01:13:36 PM PST 24
Finished Feb 29 01:18:56 PM PST 24
Peak memory 201996 kb
Host smart-1e08e153-ee7e-48f5-b4b9-31446a7fb4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992509198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1992509198
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2363423334
Short name T600
Test name
Test status
Simulation time 38596083550 ps
CPU time 43.33 seconds
Started Feb 29 01:13:41 PM PST 24
Finished Feb 29 01:14:25 PM PST 24
Peak memory 201204 kb
Host smart-1bfd6c37-9db0-4298-80ce-677f891e5ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363423334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2363423334
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.635529872
Short name T695
Test name
Test status
Simulation time 4042631098 ps
CPU time 2.96 seconds
Started Feb 29 01:13:49 PM PST 24
Finished Feb 29 01:13:53 PM PST 24
Peak memory 201220 kb
Host smart-1a0ab04a-53a0-4540-8288-83c279b98d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635529872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.635529872
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1310252181
Short name T3
Test name
Test status
Simulation time 5885135875 ps
CPU time 3.91 seconds
Started Feb 29 01:13:38 PM PST 24
Finished Feb 29 01:13:42 PM PST 24
Peak memory 201212 kb
Host smart-491c25fd-6cab-42cf-b080-880884f7effd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310252181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1310252181
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.714922371
Short name T559
Test name
Test status
Simulation time 178350245494 ps
CPU time 391.61 seconds
Started Feb 29 01:13:32 PM PST 24
Finished Feb 29 01:20:04 PM PST 24
Peak memory 201364 kb
Host smart-6f2301d5-448c-497f-81da-5d9d027a6c04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714922371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
714922371
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1409869626
Short name T75
Test name
Test status
Simulation time 104732641628 ps
CPU time 375.26 seconds
Started Feb 29 01:13:41 PM PST 24
Finished Feb 29 01:19:56 PM PST 24
Peak memory 217828 kb
Host smart-78b12a84-c43b-4d70-b2dc-c299a45f4009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409869626 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1409869626
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.746579366
Short name T780
Test name
Test status
Simulation time 419444856 ps
CPU time 1.03 seconds
Started Feb 29 01:13:36 PM PST 24
Finished Feb 29 01:13:37 PM PST 24
Peak memory 201128 kb
Host smart-63bce8e8-91e7-4f05-89d7-b575cfc9dfc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746579366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.746579366
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2726926650
Short name T523
Test name
Test status
Simulation time 511375148279 ps
CPU time 516.87 seconds
Started Feb 29 01:13:38 PM PST 24
Finished Feb 29 01:22:15 PM PST 24
Peak memory 201396 kb
Host smart-7733e63e-9474-4cd9-b717-bd4457997bb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726926650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2726926650
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1673494990
Short name T253
Test name
Test status
Simulation time 166481578221 ps
CPU time 357.46 seconds
Started Feb 29 01:13:34 PM PST 24
Finished Feb 29 01:19:31 PM PST 24
Peak memory 201500 kb
Host smart-c35b38f6-0039-4272-9b39-96d9eb073323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673494990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1673494990
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1034645866
Short name T705
Test name
Test status
Simulation time 167755769704 ps
CPU time 89.33 seconds
Started Feb 29 01:13:37 PM PST 24
Finished Feb 29 01:15:06 PM PST 24
Peak memory 201668 kb
Host smart-8e59ed79-a1f5-47c1-88a3-069b90617d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034645866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1034645866
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2560012662
Short name T596
Test name
Test status
Simulation time 158702091299 ps
CPU time 379.78 seconds
Started Feb 29 01:13:32 PM PST 24
Finished Feb 29 01:19:52 PM PST 24
Peak memory 201396 kb
Host smart-0c354400-328b-466f-8f64-b0a5cd291ab0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560012662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2560012662
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.717979885
Short name T203
Test name
Test status
Simulation time 479945038409 ps
CPU time 260.47 seconds
Started Feb 29 01:13:42 PM PST 24
Finished Feb 29 01:18:03 PM PST 24
Peak memory 201472 kb
Host smart-eb6ee08a-0548-47d1-9247-7f642f6f3cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717979885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.717979885
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1473558461
Short name T463
Test name
Test status
Simulation time 164397158523 ps
CPU time 351 seconds
Started Feb 29 01:13:42 PM PST 24
Finished Feb 29 01:19:33 PM PST 24
Peak memory 201404 kb
Host smart-ba3af51e-964a-41c4-9a3e-91866c7019cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473558461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1473558461
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.7668608
Short name T353
Test name
Test status
Simulation time 499478803588 ps
CPU time 302.38 seconds
Started Feb 29 01:13:49 PM PST 24
Finished Feb 29 01:18:52 PM PST 24
Peak memory 201412 kb
Host smart-eebc995d-1149-4f9c-8c7d-49a2559f508c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7668608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_wa
keup.7668608
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4178047307
Short name T725
Test name
Test status
Simulation time 163347950362 ps
CPU time 100.04 seconds
Started Feb 29 01:13:49 PM PST 24
Finished Feb 29 01:15:30 PM PST 24
Peak memory 201404 kb
Host smart-b97af5af-c849-4233-9ba8-0ac4163b52b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178047307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4178047307
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3343989117
Short name T556
Test name
Test status
Simulation time 81007311602 ps
CPU time 252.46 seconds
Started Feb 29 01:13:41 PM PST 24
Finished Feb 29 01:17:55 PM PST 24
Peak memory 201604 kb
Host smart-f3b8a4b6-36f7-4ce5-b470-1c88436ec10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343989117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3343989117
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1777112640
Short name T392
Test name
Test status
Simulation time 34746736041 ps
CPU time 22.59 seconds
Started Feb 29 01:13:32 PM PST 24
Finished Feb 29 01:13:55 PM PST 24
Peak memory 201188 kb
Host smart-d011e561-d028-4007-8282-b2cc31efb089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777112640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1777112640
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.301236538
Short name T577
Test name
Test status
Simulation time 2942051189 ps
CPU time 7.42 seconds
Started Feb 29 01:13:49 PM PST 24
Finished Feb 29 01:13:57 PM PST 24
Peak memory 201224 kb
Host smart-d92d4383-2c0d-4ba4-b63a-33769fc870c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301236538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.301236538
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3260146741
Short name T704
Test name
Test status
Simulation time 5810544775 ps
CPU time 4.26 seconds
Started Feb 29 01:13:49 PM PST 24
Finished Feb 29 01:13:54 PM PST 24
Peak memory 201168 kb
Host smart-b6253b89-c90a-4876-a283-29f1256fdd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260146741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3260146741
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1362121543
Short name T269
Test name
Test status
Simulation time 336355379528 ps
CPU time 666.9 seconds
Started Feb 29 01:13:41 PM PST 24
Finished Feb 29 01:24:49 PM PST 24
Peak memory 201292 kb
Host smart-7dd74f47-606b-42ad-be5a-a87464646eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362121543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1362121543
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.875995277
Short name T47
Test name
Test status
Simulation time 178608835293 ps
CPU time 113 seconds
Started Feb 29 01:13:32 PM PST 24
Finished Feb 29 01:15:25 PM PST 24
Peak memory 209976 kb
Host smart-2dfb30a9-04be-41d5-9f65-9de0dea6861c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875995277 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.875995277
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.806310126
Short name T525
Test name
Test status
Simulation time 484538134 ps
CPU time 0.9 seconds
Started Feb 29 01:13:47 PM PST 24
Finished Feb 29 01:13:49 PM PST 24
Peak memory 201036 kb
Host smart-09658add-f195-45ab-9e77-2d2b2182ee95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806310126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.806310126
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3407330530
Short name T209
Test name
Test status
Simulation time 488445689414 ps
CPU time 606.16 seconds
Started Feb 29 01:13:49 PM PST 24
Finished Feb 29 01:23:56 PM PST 24
Peak memory 201476 kb
Host smart-e07ca608-f41f-4ce9-98cb-21fe279cfbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407330530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3407330530
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1595345438
Short name T746
Test name
Test status
Simulation time 334433038347 ps
CPU time 400.77 seconds
Started Feb 29 01:13:36 PM PST 24
Finished Feb 29 01:20:17 PM PST 24
Peak memory 201440 kb
Host smart-c7922f88-845d-4bfc-b89c-d60ed8664fd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595345438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1595345438
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2204867315
Short name T62
Test name
Test status
Simulation time 166365744535 ps
CPU time 98.11 seconds
Started Feb 29 01:13:41 PM PST 24
Finished Feb 29 01:15:20 PM PST 24
Peak memory 201412 kb
Host smart-70a599c9-8205-4f42-8a44-6b2d90ca3b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204867315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2204867315
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1655321875
Short name T468
Test name
Test status
Simulation time 499903692765 ps
CPU time 140.41 seconds
Started Feb 29 01:13:48 PM PST 24
Finished Feb 29 01:16:09 PM PST 24
Peak memory 201468 kb
Host smart-0e88ba0d-6fdd-4ba0-ab43-04444b71a230
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655321875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1655321875
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3903462818
Short name T631
Test name
Test status
Simulation time 358391147526 ps
CPU time 437.26 seconds
Started Feb 29 01:13:34 PM PST 24
Finished Feb 29 01:20:51 PM PST 24
Peak memory 201504 kb
Host smart-c2aa5d40-366f-4cff-8418-8e1dfe82f7f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903462818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3903462818
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.512015053
Short name T397
Test name
Test status
Simulation time 490243454277 ps
CPU time 657.46 seconds
Started Feb 29 01:13:36 PM PST 24
Finished Feb 29 01:24:34 PM PST 24
Peak memory 201320 kb
Host smart-d020da58-3c07-4212-b1b4-7299004abba4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512015053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.512015053
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.3298840276
Short name T759
Test name
Test status
Simulation time 75080575450 ps
CPU time 299.71 seconds
Started Feb 29 01:13:44 PM PST 24
Finished Feb 29 01:18:44 PM PST 24
Peak memory 201736 kb
Host smart-38719e19-c9c5-4535-9670-296a8d5ce9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298840276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.3298840276
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1815154282
Short name T583
Test name
Test status
Simulation time 23531747111 ps
CPU time 25.02 seconds
Started Feb 29 01:13:51 PM PST 24
Finished Feb 29 01:14:17 PM PST 24
Peak memory 201076 kb
Host smart-64010e1f-52cf-4b62-9ea8-76cb57dc0fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815154282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1815154282
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1325685855
Short name T619
Test name
Test status
Simulation time 5001177899 ps
CPU time 11.79 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:13:58 PM PST 24
Peak memory 201196 kb
Host smart-0e957885-23f1-4e87-9dad-eebbba028c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325685855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1325685855
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2359714186
Short name T633
Test name
Test status
Simulation time 5811378802 ps
CPU time 3.69 seconds
Started Feb 29 01:13:37 PM PST 24
Finished Feb 29 01:13:41 PM PST 24
Peak memory 201352 kb
Host smart-6102862a-3e42-4555-a928-b4658cccbd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359714186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2359714186
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3897051649
Short name T601
Test name
Test status
Simulation time 170500581560 ps
CPU time 754.73 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:26:20 PM PST 24
Peak memory 211412 kb
Host smart-70cab22f-5c52-467b-aa40-bab25468e543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897051649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3897051649
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.1437544583
Short name T26
Test name
Test status
Simulation time 150797211316 ps
CPU time 202.06 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:17:07 PM PST 24
Peak memory 210088 kb
Host smart-3f9a0921-0ad7-4649-afda-61db5068d093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437544583 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.1437544583
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3724287026
Short name T691
Test name
Test status
Simulation time 541757628 ps
CPU time 0.93 seconds
Started Feb 29 01:13:47 PM PST 24
Finished Feb 29 01:13:48 PM PST 24
Peak memory 201108 kb
Host smart-6e902b2a-9157-49b5-a87f-fec89e33a14e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724287026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3724287026
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.738951607
Short name T350
Test name
Test status
Simulation time 328077747192 ps
CPU time 259.38 seconds
Started Feb 29 01:13:47 PM PST 24
Finished Feb 29 01:18:07 PM PST 24
Peak memory 201520 kb
Host smart-d4723d78-478d-4175-973e-dc0f8d88c9d3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738951607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.738951607
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3502858016
Short name T684
Test name
Test status
Simulation time 489157200615 ps
CPU time 792.05 seconds
Started Feb 29 01:13:47 PM PST 24
Finished Feb 29 01:27:00 PM PST 24
Peak memory 201360 kb
Host smart-c7a6ad2b-9b1d-4722-8540-3bcb061be65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502858016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3502858016
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3543038768
Short name T555
Test name
Test status
Simulation time 326236286984 ps
CPU time 775.68 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:26:41 PM PST 24
Peak memory 201380 kb
Host smart-cd249d74-9cd1-45e1-8f99-b9458d2761c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543038768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3543038768
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2420091486
Short name T712
Test name
Test status
Simulation time 486113927804 ps
CPU time 606.4 seconds
Started Feb 29 01:13:43 PM PST 24
Finished Feb 29 01:23:50 PM PST 24
Peak memory 201380 kb
Host smart-c5a3d1d7-cec9-43e4-b998-370698d0d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420091486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2420091486
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1083677188
Short name T396
Test name
Test status
Simulation time 487829150163 ps
CPU time 1220.31 seconds
Started Feb 29 01:13:47 PM PST 24
Finished Feb 29 01:34:08 PM PST 24
Peak memory 201512 kb
Host smart-3d401d06-9591-429d-af09-eb7902447a70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083677188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1083677188
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2057861750
Short name T490
Test name
Test status
Simulation time 170361973225 ps
CPU time 206.44 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:17:12 PM PST 24
Peak memory 201396 kb
Host smart-97578682-4c97-449b-8a24-98f3428a0dcc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057861750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2057861750
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.402381173
Short name T756
Test name
Test status
Simulation time 323467851673 ps
CPU time 190.52 seconds
Started Feb 29 01:13:46 PM PST 24
Finished Feb 29 01:16:57 PM PST 24
Peak memory 201396 kb
Host smart-63d32b10-90a4-474e-a1d4-ef20e96b4ab3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402381173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.402381173
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2839955859
Short name T664
Test name
Test status
Simulation time 87918958773 ps
CPU time 343.4 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:19:29 PM PST 24
Peak memory 201716 kb
Host smart-2b73d636-eb8e-4234-9077-968bf4d44959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839955859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2839955859
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.873634099
Short name T728
Test name
Test status
Simulation time 38044691749 ps
CPU time 46 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:14:32 PM PST 24
Peak memory 201208 kb
Host smart-8de66537-e4fe-416e-9db2-0884294239e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873634099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.873634099
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1801493859
Short name T465
Test name
Test status
Simulation time 4514748064 ps
CPU time 5.77 seconds
Started Feb 29 01:13:47 PM PST 24
Finished Feb 29 01:13:53 PM PST 24
Peak memory 201212 kb
Host smart-d63615d0-7b0d-4dad-9e61-31b6b68d6f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801493859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1801493859
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.233793769
Short name T408
Test name
Test status
Simulation time 6185986655 ps
CPU time 4.31 seconds
Started Feb 29 01:13:48 PM PST 24
Finished Feb 29 01:13:53 PM PST 24
Peak memory 201204 kb
Host smart-e2d02ece-9dc5-44e4-9e18-1880fdd87930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233793769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.233793769
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.402621795
Short name T581
Test name
Test status
Simulation time 175368244942 ps
CPU time 39.27 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:14:25 PM PST 24
Peak memory 201348 kb
Host smart-69c03a2a-696e-41c0-8129-31a3df697bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402621795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
402621795
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3281120129
Short name T484
Test name
Test status
Simulation time 386414686613 ps
CPU time 322.95 seconds
Started Feb 29 01:13:45 PM PST 24
Finished Feb 29 01:19:09 PM PST 24
Peak memory 210164 kb
Host smart-4d2bcfb1-4486-42ed-8908-5d1890b97e76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281120129 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3281120129
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2100844377
Short name T595
Test name
Test status
Simulation time 420393341 ps
CPU time 1.49 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:13:57 PM PST 24
Peak memory 201120 kb
Host smart-29aa5263-df7d-48ff-b33a-c91c8fd741a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100844377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2100844377
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.491326087
Short name T653
Test name
Test status
Simulation time 502458897272 ps
CPU time 1200.51 seconds
Started Feb 29 01:13:56 PM PST 24
Finished Feb 29 01:33:57 PM PST 24
Peak memory 201456 kb
Host smart-e14255a8-06df-4340-b3f6-9815290092f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491326087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.491326087
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3296813664
Short name T180
Test name
Test status
Simulation time 486544007990 ps
CPU time 278.03 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:18:33 PM PST 24
Peak memory 201448 kb
Host smart-18ccbf3d-a6ed-4d67-b713-aaaa9890a25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296813664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3296813664
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2625555602
Short name T462
Test name
Test status
Simulation time 491543983338 ps
CPU time 549.24 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:23:04 PM PST 24
Peak memory 201396 kb
Host smart-d4b4bc08-540e-4536-878f-b660551c173f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625555602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2625555602
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2245442354
Short name T310
Test name
Test status
Simulation time 487983057264 ps
CPU time 1105.06 seconds
Started Feb 29 01:13:49 PM PST 24
Finished Feb 29 01:32:15 PM PST 24
Peak memory 201408 kb
Host smart-6381e15c-d1ea-4463-8b22-1579dde7a908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245442354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2245442354
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.832694170
Short name T441
Test name
Test status
Simulation time 493474375091 ps
CPU time 334.09 seconds
Started Feb 29 01:13:50 PM PST 24
Finished Feb 29 01:19:25 PM PST 24
Peak memory 201268 kb
Host smart-f1dac551-ee35-4213-84c6-ea443cda50d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=832694170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.832694170
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3925995421
Short name T726
Test name
Test status
Simulation time 166102874322 ps
CPU time 359.9 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:19:56 PM PST 24
Peak memory 201396 kb
Host smart-30d4d0f5-ef94-45cd-b791-a2bf66ec1ced
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925995421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3925995421
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2182929981
Short name T738
Test name
Test status
Simulation time 328327421467 ps
CPU time 751.6 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:26:27 PM PST 24
Peak memory 201504 kb
Host smart-03ff4c05-8cdf-4254-9495-73ae7f4d6cc2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182929981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2182929981
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1624137166
Short name T365
Test name
Test status
Simulation time 96757834364 ps
CPU time 536.05 seconds
Started Feb 29 01:13:56 PM PST 24
Finished Feb 29 01:22:53 PM PST 24
Peak memory 201724 kb
Host smart-61679af4-afbb-4b2e-a4c1-b8a92c38a365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624137166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1624137166
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.132388600
Short name T77
Test name
Test status
Simulation time 22710363480 ps
CPU time 10.03 seconds
Started Feb 29 01:13:54 PM PST 24
Finished Feb 29 01:14:04 PM PST 24
Peak memory 201160 kb
Host smart-39784eee-dbb4-4801-bc05-2ed5fcd41e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132388600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.132388600
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1354422269
Short name T751
Test name
Test status
Simulation time 4004540355 ps
CPU time 3.11 seconds
Started Feb 29 01:13:54 PM PST 24
Finished Feb 29 01:13:58 PM PST 24
Peak memory 201196 kb
Host smart-f8de8468-e068-4879-99b4-a6e1d3a2a555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354422269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1354422269
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3293205316
Short name T544
Test name
Test status
Simulation time 5991860090 ps
CPU time 13.93 seconds
Started Feb 29 01:13:46 PM PST 24
Finished Feb 29 01:14:00 PM PST 24
Peak memory 201248 kb
Host smart-b32b973c-ac1b-4cc2-95e2-179db6b39a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293205316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3293205316
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2356097664
Short name T48
Test name
Test status
Simulation time 207386740893 ps
CPU time 238.13 seconds
Started Feb 29 01:14:02 PM PST 24
Finished Feb 29 01:18:01 PM PST 24
Peak memory 201408 kb
Host smart-d15d2b4e-6c78-42ba-83d5-d61d5e0a4a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356097664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2356097664
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2699987171
Short name T46
Test name
Test status
Simulation time 330059710608 ps
CPU time 774.98 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:26:50 PM PST 24
Peak memory 201412 kb
Host smart-7a016595-226d-4531-8816-320a3dbb937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699987171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2699987171
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3863127164
Short name T503
Test name
Test status
Simulation time 495435949154 ps
CPU time 99.09 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:15:34 PM PST 24
Peak memory 201444 kb
Host smart-ab3e9709-e846-4d15-8b22-54c73dad9ce6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863127164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3863127164
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1423971285
Short name T162
Test name
Test status
Simulation time 329246656967 ps
CPU time 209.38 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:17:25 PM PST 24
Peak memory 201476 kb
Host smart-b92f427b-9bf3-4840-b938-e36abf038040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423971285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1423971285
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1491657037
Short name T80
Test name
Test status
Simulation time 327017375089 ps
CPU time 180.64 seconds
Started Feb 29 01:13:56 PM PST 24
Finished Feb 29 01:16:57 PM PST 24
Peak memory 201456 kb
Host smart-a1f91acc-7cd3-4112-9fc5-2ad377f2055d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491657037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1491657037
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1736129615
Short name T767
Test name
Test status
Simulation time 366360077378 ps
CPU time 823.13 seconds
Started Feb 29 01:13:57 PM PST 24
Finished Feb 29 01:27:41 PM PST 24
Peak memory 201380 kb
Host smart-21e3045f-76d8-438f-9dd5-3767bf01a41f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736129615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1736129615
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2736031369
Short name T536
Test name
Test status
Simulation time 164828178862 ps
CPU time 91.17 seconds
Started Feb 29 01:13:57 PM PST 24
Finished Feb 29 01:15:28 PM PST 24
Peak memory 201288 kb
Host smart-f7639504-fb7d-4073-b33a-87c74a78e20a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736031369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2736031369
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3682266584
Short name T432
Test name
Test status
Simulation time 97750917369 ps
CPU time 372.19 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:20:08 PM PST 24
Peak memory 201772 kb
Host smart-f6032f6a-4510-40f8-9e26-5ffca8109f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682266584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3682266584
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.1279303696
Short name T592
Test name
Test status
Simulation time 32010273901 ps
CPU time 77.2 seconds
Started Feb 29 01:13:57 PM PST 24
Finished Feb 29 01:15:14 PM PST 24
Peak memory 201188 kb
Host smart-cceb58d5-771c-49d4-8845-54fbcc0ed158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279303696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.1279303696
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.153597142
Short name T670
Test name
Test status
Simulation time 4283857158 ps
CPU time 9.99 seconds
Started Feb 29 01:13:57 PM PST 24
Finished Feb 29 01:14:07 PM PST 24
Peak memory 201100 kb
Host smart-7a98ada5-a4fe-4984-98d6-b69cb6cd2854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153597142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.153597142
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3809604732
Short name T418
Test name
Test status
Simulation time 6114761684 ps
CPU time 5.56 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:14:01 PM PST 24
Peak memory 201200 kb
Host smart-eeea3ae2-f69a-4f0c-b192-e0296313bca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809604732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3809604732
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3247470406
Short name T175
Test name
Test status
Simulation time 191032316195 ps
CPU time 374.59 seconds
Started Feb 29 01:13:56 PM PST 24
Finished Feb 29 01:20:11 PM PST 24
Peak memory 201460 kb
Host smart-19c497f8-ee2c-48d7-be90-a75748dbd19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247470406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3247470406
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2146806142
Short name T302
Test name
Test status
Simulation time 256830302277 ps
CPU time 196.79 seconds
Started Feb 29 01:13:57 PM PST 24
Finished Feb 29 01:17:15 PM PST 24
Peak memory 210036 kb
Host smart-c8c63eeb-ed53-42bd-9535-f9382f0c26fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146806142 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2146806142
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4161954061
Short name T413
Test name
Test status
Simulation time 463370039 ps
CPU time 0.86 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:14:11 PM PST 24
Peak memory 201136 kb
Host smart-730697fa-fcb7-40b8-8132-6e14b2b173c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161954061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4161954061
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3098784901
Short name T243
Test name
Test status
Simulation time 165655205540 ps
CPU time 99.73 seconds
Started Feb 29 01:13:59 PM PST 24
Finished Feb 29 01:15:39 PM PST 24
Peak memory 201444 kb
Host smart-3b002227-615d-44e6-a957-f2d2ef272979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098784901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3098784901
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2980064427
Short name T189
Test name
Test status
Simulation time 164751281187 ps
CPU time 354.33 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:19:50 PM PST 24
Peak memory 201464 kb
Host smart-6b6d8d80-7f29-4d0c-b883-a5bc6c9c226d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980064427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2980064427
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.347282337
Short name T410
Test name
Test status
Simulation time 494946147751 ps
CPU time 312.74 seconds
Started Feb 29 01:13:57 PM PST 24
Finished Feb 29 01:19:10 PM PST 24
Peak memory 201280 kb
Host smart-047c6c59-fe25-4eb9-ad24-88674f26a8c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=347282337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.347282337
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2715270035
Short name T477
Test name
Test status
Simulation time 326670463624 ps
CPU time 575.15 seconds
Started Feb 29 01:13:55 PM PST 24
Finished Feb 29 01:23:30 PM PST 24
Peak memory 201356 kb
Host smart-812cfcf0-7609-4efc-a42e-00da3ce27bc3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715270035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2715270035
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1384453610
Short name T656
Test name
Test status
Simulation time 90989482936 ps
CPU time 355.72 seconds
Started Feb 29 01:14:09 PM PST 24
Finished Feb 29 01:20:05 PM PST 24
Peak memory 201780 kb
Host smart-46f49767-55f3-4ee5-9965-4acfa17ca865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384453610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1384453610
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2977029876
Short name T50
Test name
Test status
Simulation time 41423993472 ps
CPU time 12.26 seconds
Started Feb 29 01:14:09 PM PST 24
Finished Feb 29 01:14:21 PM PST 24
Peak memory 201156 kb
Host smart-9a519159-1d5e-4282-8a0c-af1433813d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977029876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2977029876
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.685055158
Short name T83
Test name
Test status
Simulation time 4492651750 ps
CPU time 10.59 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:14:21 PM PST 24
Peak memory 201200 kb
Host smart-1c47b503-8c0e-4bb0-a389-c17059544d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685055158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.685055158
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.949875596
Short name T188
Test name
Test status
Simulation time 5631510516 ps
CPU time 14.09 seconds
Started Feb 29 01:13:54 PM PST 24
Finished Feb 29 01:14:08 PM PST 24
Peak memory 201136 kb
Host smart-df9f939f-5d84-40f1-85df-69018bbea916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949875596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.949875596
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1527293978
Short name T772
Test name
Test status
Simulation time 401523344560 ps
CPU time 671.49 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:25:22 PM PST 24
Peak memory 210020 kb
Host smart-21f820b3-da44-4fb7-b1c8-c68e29e04bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527293978 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1527293978
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2748117167
Short name T407
Test name
Test status
Simulation time 554651312 ps
CPU time 0.9 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:12:29 PM PST 24
Peak memory 201144 kb
Host smart-31d3eb6f-50ca-4680-951f-13a71110d8e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748117167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2748117167
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.4056691880
Short name T182
Test name
Test status
Simulation time 490718978007 ps
CPU time 115.51 seconds
Started Feb 29 01:12:27 PM PST 24
Finished Feb 29 01:14:23 PM PST 24
Peak memory 201388 kb
Host smart-4898eb30-235c-4128-b760-f0ae40c01b54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056691880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.4056691880
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.609681636
Short name T252
Test name
Test status
Simulation time 162729334963 ps
CPU time 203.81 seconds
Started Feb 29 01:12:31 PM PST 24
Finished Feb 29 01:15:55 PM PST 24
Peak memory 201432 kb
Host smart-eda56560-de5f-4b9d-954d-27f5c981fefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609681636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.609681636
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3859861712
Short name T765
Test name
Test status
Simulation time 481680792370 ps
CPU time 1057.7 seconds
Started Feb 29 01:12:29 PM PST 24
Finished Feb 29 01:30:07 PM PST 24
Peak memory 201560 kb
Host smart-549a47d3-47ea-4b3d-b300-a06fdb0df1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859861712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3859861712
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3117232716
Short name T521
Test name
Test status
Simulation time 331260714042 ps
CPU time 772.97 seconds
Started Feb 29 01:12:26 PM PST 24
Finished Feb 29 01:25:19 PM PST 24
Peak memory 201368 kb
Host smart-e1b52543-eedf-4996-b94a-288d97a97f66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117232716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3117232716
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.2168153693
Short name T681
Test name
Test status
Simulation time 490710006275 ps
CPU time 283.43 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:17:11 PM PST 24
Peak memory 201236 kb
Host smart-5420fdc9-1cc3-4110-8aa6-7594265a730d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168153693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.2168153693
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3736338631
Short name T458
Test name
Test status
Simulation time 498678131741 ps
CPU time 211.18 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:16:00 PM PST 24
Peak memory 201460 kb
Host smart-a7ef2be2-f80e-48c1-840a-7590a626e246
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736338631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3736338631
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3373989729
Short name T429
Test name
Test status
Simulation time 102947342214 ps
CPU time 390.32 seconds
Started Feb 29 01:12:25 PM PST 24
Finished Feb 29 01:18:56 PM PST 24
Peak memory 201748 kb
Host smart-4f0e2ecd-7e83-4e2a-8904-6d516d70b805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373989729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3373989729
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1379198877
Short name T374
Test name
Test status
Simulation time 31063703118 ps
CPU time 19.44 seconds
Started Feb 29 01:12:31 PM PST 24
Finished Feb 29 01:12:50 PM PST 24
Peak memory 201404 kb
Host smart-bf35e165-a234-440c-ab38-a72a8f7fff1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379198877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1379198877
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.4084366420
Short name T476
Test name
Test status
Simulation time 3537827051 ps
CPU time 2.39 seconds
Started Feb 29 01:12:31 PM PST 24
Finished Feb 29 01:12:34 PM PST 24
Peak memory 201400 kb
Host smart-9832e6c4-e9a0-493f-8d5a-a5b09032cd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084366420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.4084366420
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.881799873
Short name T43
Test name
Test status
Simulation time 7742299949 ps
CPU time 18.77 seconds
Started Feb 29 01:12:27 PM PST 24
Finished Feb 29 01:12:46 PM PST 24
Peak memory 217320 kb
Host smart-f2702099-3b35-46f8-b0a3-8dd89e06ac9a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881799873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.881799873
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2234480432
Short name T671
Test name
Test status
Simulation time 5835544310 ps
CPU time 14.28 seconds
Started Feb 29 01:12:25 PM PST 24
Finished Feb 29 01:12:39 PM PST 24
Peak memory 201152 kb
Host smart-9dc92197-8487-483e-bb96-bd4f6b1ded83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234480432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2234480432
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1944400536
Short name T326
Test name
Test status
Simulation time 181799578578 ps
CPU time 103.44 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:14:12 PM PST 24
Peak memory 201388 kb
Host smart-286e65fd-9068-4fcf-ba9a-6447102d4325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944400536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1944400536
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3682341756
Short name T213
Test name
Test status
Simulation time 72158061532 ps
CPU time 57.42 seconds
Started Feb 29 01:12:31 PM PST 24
Finished Feb 29 01:13:29 PM PST 24
Peak memory 210040 kb
Host smart-f6ffa249-55e6-4d46-86e3-4d900eae37d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682341756 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3682341756
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2792389452
Short name T504
Test name
Test status
Simulation time 451064820 ps
CPU time 0.86 seconds
Started Feb 29 01:14:09 PM PST 24
Finished Feb 29 01:14:10 PM PST 24
Peak memory 201136 kb
Host smart-91076208-04e8-422f-ba18-7ac91c44d365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792389452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2792389452
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3529056531
Short name T183
Test name
Test status
Simulation time 483985259249 ps
CPU time 199.24 seconds
Started Feb 29 01:14:12 PM PST 24
Finished Feb 29 01:17:31 PM PST 24
Peak memory 201264 kb
Host smart-ad5a37d6-f4f0-4bc3-a6ad-48a389df2739
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529056531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3529056531
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2031854933
Short name T430
Test name
Test status
Simulation time 165050718810 ps
CPU time 49.92 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:15:00 PM PST 24
Peak memory 201444 kb
Host smart-517efcc8-be87-4930-adce-e3d89e3ca0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031854933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2031854933
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1156607363
Short name T620
Test name
Test status
Simulation time 496831419730 ps
CPU time 280.03 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:18:50 PM PST 24
Peak memory 201348 kb
Host smart-46dcf9d8-4d2e-47cc-810d-89dcb2dc21cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156607363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1156607363
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2843101005
Short name T424
Test name
Test status
Simulation time 163348810761 ps
CPU time 41.09 seconds
Started Feb 29 01:14:11 PM PST 24
Finished Feb 29 01:14:52 PM PST 24
Peak memory 201248 kb
Host smart-8320ac73-7a9c-4389-a0eb-b6773d3fbbdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843101005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2843101005
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2681475375
Short name T264
Test name
Test status
Simulation time 493494461126 ps
CPU time 1036.13 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:31:27 PM PST 24
Peak memory 201392 kb
Host smart-6da7df6c-7b51-4460-90b1-d17c45bb0ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681475375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2681475375
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1746278507
Short name T672
Test name
Test status
Simulation time 329049974302 ps
CPU time 724.36 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:26:15 PM PST 24
Peak memory 201576 kb
Host smart-61786612-fc9f-4e7f-8d98-4945d72dc9c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746278507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1746278507
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1374993097
Short name T528
Test name
Test status
Simulation time 330176267386 ps
CPU time 643.33 seconds
Started Feb 29 01:14:12 PM PST 24
Finished Feb 29 01:24:56 PM PST 24
Peak memory 201372 kb
Host smart-352383b4-a305-472d-a587-d78398c6dbab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374993097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1374993097
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2881372038
Short name T226
Test name
Test status
Simulation time 120085070395 ps
CPU time 694.37 seconds
Started Feb 29 01:14:11 PM PST 24
Finished Feb 29 01:25:46 PM PST 24
Peak memory 201912 kb
Host smart-19fd9434-10be-40c3-9e74-4408e3dfdd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881372038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2881372038
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1896717482
Short name T391
Test name
Test status
Simulation time 37857880687 ps
CPU time 22.09 seconds
Started Feb 29 01:14:11 PM PST 24
Finished Feb 29 01:14:33 PM PST 24
Peak memory 201192 kb
Host smart-d3921096-8af6-4aa2-8057-00755f5c2abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896717482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1896717482
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.646483657
Short name T635
Test name
Test status
Simulation time 3262450876 ps
CPU time 2.36 seconds
Started Feb 29 01:14:11 PM PST 24
Finished Feb 29 01:14:14 PM PST 24
Peak memory 201396 kb
Host smart-40d54c98-62ec-43e5-8904-b2743b438e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646483657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.646483657
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2941377398
Short name T483
Test name
Test status
Simulation time 5871019829 ps
CPU time 4.43 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:14:14 PM PST 24
Peak memory 201132 kb
Host smart-01393375-c38b-4c1a-85da-609f6b83dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941377398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2941377398
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3144693999
Short name T268
Test name
Test status
Simulation time 363582569046 ps
CPU time 841.71 seconds
Started Feb 29 01:14:09 PM PST 24
Finished Feb 29 01:28:11 PM PST 24
Peak memory 201356 kb
Host smart-b6627406-5f37-4493-a641-50ba874d33bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144693999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3144693999
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.4224077983
Short name T495
Test name
Test status
Simulation time 20669540678 ps
CPU time 52.32 seconds
Started Feb 29 01:14:08 PM PST 24
Finished Feb 29 01:15:01 PM PST 24
Peak memory 210032 kb
Host smart-c3f99374-5e51-4879-b96e-65730c78f6c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224077983 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.4224077983
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2412999918
Short name T406
Test name
Test status
Simulation time 458116514 ps
CPU time 1.67 seconds
Started Feb 29 01:14:23 PM PST 24
Finished Feb 29 01:14:25 PM PST 24
Peak memory 201180 kb
Host smart-2ec984f2-7f89-4329-a4a7-895bf4850127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412999918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2412999918
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1430351463
Short name T359
Test name
Test status
Simulation time 493934321957 ps
CPU time 1154.94 seconds
Started Feb 29 01:14:21 PM PST 24
Finished Feb 29 01:33:36 PM PST 24
Peak memory 201516 kb
Host smart-47d5261a-adad-4c66-aeed-fa9ae2f4fc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430351463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1430351463
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2638472256
Short name T199
Test name
Test status
Simulation time 162215496123 ps
CPU time 326.83 seconds
Started Feb 29 01:14:10 PM PST 24
Finished Feb 29 01:19:37 PM PST 24
Peak memory 201452 kb
Host smart-b1f3a083-ea09-4b45-9f68-78ab7a96c4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638472256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2638472256
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2097658828
Short name T641
Test name
Test status
Simulation time 331675494077 ps
CPU time 209.23 seconds
Started Feb 29 01:14:13 PM PST 24
Finished Feb 29 01:17:43 PM PST 24
Peak memory 201408 kb
Host smart-b59b5c7f-ee0d-412c-aea4-640a99ff63e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097658828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2097658828
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1272322395
Short name T231
Test name
Test status
Simulation time 161998186411 ps
CPU time 350.61 seconds
Started Feb 29 01:14:09 PM PST 24
Finished Feb 29 01:20:00 PM PST 24
Peak memory 201404 kb
Host smart-05ac1035-a2de-4522-8a20-81f8e7f391a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272322395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1272322395
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3453643024
Short name T579
Test name
Test status
Simulation time 318067000203 ps
CPU time 171.09 seconds
Started Feb 29 01:14:13 PM PST 24
Finished Feb 29 01:17:04 PM PST 24
Peak memory 201340 kb
Host smart-a66c5176-5513-4f2b-b97d-ab9fd85c47fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453643024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3453643024
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1158799380
Short name T502
Test name
Test status
Simulation time 161315835488 ps
CPU time 100.19 seconds
Started Feb 29 01:14:09 PM PST 24
Finished Feb 29 01:15:50 PM PST 24
Peak memory 201460 kb
Host smart-4419bbb4-50e9-43d2-9338-d893ddaf3d38
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158799380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1158799380
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1777970471
Short name T224
Test name
Test status
Simulation time 102906064296 ps
CPU time 399.56 seconds
Started Feb 29 01:14:20 PM PST 24
Finished Feb 29 01:21:00 PM PST 24
Peak memory 201708 kb
Host smart-a26f76b6-8da0-4ff0-8f85-10b361d37b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777970471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1777970471
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.677785061
Short name T207
Test name
Test status
Simulation time 24615392364 ps
CPU time 29.52 seconds
Started Feb 29 01:14:26 PM PST 24
Finished Feb 29 01:14:55 PM PST 24
Peak memory 201160 kb
Host smart-9e91e574-9b94-4396-84ff-759a00ba04f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677785061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.677785061
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.424743831
Short name T431
Test name
Test status
Simulation time 4657717220 ps
CPU time 11.54 seconds
Started Feb 29 01:14:20 PM PST 24
Finished Feb 29 01:14:32 PM PST 24
Peak memory 201096 kb
Host smart-74f3505b-febb-44ad-a8eb-ed5cd1a66272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424743831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.424743831
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3283028358
Short name T61
Test name
Test status
Simulation time 5727590837 ps
CPU time 13.72 seconds
Started Feb 29 01:14:12 PM PST 24
Finished Feb 29 01:14:26 PM PST 24
Peak memory 201136 kb
Host smart-6fa532dd-f173-4860-ac8e-7bf88302409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283028358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3283028358
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1118835134
Short name T770
Test name
Test status
Simulation time 172419001266 ps
CPU time 375.28 seconds
Started Feb 29 01:14:28 PM PST 24
Finished Feb 29 01:20:43 PM PST 24
Peak memory 201452 kb
Host smart-da2ae2da-d652-49bf-ae79-24e15d913849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118835134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1118835134
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1996246940
Short name T288
Test name
Test status
Simulation time 193601880265 ps
CPU time 94.67 seconds
Started Feb 29 01:14:22 PM PST 24
Finished Feb 29 01:15:57 PM PST 24
Peak memory 210072 kb
Host smart-5afbfca5-6a0d-4d74-ae1d-54912ea80b94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996246940 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1996246940
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2902754828
Short name T469
Test name
Test status
Simulation time 356344228 ps
CPU time 0.65 seconds
Started Feb 29 01:14:25 PM PST 24
Finished Feb 29 01:14:26 PM PST 24
Peak memory 201332 kb
Host smart-30a6a02c-e843-4d7a-b54b-f9907525764c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902754828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2902754828
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4089606573
Short name T230
Test name
Test status
Simulation time 497980424442 ps
CPU time 1067.46 seconds
Started Feb 29 01:14:20 PM PST 24
Finished Feb 29 01:32:08 PM PST 24
Peak memory 201324 kb
Host smart-cdae0314-3daf-4dde-ba0c-dcc8f26b2973
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089606573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4089606573
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.476567618
Short name T160
Test name
Test status
Simulation time 494980726130 ps
CPU time 1145.36 seconds
Started Feb 29 01:14:20 PM PST 24
Finished Feb 29 01:33:26 PM PST 24
Peak memory 201560 kb
Host smart-ee420dcc-1ba5-4650-a9e3-191f42a921c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476567618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.476567618
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.4060529215
Short name T147
Test name
Test status
Simulation time 169103429162 ps
CPU time 174.62 seconds
Started Feb 29 01:14:21 PM PST 24
Finished Feb 29 01:17:16 PM PST 24
Peak memory 201516 kb
Host smart-056ee3a9-2eac-4f7e-bc8c-174440801523
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060529215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.4060529215
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2859574168
Short name T303
Test name
Test status
Simulation time 492920309512 ps
CPU time 286.38 seconds
Started Feb 29 01:14:23 PM PST 24
Finished Feb 29 01:19:10 PM PST 24
Peak memory 201668 kb
Host smart-1401904c-fd25-4903-9684-cfb08e16138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859574168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2859574168
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1293989893
Short name T444
Test name
Test status
Simulation time 162075239522 ps
CPU time 85.71 seconds
Started Feb 29 01:14:24 PM PST 24
Finished Feb 29 01:15:49 PM PST 24
Peak memory 201396 kb
Host smart-620b25a0-f815-4573-b20e-6f0927a97d64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293989893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1293989893
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.402573989
Short name T335
Test name
Test status
Simulation time 165491688344 ps
CPU time 381.81 seconds
Started Feb 29 01:14:36 PM PST 24
Finished Feb 29 01:20:58 PM PST 24
Peak memory 201396 kb
Host smart-997f350b-69da-4bab-8b48-44c99320ab12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402573989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.402573989
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.276476556
Short name T569
Test name
Test status
Simulation time 322367415294 ps
CPU time 178.08 seconds
Started Feb 29 01:14:23 PM PST 24
Finished Feb 29 01:17:21 PM PST 24
Peak memory 201460 kb
Host smart-ec98b1bd-ddb3-4e75-a4ac-7373d9bf590b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276476556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.276476556
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3194476569
Short name T25
Test name
Test status
Simulation time 80214675229 ps
CPU time 333.3 seconds
Started Feb 29 01:14:24 PM PST 24
Finished Feb 29 01:19:58 PM PST 24
Peak memory 201712 kb
Host smart-944e3273-f6a5-4248-adbe-986f42e000f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194476569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3194476569
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4285902950
Short name T519
Test name
Test status
Simulation time 42045858199 ps
CPU time 92.9 seconds
Started Feb 29 01:14:25 PM PST 24
Finished Feb 29 01:15:58 PM PST 24
Peak memory 201192 kb
Host smart-8b716b20-bf9c-4aa5-afea-08e1ecf258b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285902950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4285902950
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2411341034
Short name T626
Test name
Test status
Simulation time 5199342801 ps
CPU time 11.89 seconds
Started Feb 29 01:14:21 PM PST 24
Finished Feb 29 01:14:33 PM PST 24
Peak memory 201204 kb
Host smart-aa76d4a4-73cc-4da4-a71b-4da7637dfc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411341034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2411341034
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3126644264
Short name T769
Test name
Test status
Simulation time 5616333542 ps
CPU time 2.01 seconds
Started Feb 29 01:14:21 PM PST 24
Finished Feb 29 01:14:23 PM PST 24
Peak memory 201128 kb
Host smart-feab2668-2780-418e-8e0a-21de32b1d647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126644264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3126644264
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1073311407
Short name T561
Test name
Test status
Simulation time 33345649143 ps
CPU time 72.17 seconds
Started Feb 29 01:14:28 PM PST 24
Finished Feb 29 01:15:40 PM PST 24
Peak memory 210020 kb
Host smart-1d676e0c-2911-47e4-a1a5-4fd29fca688c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073311407 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1073311407
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.640369788
Short name T394
Test name
Test status
Simulation time 523922902 ps
CPU time 1.82 seconds
Started Feb 29 01:14:37 PM PST 24
Finished Feb 29 01:14:39 PM PST 24
Peak memory 201156 kb
Host smart-de215f7e-d89b-4115-93c0-9c70ec4d613b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640369788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.640369788
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3278379521
Short name T245
Test name
Test status
Simulation time 163236665172 ps
CPU time 58.97 seconds
Started Feb 29 01:14:21 PM PST 24
Finished Feb 29 01:15:20 PM PST 24
Peak memory 201476 kb
Host smart-1b6fecd6-2e5a-4558-a096-81eab4427174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278379521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3278379521
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.280426606
Short name T150
Test name
Test status
Simulation time 161964613969 ps
CPU time 101.04 seconds
Started Feb 29 01:14:21 PM PST 24
Finished Feb 29 01:16:02 PM PST 24
Peak memory 201628 kb
Host smart-7ef2b053-93d3-488c-bac6-34a690595e61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=280426606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.280426606
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1876050331
Short name T460
Test name
Test status
Simulation time 487560643427 ps
CPU time 1032.16 seconds
Started Feb 29 01:14:23 PM PST 24
Finished Feb 29 01:31:35 PM PST 24
Peak memory 201604 kb
Host smart-1c1b5133-45b6-44e3-b467-61295c1e53e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876050331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1876050331
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1692803326
Short name T197
Test name
Test status
Simulation time 489480725199 ps
CPU time 1053 seconds
Started Feb 29 01:14:21 PM PST 24
Finished Feb 29 01:31:54 PM PST 24
Peak memory 201376 kb
Host smart-bd263c9f-25da-4e31-87de-5a9637cb9863
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692803326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1692803326
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1044125170
Short name T156
Test name
Test status
Simulation time 497814079715 ps
CPU time 122.96 seconds
Started Feb 29 01:14:23 PM PST 24
Finished Feb 29 01:16:26 PM PST 24
Peak memory 201472 kb
Host smart-5d67a5c6-151b-4c94-9132-cc1c3439c36f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044125170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1044125170
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1101999826
Short name T685
Test name
Test status
Simulation time 160620685016 ps
CPU time 376.78 seconds
Started Feb 29 01:14:20 PM PST 24
Finished Feb 29 01:20:36 PM PST 24
Peak memory 201468 kb
Host smart-844e3f5a-075f-4507-a74e-6915601a31d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101999826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1101999826
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1315961202
Short name T679
Test name
Test status
Simulation time 120823125734 ps
CPU time 400.91 seconds
Started Feb 29 01:14:37 PM PST 24
Finished Feb 29 01:21:19 PM PST 24
Peak memory 201764 kb
Host smart-79f21b00-6ec6-40b2-9f23-d51069b65e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315961202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1315961202
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.102151660
Short name T445
Test name
Test status
Simulation time 34434239530 ps
CPU time 41.32 seconds
Started Feb 29 01:14:33 PM PST 24
Finished Feb 29 01:15:15 PM PST 24
Peak memory 201192 kb
Host smart-1e2cf05a-c9c7-400f-8c6e-9c1c3f8b0caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102151660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.102151660
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1059921457
Short name T779
Test name
Test status
Simulation time 4459977239 ps
CPU time 10.82 seconds
Started Feb 29 01:14:23 PM PST 24
Finished Feb 29 01:14:34 PM PST 24
Peak memory 201232 kb
Host smart-9b9f3a77-5d31-4292-97e1-766f3e439134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059921457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1059921457
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1883839714
Short name T376
Test name
Test status
Simulation time 5686609027 ps
CPU time 4.55 seconds
Started Feb 29 01:14:28 PM PST 24
Finished Feb 29 01:14:33 PM PST 24
Peak memory 201096 kb
Host smart-efb22033-945f-4707-8f7d-b188d7de978d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883839714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1883839714
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.507127243
Short name T526
Test name
Test status
Simulation time 172835355164 ps
CPU time 320.47 seconds
Started Feb 29 01:14:37 PM PST 24
Finished Feb 29 01:19:58 PM PST 24
Peak memory 201412 kb
Host smart-fa1da538-d6cd-48bf-b883-bd3bccfc0246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507127243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
507127243
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.614576045
Short name T673
Test name
Test status
Simulation time 445660907 ps
CPU time 0.86 seconds
Started Feb 29 01:14:47 PM PST 24
Finished Feb 29 01:14:48 PM PST 24
Peak memory 201192 kb
Host smart-a2d5d9e4-1f94-44cb-b998-75dd3fdd7170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614576045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.614576045
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1180359335
Short name T333
Test name
Test status
Simulation time 499595697871 ps
CPU time 680.7 seconds
Started Feb 29 01:14:33 PM PST 24
Finished Feb 29 01:25:53 PM PST 24
Peak memory 201548 kb
Host smart-f979e96c-2491-45a7-86df-0a4f845e0b77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180359335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1180359335
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2817559164
Short name T485
Test name
Test status
Simulation time 165716540921 ps
CPU time 197.76 seconds
Started Feb 29 01:14:32 PM PST 24
Finished Feb 29 01:17:50 PM PST 24
Peak memory 201440 kb
Host smart-ffd0ce3c-d2c7-4177-bc7d-28697064018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817559164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2817559164
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2546165996
Short name T541
Test name
Test status
Simulation time 164877813778 ps
CPU time 386.12 seconds
Started Feb 29 01:14:33 PM PST 24
Finished Feb 29 01:20:59 PM PST 24
Peak memory 201460 kb
Host smart-0d709408-0e43-4778-8fde-32fb811918ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546165996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2546165996
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.735086662
Short name T632
Test name
Test status
Simulation time 167980960719 ps
CPU time 201.06 seconds
Started Feb 29 01:14:34 PM PST 24
Finished Feb 29 01:17:55 PM PST 24
Peak memory 201304 kb
Host smart-a6dec9e5-cc5b-4932-afac-ce877b0a1ea3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=735086662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.735086662
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.332102233
Short name T282
Test name
Test status
Simulation time 165416681793 ps
CPU time 362.48 seconds
Started Feb 29 01:14:31 PM PST 24
Finished Feb 29 01:20:34 PM PST 24
Peak memory 201404 kb
Host smart-168cbefb-023d-489f-bfc1-4d6a8f597133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332102233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.332102233
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3405284054
Short name T86
Test name
Test status
Simulation time 327609949990 ps
CPU time 726.23 seconds
Started Feb 29 01:14:34 PM PST 24
Finished Feb 29 01:26:40 PM PST 24
Peak memory 201368 kb
Host smart-6358ed8b-4a7c-4e66-9737-be922c5c1057
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405284054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3405284054
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2051552529
Short name T299
Test name
Test status
Simulation time 496725382202 ps
CPU time 287.05 seconds
Started Feb 29 01:14:33 PM PST 24
Finished Feb 29 01:19:20 PM PST 24
Peak memory 201376 kb
Host smart-ee107782-baee-4999-858c-85828c1ae908
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051552529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2051552529
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.51070508
Short name T750
Test name
Test status
Simulation time 342632880897 ps
CPU time 798.3 seconds
Started Feb 29 01:14:37 PM PST 24
Finished Feb 29 01:27:56 PM PST 24
Peak memory 201408 kb
Host smart-55aa7e5e-1e52-48d0-890d-9a1852807a9b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51070508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.a
dc_ctrl_filters_wakeup_fixed.51070508
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1306858211
Short name T23
Test name
Test status
Simulation time 127872015506 ps
CPU time 676.17 seconds
Started Feb 29 01:14:48 PM PST 24
Finished Feb 29 01:26:05 PM PST 24
Peak memory 201916 kb
Host smart-7c4fac3d-78aa-48bf-ac9c-c78913544d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306858211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1306858211
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3785427447
Short name T423
Test name
Test status
Simulation time 37803024184 ps
CPU time 89.4 seconds
Started Feb 29 01:14:32 PM PST 24
Finished Feb 29 01:16:02 PM PST 24
Peak memory 201188 kb
Host smart-32adb4cf-6851-452c-9569-899d61039fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785427447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3785427447
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.722696476
Short name T590
Test name
Test status
Simulation time 5423161198 ps
CPU time 4.46 seconds
Started Feb 29 01:14:32 PM PST 24
Finished Feb 29 01:14:36 PM PST 24
Peak memory 201192 kb
Host smart-50156f9d-3870-4fb4-91db-25a58d48ba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722696476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.722696476
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2441451335
Short name T687
Test name
Test status
Simulation time 6219494617 ps
CPU time 3.73 seconds
Started Feb 29 01:14:32 PM PST 24
Finished Feb 29 01:14:36 PM PST 24
Peak memory 201088 kb
Host smart-7fc93314-d984-4ad2-9543-eeac45c5f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441451335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2441451335
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3574632462
Short name T20
Test name
Test status
Simulation time 289381794886 ps
CPU time 988.84 seconds
Started Feb 29 01:14:47 PM PST 24
Finished Feb 29 01:31:17 PM PST 24
Peak memory 201772 kb
Host smart-744b301a-e5a4-4807-a2a4-59a2f6f63aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574632462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3574632462
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.850967569
Short name T246
Test name
Test status
Simulation time 210283639636 ps
CPU time 195.2 seconds
Started Feb 29 01:14:47 PM PST 24
Finished Feb 29 01:18:03 PM PST 24
Peak memory 209988 kb
Host smart-181417b6-eaee-453b-86b9-bd1a39a158ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850967569 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.850967569
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.161437666
Short name T598
Test name
Test status
Simulation time 518652198 ps
CPU time 0.76 seconds
Started Feb 29 01:14:48 PM PST 24
Finished Feb 29 01:14:49 PM PST 24
Peak memory 201100 kb
Host smart-96908ae1-6590-45c2-a273-8f11ffd32ddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161437666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.161437666
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2124389201
Short name T777
Test name
Test status
Simulation time 164484130552 ps
CPU time 149.61 seconds
Started Feb 29 01:14:49 PM PST 24
Finished Feb 29 01:17:19 PM PST 24
Peak memory 201424 kb
Host smart-6fa04e7d-2b33-475a-bd75-4fadabc65cdc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124389201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2124389201
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1104748318
Short name T500
Test name
Test status
Simulation time 352394947134 ps
CPU time 717.3 seconds
Started Feb 29 01:14:47 PM PST 24
Finished Feb 29 01:26:45 PM PST 24
Peak memory 201372 kb
Host smart-83d6959c-0e50-4412-bbff-347a96714e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104748318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1104748318
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.555324581
Short name T307
Test name
Test status
Simulation time 481437777125 ps
CPU time 1123.98 seconds
Started Feb 29 01:14:47 PM PST 24
Finished Feb 29 01:33:31 PM PST 24
Peak memory 201300 kb
Host smart-adea676a-0139-4121-87b8-3e7fad9be85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555324581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.555324581
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.619377132
Short name T87
Test name
Test status
Simulation time 493969730796 ps
CPU time 151.93 seconds
Started Feb 29 01:14:47 PM PST 24
Finished Feb 29 01:17:19 PM PST 24
Peak memory 201444 kb
Host smart-65299913-b173-4f1f-a480-6fad01c2bc28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=619377132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.619377132
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3703354581
Short name T178
Test name
Test status
Simulation time 495290710573 ps
CPU time 653.16 seconds
Started Feb 29 01:14:49 PM PST 24
Finished Feb 29 01:25:42 PM PST 24
Peak memory 201424 kb
Host smart-43e56799-10b4-43f9-acb6-f93ffb3f3d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703354581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3703354581
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4026549814
Short name T758
Test name
Test status
Simulation time 323895252460 ps
CPU time 821.71 seconds
Started Feb 29 01:14:49 PM PST 24
Finished Feb 29 01:28:31 PM PST 24
Peak memory 201448 kb
Host smart-07bd7de5-5cba-4fee-bce5-efaadcf02f8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026549814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4026549814
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1781234622
Short name T636
Test name
Test status
Simulation time 164545280505 ps
CPU time 39.86 seconds
Started Feb 29 01:14:46 PM PST 24
Finished Feb 29 01:15:26 PM PST 24
Peak memory 201448 kb
Host smart-cda88801-0d53-4a04-ad6d-262668b84580
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781234622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1781234622
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1896177816
Short name T593
Test name
Test status
Simulation time 168208030849 ps
CPU time 409.44 seconds
Started Feb 29 01:14:47 PM PST 24
Finished Feb 29 01:21:37 PM PST 24
Peak memory 201252 kb
Host smart-4cf02979-3928-4c98-b191-161e34c03af3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896177816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1896177816
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3547443135
Short name T645
Test name
Test status
Simulation time 71275046223 ps
CPU time 369.23 seconds
Started Feb 29 01:14:47 PM PST 24
Finished Feb 29 01:20:56 PM PST 24
Peak memory 201704 kb
Host smart-4785e80d-518f-45b2-805a-0bb3e666fecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547443135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3547443135
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3838634644
Short name T552
Test name
Test status
Simulation time 27156476985 ps
CPU time 62.44 seconds
Started Feb 29 01:14:48 PM PST 24
Finished Feb 29 01:15:51 PM PST 24
Peak memory 201200 kb
Host smart-e714c4fb-35f4-4b4e-aef3-fff91748d2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838634644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3838634644
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.829610632
Short name T663
Test name
Test status
Simulation time 3358196970 ps
CPU time 7.94 seconds
Started Feb 29 01:14:49 PM PST 24
Finished Feb 29 01:14:57 PM PST 24
Peak memory 201396 kb
Host smart-db162c9c-d4ab-478d-a5e6-c0b343454606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829610632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.829610632
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3894859143
Short name T785
Test name
Test status
Simulation time 5642806976 ps
CPU time 12.31 seconds
Started Feb 29 01:14:50 PM PST 24
Finished Feb 29 01:15:02 PM PST 24
Peak memory 201212 kb
Host smart-8cd47e74-3f45-4b26-b786-4d62ec555a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894859143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3894859143
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1044072132
Short name T220
Test name
Test status
Simulation time 149129120489 ps
CPU time 124.16 seconds
Started Feb 29 01:14:50 PM PST 24
Finished Feb 29 01:16:55 PM PST 24
Peak memory 210008 kb
Host smart-1ad971d6-f3a8-4d7f-a183-baa5f002a542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044072132 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1044072132
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3750732153
Short name T699
Test name
Test status
Simulation time 422890766 ps
CPU time 0.83 seconds
Started Feb 29 01:15:02 PM PST 24
Finished Feb 29 01:15:03 PM PST 24
Peak memory 201156 kb
Host smart-8e00571b-a9d7-40cd-a9b8-cf528630d85e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750732153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3750732153
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2128552236
Short name T247
Test name
Test status
Simulation time 494461599039 ps
CPU time 261.06 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:19:23 PM PST 24
Peak memory 201428 kb
Host smart-ffe1aaaa-598a-481f-92a9-631c29ee9709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128552236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2128552236
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2284273585
Short name T630
Test name
Test status
Simulation time 170124373508 ps
CPU time 103.17 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:16:45 PM PST 24
Peak memory 201356 kb
Host smart-c8b2ca15-2f88-46a7-9058-47f6c6659424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284273585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2284273585
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2294687830
Short name T379
Test name
Test status
Simulation time 484754242501 ps
CPU time 542.22 seconds
Started Feb 29 01:15:04 PM PST 24
Finished Feb 29 01:24:07 PM PST 24
Peak memory 201456 kb
Host smart-ad693df8-678d-4c2b-a04f-7daa5bf0b337
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294687830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2294687830
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1376957392
Short name T283
Test name
Test status
Simulation time 331554638097 ps
CPU time 186.69 seconds
Started Feb 29 01:15:02 PM PST 24
Finished Feb 29 01:18:09 PM PST 24
Peak memory 201408 kb
Host smart-5ecadbc4-e111-4b3d-8cd0-55b4e911865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376957392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1376957392
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1250069529
Short name T474
Test name
Test status
Simulation time 329175677624 ps
CPU time 160.7 seconds
Started Feb 29 01:15:02 PM PST 24
Finished Feb 29 01:17:43 PM PST 24
Peak memory 201376 kb
Host smart-d3803418-c4f6-46d0-a382-f43afbc6c107
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250069529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1250069529
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2521445836
Short name T452
Test name
Test status
Simulation time 162808725715 ps
CPU time 83.58 seconds
Started Feb 29 01:15:00 PM PST 24
Finished Feb 29 01:16:24 PM PST 24
Peak memory 201428 kb
Host smart-61ac68f3-aec8-4523-9e41-4098cb735c21
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521445836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2521445836
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.863899121
Short name T401
Test name
Test status
Simulation time 324214352690 ps
CPU time 782.9 seconds
Started Feb 29 01:15:03 PM PST 24
Finished Feb 29 01:28:07 PM PST 24
Peak memory 201580 kb
Host smart-638eaf61-e8b4-4b2f-b92f-52aa85304531
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863899121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.863899121
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1049889551
Short name T467
Test name
Test status
Simulation time 84749718789 ps
CPU time 356.09 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:20:57 PM PST 24
Peak memory 201760 kb
Host smart-8cf3c990-a697-4af4-b3a0-d6f46d301e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049889551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1049889551
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3346953827
Short name T524
Test name
Test status
Simulation time 24760621249 ps
CPU time 29.19 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:15:30 PM PST 24
Peak memory 201140 kb
Host smart-0a22961b-62d0-44bd-839d-aa3cf1b36671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346953827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3346953827
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.345097842
Short name T648
Test name
Test status
Simulation time 5364167101 ps
CPU time 1.84 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:15:03 PM PST 24
Peak memory 201160 kb
Host smart-4b649cca-762f-42a0-92ad-c8c3fdae05c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345097842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.345097842
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3896938919
Short name T491
Test name
Test status
Simulation time 5749275873 ps
CPU time 14.08 seconds
Started Feb 29 01:14:52 PM PST 24
Finished Feb 29 01:15:06 PM PST 24
Peak memory 201120 kb
Host smart-461d20d3-ba51-49b2-847f-e747eb59dc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896938919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3896938919
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1155125431
Short name T366
Test name
Test status
Simulation time 447319535177 ps
CPU time 657.02 seconds
Started Feb 29 01:15:04 PM PST 24
Finished Feb 29 01:26:01 PM PST 24
Peak memory 212280 kb
Host smart-3897f257-df6b-4c22-9d8b-5aabbbce807c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155125431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1155125431
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1200856300
Short name T786
Test name
Test status
Simulation time 203883766417 ps
CPU time 250.36 seconds
Started Feb 29 01:15:03 PM PST 24
Finished Feb 29 01:19:14 PM PST 24
Peak memory 210108 kb
Host smart-587154be-779d-428d-aed9-ead08471d9e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200856300 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1200856300
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2428086451
Short name T692
Test name
Test status
Simulation time 483076817 ps
CPU time 1.15 seconds
Started Feb 29 01:15:03 PM PST 24
Finished Feb 29 01:15:05 PM PST 24
Peak memory 201128 kb
Host smart-741b951c-a29e-4e3d-9dd1-6f7161dc8bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428086451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2428086451
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1422564339
Short name T749
Test name
Test status
Simulation time 168286394530 ps
CPU time 373.68 seconds
Started Feb 29 01:15:00 PM PST 24
Finished Feb 29 01:21:14 PM PST 24
Peak memory 201380 kb
Host smart-d3477397-7ca4-4900-8a48-6af7186b42c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422564339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1422564339
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.499788221
Short name T660
Test name
Test status
Simulation time 489886410983 ps
CPU time 938.08 seconds
Started Feb 29 01:15:04 PM PST 24
Finished Feb 29 01:30:43 PM PST 24
Peak memory 201440 kb
Host smart-765007ba-c555-4f2e-968e-c831b424565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499788221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.499788221
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3734680488
Short name T356
Test name
Test status
Simulation time 325056311256 ps
CPU time 193.21 seconds
Started Feb 29 01:15:04 PM PST 24
Finished Feb 29 01:18:17 PM PST 24
Peak memory 201444 kb
Host smart-d41a81a5-5427-474b-b3ff-5208fe91f168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734680488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3734680488
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.3709072000
Short name T242
Test name
Test status
Simulation time 335182571316 ps
CPU time 562.37 seconds
Started Feb 29 01:15:02 PM PST 24
Finished Feb 29 01:24:24 PM PST 24
Peak memory 201384 kb
Host smart-c706a885-1cc1-4c83-ba96-de65cada34ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709072000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.3709072000
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1505419726
Short name T549
Test name
Test status
Simulation time 496905739658 ps
CPU time 1134.08 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:33:55 PM PST 24
Peak memory 201388 kb
Host smart-75530114-e771-4bb8-a25b-71f0842da7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505419726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1505419726
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2004034997
Short name T542
Test name
Test status
Simulation time 478009720948 ps
CPU time 1165.56 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:34:27 PM PST 24
Peak memory 201396 kb
Host smart-88069004-bd72-4ff7-bc07-76489c677614
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004034997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2004034997
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4141555661
Short name T312
Test name
Test status
Simulation time 166095521162 ps
CPU time 143.44 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:17:25 PM PST 24
Peak memory 201412 kb
Host smart-8d166e41-b00f-42b8-8cec-9fe1293bf4a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141555661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4141555661
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1431756698
Short name T66
Test name
Test status
Simulation time 343650902447 ps
CPU time 75.24 seconds
Started Feb 29 01:15:02 PM PST 24
Finished Feb 29 01:16:17 PM PST 24
Peak memory 201396 kb
Host smart-ed652b7e-05f1-4c56-a34a-add3a5fe6455
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431756698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1431756698
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1232476866
Short name T185
Test name
Test status
Simulation time 29799358637 ps
CPU time 66.82 seconds
Started Feb 29 01:15:04 PM PST 24
Finished Feb 29 01:16:11 PM PST 24
Peak memory 201192 kb
Host smart-8743cbad-60d9-4ca6-a98d-256d0942bd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232476866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1232476866
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2525565908
Short name T510
Test name
Test status
Simulation time 5054868571 ps
CPU time 2.82 seconds
Started Feb 29 01:15:02 PM PST 24
Finished Feb 29 01:15:05 PM PST 24
Peak memory 201404 kb
Host smart-96e3c9c4-9e76-4c3b-81c7-d8c32d9f7834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525565908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2525565908
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3312043492
Short name T538
Test name
Test status
Simulation time 5901064110 ps
CPU time 4.09 seconds
Started Feb 29 01:15:01 PM PST 24
Finished Feb 29 01:15:06 PM PST 24
Peak memory 201396 kb
Host smart-6f3329bb-4d99-4565-9ea7-4523708a4ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312043492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3312043492
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.67826649
Short name T194
Test name
Test status
Simulation time 169586330160 ps
CPU time 209.32 seconds
Started Feb 29 01:15:04 PM PST 24
Finished Feb 29 01:18:34 PM PST 24
Peak memory 201316 kb
Host smart-8d970857-ea77-4b1c-b01c-2aeaf15a0571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67826649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.67826649
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.447861413
Short name T724
Test name
Test status
Simulation time 516005674 ps
CPU time 0.79 seconds
Started Feb 29 01:15:16 PM PST 24
Finished Feb 29 01:15:17 PM PST 24
Peak memory 201092 kb
Host smart-d1b0bc1d-50a6-4a73-b040-a9c3479d6257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447861413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.447861413
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1231495314
Short name T343
Test name
Test status
Simulation time 331774032342 ps
CPU time 729.26 seconds
Started Feb 29 01:15:14 PM PST 24
Finished Feb 29 01:27:23 PM PST 24
Peak memory 201396 kb
Host smart-41442597-5a9c-45ef-a46a-2bc1ba25f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231495314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1231495314
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.232204229
Short name T730
Test name
Test status
Simulation time 165189451266 ps
CPU time 108.43 seconds
Started Feb 29 01:15:05 PM PST 24
Finished Feb 29 01:16:53 PM PST 24
Peak memory 201364 kb
Host smart-56eba8f4-f74d-4833-a7e7-6668843f4859
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=232204229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.232204229
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.2884707608
Short name T193
Test name
Test status
Simulation time 332321764489 ps
CPU time 182.6 seconds
Started Feb 29 01:15:04 PM PST 24
Finished Feb 29 01:18:07 PM PST 24
Peak memory 201464 kb
Host smart-b0592084-dbf6-4825-ab05-3b9bf3a4de8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884707608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.2884707608
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.441563442
Short name T507
Test name
Test status
Simulation time 325522618924 ps
CPU time 659.97 seconds
Started Feb 29 01:15:04 PM PST 24
Finished Feb 29 01:26:04 PM PST 24
Peak memory 201388 kb
Host smart-61406d98-bf33-46a6-9ca3-58275fd32f28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=441563442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.441563442
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3927767510
Short name T539
Test name
Test status
Simulation time 327811069935 ps
CPU time 795.61 seconds
Started Feb 29 01:15:14 PM PST 24
Finished Feb 29 01:28:29 PM PST 24
Peak memory 201384 kb
Host smart-d400caae-5cc4-41eb-8cf9-246fc67c1c13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927767510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3927767510
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.4245295892
Short name T682
Test name
Test status
Simulation time 76121862947 ps
CPU time 426.68 seconds
Started Feb 29 01:15:14 PM PST 24
Finished Feb 29 01:22:21 PM PST 24
Peak memory 201780 kb
Host smart-70d26e1e-4e1f-4131-b94e-81e8ce5c3976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245295892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.4245295892
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2598362413
Short name T404
Test name
Test status
Simulation time 45776865643 ps
CPU time 29.01 seconds
Started Feb 29 01:15:14 PM PST 24
Finished Feb 29 01:15:44 PM PST 24
Peak memory 201224 kb
Host smart-607cee4c-401a-45e9-b3ae-02b44d53ab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598362413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2598362413
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1613730560
Short name T390
Test name
Test status
Simulation time 3818976348 ps
CPU time 7.33 seconds
Started Feb 29 01:15:14 PM PST 24
Finished Feb 29 01:15:21 PM PST 24
Peak memory 201224 kb
Host smart-d6c9cb48-c0ea-4347-ae96-aae957780450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613730560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1613730560
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4018676397
Short name T669
Test name
Test status
Simulation time 5848187101 ps
CPU time 13.21 seconds
Started Feb 29 01:15:03 PM PST 24
Finished Feb 29 01:15:16 PM PST 24
Peak memory 201140 kb
Host smart-1dc69094-ba57-45da-968b-f95c365d3cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018676397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4018676397
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1738281897
Short name T459
Test name
Test status
Simulation time 38481712595 ps
CPU time 85.96 seconds
Started Feb 29 01:15:19 PM PST 24
Finished Feb 29 01:16:45 PM PST 24
Peak memory 201180 kb
Host smart-2aabdec9-2240-4696-9d6d-0eaf700504de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738281897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1738281897
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.338609147
Short name T218
Test name
Test status
Simulation time 21432821562 ps
CPU time 47.89 seconds
Started Feb 29 01:15:15 PM PST 24
Finished Feb 29 01:16:03 PM PST 24
Peak memory 209756 kb
Host smart-cf9f96ae-79db-41ce-832e-b1550ab82396
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338609147 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.338609147
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.165591538
Short name T37
Test name
Test status
Simulation time 419376671 ps
CPU time 1.51 seconds
Started Feb 29 01:15:16 PM PST 24
Finished Feb 29 01:15:18 PM PST 24
Peak memory 201024 kb
Host smart-4e29d153-0010-4e37-9950-53a664f75298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165591538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.165591538
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3492994419
Short name T266
Test name
Test status
Simulation time 492950722971 ps
CPU time 430.39 seconds
Started Feb 29 01:15:16 PM PST 24
Finished Feb 29 01:22:26 PM PST 24
Peak memory 201336 kb
Host smart-8dccbf0a-1c63-40b5-b688-e3e038d1a5fa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492994419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3492994419
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3757563728
Short name T439
Test name
Test status
Simulation time 164542577425 ps
CPU time 188.44 seconds
Started Feb 29 01:15:15 PM PST 24
Finished Feb 29 01:18:24 PM PST 24
Peak memory 201512 kb
Host smart-06e94e51-35ef-4daa-82b4-f7de4cc4504b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757563728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3757563728
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1476733652
Short name T292
Test name
Test status
Simulation time 479805086129 ps
CPU time 257.54 seconds
Started Feb 29 01:15:17 PM PST 24
Finished Feb 29 01:19:35 PM PST 24
Peak memory 201476 kb
Host smart-f311ce3d-9b60-4397-adba-e26207c69a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476733652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1476733652
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1794014828
Short name T762
Test name
Test status
Simulation time 333338046374 ps
CPU time 803.46 seconds
Started Feb 29 01:15:18 PM PST 24
Finished Feb 29 01:28:42 PM PST 24
Peak memory 201448 kb
Host smart-cc93f244-8d71-4730-9f07-a1e780aa8319
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794014828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1794014828
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3172015126
Short name T696
Test name
Test status
Simulation time 159986030791 ps
CPU time 192.18 seconds
Started Feb 29 01:15:14 PM PST 24
Finished Feb 29 01:18:26 PM PST 24
Peak memory 201452 kb
Host smart-10421e91-66c5-4b1c-8477-ed34a5f58f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172015126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3172015126
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1817079629
Short name T723
Test name
Test status
Simulation time 490027175105 ps
CPU time 322.43 seconds
Started Feb 29 01:15:19 PM PST 24
Finished Feb 29 01:20:42 PM PST 24
Peak memory 201368 kb
Host smart-e38c5938-7681-4ed8-a265-bb3134a95753
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817079629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1817079629
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1644779079
Short name T328
Test name
Test status
Simulation time 496498595721 ps
CPU time 1215.55 seconds
Started Feb 29 01:15:15 PM PST 24
Finished Feb 29 01:35:30 PM PST 24
Peak memory 201608 kb
Host smart-8e6407b0-be8c-4270-9fe0-55aff06b504d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644779079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1644779079
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.40968368
Short name T399
Test name
Test status
Simulation time 493522209871 ps
CPU time 309.64 seconds
Started Feb 29 01:15:15 PM PST 24
Finished Feb 29 01:20:26 PM PST 24
Peak memory 201332 kb
Host smart-6abb5f5d-9a5b-4c7a-a977-fcede84b58af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40968368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.a
dc_ctrl_filters_wakeup_fixed.40968368
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.682352690
Short name T21
Test name
Test status
Simulation time 89095278624 ps
CPU time 453.64 seconds
Started Feb 29 01:15:19 PM PST 24
Finished Feb 29 01:22:53 PM PST 24
Peak memory 201748 kb
Host smart-f342982f-8d88-4170-bf60-5ded94b35a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682352690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.682352690
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.810283183
Short name T372
Test name
Test status
Simulation time 41678876411 ps
CPU time 50.16 seconds
Started Feb 29 01:15:16 PM PST 24
Finished Feb 29 01:16:06 PM PST 24
Peak memory 201212 kb
Host smart-2bfda8f6-6b4e-453c-beb1-e290aa4a4a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810283183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.810283183
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.4211291390
Short name T421
Test name
Test status
Simulation time 3468813966 ps
CPU time 4.8 seconds
Started Feb 29 01:15:17 PM PST 24
Finished Feb 29 01:15:22 PM PST 24
Peak memory 201208 kb
Host smart-5ab34fd1-dfe4-4889-8004-93096317dd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211291390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4211291390
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2677238022
Short name T387
Test name
Test status
Simulation time 5782533584 ps
CPU time 13.37 seconds
Started Feb 29 01:15:14 PM PST 24
Finished Feb 29 01:15:28 PM PST 24
Peak memory 201204 kb
Host smart-45f74e95-eae6-4a3a-a67d-105a7dd8c04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677238022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2677238022
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2396600312
Short name T222
Test name
Test status
Simulation time 357586162453 ps
CPU time 616.81 seconds
Started Feb 29 01:15:13 PM PST 24
Finished Feb 29 01:25:31 PM PST 24
Peak memory 209760 kb
Host smart-d1e63485-7f0d-40ec-8967-533000934afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396600312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2396600312
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1967040632
Short name T489
Test name
Test status
Simulation time 388825925 ps
CPU time 1.45 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:12:49 PM PST 24
Peak memory 200884 kb
Host smart-37ac2b8b-b7a9-4d6e-a2f9-dbacc1f3bb3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967040632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1967040632
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.852972060
Short name T737
Test name
Test status
Simulation time 493317467703 ps
CPU time 358.89 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:18:45 PM PST 24
Peak memory 201368 kb
Host smart-15c59857-7bf5-4f25-aa09-1e2423a8cc4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852972060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.852972060
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2668653788
Short name T586
Test name
Test status
Simulation time 162523239389 ps
CPU time 182.27 seconds
Started Feb 29 01:12:31 PM PST 24
Finished Feb 29 01:15:33 PM PST 24
Peak memory 201656 kb
Host smart-7822567e-d112-4f36-a063-f610e7a0d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668653788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2668653788
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4178401923
Short name T666
Test name
Test status
Simulation time 487836510381 ps
CPU time 300.97 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:17:29 PM PST 24
Peak memory 201348 kb
Host smart-31f74040-afb2-46a4-a347-2d8c42047b82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178401923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4178401923
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3976126587
Short name T486
Test name
Test status
Simulation time 327542729049 ps
CPU time 109.45 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:14:18 PM PST 24
Peak memory 201384 kb
Host smart-ae321a9a-6a89-47ac-b25b-3c8051f5fcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976126587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3976126587
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.338156177
Short name T165
Test name
Test status
Simulation time 163770666893 ps
CPU time 94.92 seconds
Started Feb 29 01:12:31 PM PST 24
Finished Feb 29 01:14:06 PM PST 24
Peak memory 201680 kb
Host smart-06eac3c8-df09-4285-b65e-5a711604756d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=338156177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.338156177
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.4233083045
Short name T345
Test name
Test status
Simulation time 326107049365 ps
CPU time 362.61 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:18:31 PM PST 24
Peak memory 201348 kb
Host smart-acef6762-9940-4702-9f5e-bf19f68ad6aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233083045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.4233083045
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2626279563
Short name T449
Test name
Test status
Simulation time 160005007814 ps
CPU time 144.95 seconds
Started Feb 29 01:12:27 PM PST 24
Finished Feb 29 01:14:52 PM PST 24
Peak memory 201292 kb
Host smart-fe7d2917-5c7a-4e28-ac0b-b70a5038771a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626279563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2626279563
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.4054231489
Short name T8
Test name
Test status
Simulation time 129651605684 ps
CPU time 473.74 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:20:41 PM PST 24
Peak memory 201468 kb
Host smart-43dedfa4-ea0a-4973-9255-9bfa383975a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054231489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.4054231489
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1047098232
Short name T727
Test name
Test status
Simulation time 28661000801 ps
CPU time 33.08 seconds
Started Feb 29 01:12:43 PM PST 24
Finished Feb 29 01:13:17 PM PST 24
Peak memory 201260 kb
Host smart-2bfc840d-be10-485a-98e9-0c2d2d046d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047098232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1047098232
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3927591773
Short name T628
Test name
Test status
Simulation time 5169102231 ps
CPU time 3.85 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:12:50 PM PST 24
Peak memory 201100 kb
Host smart-528705fc-521a-4015-8681-3541b45138fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927591773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3927591773
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2584183555
Short name T41
Test name
Test status
Simulation time 7562670765 ps
CPU time 9.76 seconds
Started Feb 29 01:12:48 PM PST 24
Finished Feb 29 01:12:58 PM PST 24
Peak memory 217216 kb
Host smart-865c0837-2120-4131-a53b-6bc14a19c5ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584183555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2584183555
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3863190251
Short name T68
Test name
Test status
Simulation time 5940695028 ps
CPU time 15.96 seconds
Started Feb 29 01:12:28 PM PST 24
Finished Feb 29 01:12:44 PM PST 24
Peak memory 201144 kb
Host smart-a08b7a17-388b-4f77-910d-279e8bddc5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863190251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3863190251
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3765777195
Short name T782
Test name
Test status
Simulation time 122655756530 ps
CPU time 487.68 seconds
Started Feb 29 01:12:44 PM PST 24
Finished Feb 29 01:20:52 PM PST 24
Peak memory 201680 kb
Host smart-b95ac9c6-3b51-44d4-b7b0-b6725a0cbe03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765777195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3765777195
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3356341797
Short name T211
Test name
Test status
Simulation time 22025710681 ps
CPU time 88.5 seconds
Started Feb 29 01:12:45 PM PST 24
Finished Feb 29 01:14:14 PM PST 24
Peak memory 216288 kb
Host smart-d4a0d249-1468-4aad-88d7-ec5d6fbb53b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356341797 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3356341797
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.523678881
Short name T195
Test name
Test status
Simulation time 469332082 ps
CPU time 1.08 seconds
Started Feb 29 01:15:42 PM PST 24
Finished Feb 29 01:15:43 PM PST 24
Peak memory 201128 kb
Host smart-6b8a91d6-6877-4087-b9b8-9eed60c68cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523678881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.523678881
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.994782080
Short name T319
Test name
Test status
Simulation time 321589820459 ps
CPU time 767.4 seconds
Started Feb 29 01:15:27 PM PST 24
Finished Feb 29 01:28:15 PM PST 24
Peak memory 201480 kb
Host smart-661692a1-5f14-49f1-8af8-ed0e578f080a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994782080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.994782080
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2868407141
Short name T771
Test name
Test status
Simulation time 485235239094 ps
CPU time 1137.13 seconds
Started Feb 29 01:15:25 PM PST 24
Finished Feb 29 01:34:23 PM PST 24
Peak memory 201352 kb
Host smart-8e55557c-f09b-460d-b0e0-a4859d3d243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868407141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2868407141
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.4263629950
Short name T435
Test name
Test status
Simulation time 168192164423 ps
CPU time 406.07 seconds
Started Feb 29 01:15:25 PM PST 24
Finished Feb 29 01:22:12 PM PST 24
Peak memory 201428 kb
Host smart-95cd89ba-4ff6-497b-a864-1189e86b591e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263629950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.4263629950
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.2062674286
Short name T232
Test name
Test status
Simulation time 483220205983 ps
CPU time 992.87 seconds
Started Feb 29 01:15:14 PM PST 24
Finished Feb 29 01:31:47 PM PST 24
Peak memory 201404 kb
Host smart-2db9efd2-011e-492a-8b38-77d9dfdac897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062674286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.2062674286
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.4019965497
Short name T49
Test name
Test status
Simulation time 334943414963 ps
CPU time 725.37 seconds
Started Feb 29 01:15:17 PM PST 24
Finished Feb 29 01:27:22 PM PST 24
Peak memory 201396 kb
Host smart-c4adc125-3e3c-4916-a766-836f6a653ddd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019965497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.4019965497
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3496073501
Short name T257
Test name
Test status
Simulation time 335757225301 ps
CPU time 206.22 seconds
Started Feb 29 01:15:26 PM PST 24
Finished Feb 29 01:18:53 PM PST 24
Peak memory 201396 kb
Host smart-5c999ea2-ade1-41ec-8d98-ba6d4c132068
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496073501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3496073501
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.316064564
Short name T464
Test name
Test status
Simulation time 492666586999 ps
CPU time 1135.42 seconds
Started Feb 29 01:15:26 PM PST 24
Finished Feb 29 01:34:23 PM PST 24
Peak memory 201400 kb
Host smart-80561e44-a7d0-40c9-874d-6598d2e0092c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316064564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
adc_ctrl_filters_wakeup_fixed.316064564
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.652707479
Short name T81
Test name
Test status
Simulation time 83603749447 ps
CPU time 466.41 seconds
Started Feb 29 01:15:26 PM PST 24
Finished Feb 29 01:23:13 PM PST 24
Peak memory 201580 kb
Host smart-c89b7809-370a-4255-b77b-374ce14be821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652707479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.652707479
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3073577466
Short name T714
Test name
Test status
Simulation time 29402498191 ps
CPU time 18.76 seconds
Started Feb 29 01:15:26 PM PST 24
Finished Feb 29 01:15:46 PM PST 24
Peak memory 201176 kb
Host smart-2144432e-f81d-45df-bc2a-3fd627c1abc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073577466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3073577466
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3273789987
Short name T518
Test name
Test status
Simulation time 5084687611 ps
CPU time 11.17 seconds
Started Feb 29 01:15:25 PM PST 24
Finished Feb 29 01:15:37 PM PST 24
Peak memory 201196 kb
Host smart-14a500f7-c8c0-4149-85d4-f9647e185c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273789987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3273789987
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2251989309
Short name T378
Test name
Test status
Simulation time 5655262128 ps
CPU time 4.34 seconds
Started Feb 29 01:15:16 PM PST 24
Finished Feb 29 01:15:21 PM PST 24
Peak memory 201104 kb
Host smart-30b33ff6-e3bc-40dc-91a4-da6427ab0a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251989309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2251989309
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.978550280
Short name T176
Test name
Test status
Simulation time 189862026053 ps
CPU time 711.08 seconds
Started Feb 29 01:15:27 PM PST 24
Finished Feb 29 01:27:18 PM PST 24
Peak memory 201764 kb
Host smart-5ba9a749-38f5-459e-9173-01dc9d17131c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978550280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
978550280
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.739228161
Short name T747
Test name
Test status
Simulation time 81558456435 ps
CPU time 96.89 seconds
Started Feb 29 01:15:27 PM PST 24
Finished Feb 29 01:17:05 PM PST 24
Peak memory 210028 kb
Host smart-99a7fabb-d8d9-463f-8ead-5c682e09bc0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739228161 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.739228161
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.4007688064
Short name T383
Test name
Test status
Simulation time 399264742 ps
CPU time 0.83 seconds
Started Feb 29 01:15:42 PM PST 24
Finished Feb 29 01:15:43 PM PST 24
Peak memory 201144 kb
Host smart-5a9584c2-baf8-4903-8731-d80a63d74555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007688064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.4007688064
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.972148154
Short name T284
Test name
Test status
Simulation time 162667309128 ps
CPU time 93.74 seconds
Started Feb 29 01:15:44 PM PST 24
Finished Feb 29 01:17:18 PM PST 24
Peak memory 201360 kb
Host smart-c6ea8994-9ae9-45bf-980a-8131692d301f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972148154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.972148154
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.542813325
Short name T358
Test name
Test status
Simulation time 495680640808 ps
CPU time 1070.12 seconds
Started Feb 29 01:15:45 PM PST 24
Finished Feb 29 01:33:35 PM PST 24
Peak memory 201492 kb
Host smart-dc58c63b-b958-46f3-8e59-7482111dcb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542813325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.542813325
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2651274196
Short name T739
Test name
Test status
Simulation time 329845925271 ps
CPU time 84.9 seconds
Started Feb 29 01:15:45 PM PST 24
Finished Feb 29 01:17:10 PM PST 24
Peak memory 201592 kb
Host smart-5aa85bab-006a-44aa-bd1c-f0531f8ec2b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651274196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2651274196
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2747420400
Short name T305
Test name
Test status
Simulation time 488615210691 ps
CPU time 298.74 seconds
Started Feb 29 01:15:43 PM PST 24
Finished Feb 29 01:20:41 PM PST 24
Peak memory 201608 kb
Host smart-5b996baa-c290-4baf-9c10-f80907c8ab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747420400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2747420400
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3636749374
Short name T480
Test name
Test status
Simulation time 334663862759 ps
CPU time 243.59 seconds
Started Feb 29 01:15:45 PM PST 24
Finished Feb 29 01:19:49 PM PST 24
Peak memory 201300 kb
Host smart-0c410f9d-73ac-4f07-bc84-8dc28a246eb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636749374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3636749374
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2559750369
Short name T788
Test name
Test status
Simulation time 325272702416 ps
CPU time 170.92 seconds
Started Feb 29 01:15:42 PM PST 24
Finished Feb 29 01:18:33 PM PST 24
Peak memory 201476 kb
Host smart-c9c640ae-e23a-4b8e-8fad-39837d0db662
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559750369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2559750369
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.2837782237
Short name T789
Test name
Test status
Simulation time 485856397876 ps
CPU time 1081.13 seconds
Started Feb 29 01:15:43 PM PST 24
Finished Feb 29 01:33:44 PM PST 24
Peak memory 201468 kb
Host smart-2b739735-d130-40c6-a61e-338ea035ffa2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837782237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.2837782237
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3377929698
Short name T368
Test name
Test status
Simulation time 82388121274 ps
CPU time 312.89 seconds
Started Feb 29 01:15:50 PM PST 24
Finished Feb 29 01:21:03 PM PST 24
Peak memory 201560 kb
Host smart-b98c2e43-62de-4875-b9b1-40a85e9e979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377929698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3377929698
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2711822343
Short name T698
Test name
Test status
Simulation time 38554704645 ps
CPU time 11.36 seconds
Started Feb 29 01:15:42 PM PST 24
Finished Feb 29 01:15:54 PM PST 24
Peak memory 201196 kb
Host smart-428c26b3-378e-4fa5-8608-bc87f95dec77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711822343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2711822343
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.962720996
Short name T389
Test name
Test status
Simulation time 3643958189 ps
CPU time 5.12 seconds
Started Feb 29 01:15:44 PM PST 24
Finished Feb 29 01:15:49 PM PST 24
Peak memory 201164 kb
Host smart-83813a52-e37b-46ad-af63-e090cc7194a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962720996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.962720996
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3700541249
Short name T414
Test name
Test status
Simulation time 6192620359 ps
CPU time 4.05 seconds
Started Feb 29 01:15:45 PM PST 24
Finished Feb 29 01:15:49 PM PST 24
Peak memory 201108 kb
Host smart-a75c7bb7-c976-4299-984c-c5c7ec6c4325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700541249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3700541249
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.374989461
Short name T221
Test name
Test status
Simulation time 6120527335 ps
CPU time 8.65 seconds
Started Feb 29 01:15:43 PM PST 24
Finished Feb 29 01:15:52 PM PST 24
Peak memory 201152 kb
Host smart-a8162568-a712-4770-beeb-a94ffed9f43a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374989461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
374989461
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2722540539
Short name T270
Test name
Test status
Simulation time 210328829993 ps
CPU time 300.22 seconds
Started Feb 29 01:15:43 PM PST 24
Finished Feb 29 01:20:44 PM PST 24
Peak memory 209980 kb
Host smart-5db5a8e9-f5ba-407e-9b59-be29e31747f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722540539 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2722540539
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.90224770
Short name T39
Test name
Test status
Simulation time 359493024 ps
CPU time 1.39 seconds
Started Feb 29 01:15:58 PM PST 24
Finished Feb 29 01:16:00 PM PST 24
Peak memory 201076 kb
Host smart-28e2ad8f-18f3-4aae-bb82-17ea7b9d9b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90224770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.90224770
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3137166834
Short name T545
Test name
Test status
Simulation time 495500753204 ps
CPU time 204.85 seconds
Started Feb 29 01:15:58 PM PST 24
Finished Feb 29 01:19:23 PM PST 24
Peak memory 201312 kb
Host smart-e9a1abfb-7e8d-499f-a955-682c9fafc0a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137166834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3137166834
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1713532934
Short name T678
Test name
Test status
Simulation time 331599126329 ps
CPU time 196.6 seconds
Started Feb 29 01:16:01 PM PST 24
Finished Feb 29 01:19:17 PM PST 24
Peak memory 201628 kb
Host smart-43d22f83-1057-4ba9-b97f-57ded36dab35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713532934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1713532934
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.3218079329
Short name T405
Test name
Test status
Simulation time 329305816715 ps
CPU time 752.85 seconds
Started Feb 29 01:16:00 PM PST 24
Finished Feb 29 01:28:33 PM PST 24
Peak memory 201380 kb
Host smart-0c42251f-b376-432b-b7af-9add1f737d93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218079329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.3218079329
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.3817649786
Short name T260
Test name
Test status
Simulation time 163354380163 ps
CPU time 119.19 seconds
Started Feb 29 01:15:42 PM PST 24
Finished Feb 29 01:17:41 PM PST 24
Peak memory 201404 kb
Host smart-7297ecfc-a93e-44b7-aa2c-e1b023d22633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817649786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.3817649786
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4021168041
Short name T517
Test name
Test status
Simulation time 491111170412 ps
CPU time 1036.97 seconds
Started Feb 29 01:15:45 PM PST 24
Finished Feb 29 01:33:02 PM PST 24
Peak memory 201592 kb
Host smart-cbc150ab-5a23-44dc-9f74-c72bf3eb8326
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021168041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4021168041
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2610143516
Short name T301
Test name
Test status
Simulation time 324076369571 ps
CPU time 806.17 seconds
Started Feb 29 01:15:59 PM PST 24
Finished Feb 29 01:29:25 PM PST 24
Peak memory 201464 kb
Host smart-2d527564-2f52-4afd-9e45-c6a517c5ca28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610143516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2610143516
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.815264525
Short name T63
Test name
Test status
Simulation time 504086846526 ps
CPU time 1143.47 seconds
Started Feb 29 01:15:58 PM PST 24
Finished Feb 29 01:35:02 PM PST 24
Peak memory 201444 kb
Host smart-062eb588-0343-4db8-a93c-330eebdeb02e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815264525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.815264525
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1902212862
Short name T146
Test name
Test status
Simulation time 36129004830 ps
CPU time 21.72 seconds
Started Feb 29 01:15:57 PM PST 24
Finished Feb 29 01:16:18 PM PST 24
Peak memory 201196 kb
Host smart-94215bc9-99ae-4865-b69d-7b2f2c587634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902212862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1902212862
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1931231349
Short name T76
Test name
Test status
Simulation time 3795108825 ps
CPU time 10.25 seconds
Started Feb 29 01:16:02 PM PST 24
Finished Feb 29 01:16:12 PM PST 24
Peak memory 201208 kb
Host smart-fa687b30-92e9-4289-9415-526f2c1f7089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931231349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1931231349
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1051028042
Short name T434
Test name
Test status
Simulation time 6018330111 ps
CPU time 13.81 seconds
Started Feb 29 01:15:44 PM PST 24
Finished Feb 29 01:15:58 PM PST 24
Peak memory 201032 kb
Host smart-a656050d-ad50-4a9c-b920-bf519e8c51e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051028042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1051028042
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2318356744
Short name T508
Test name
Test status
Simulation time 332820246 ps
CPU time 1.33 seconds
Started Feb 29 01:16:18 PM PST 24
Finished Feb 29 01:16:20 PM PST 24
Peak memory 201136 kb
Host smart-a2e8fc60-8c1b-4672-9416-bfbf1b1a4974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318356744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2318356744
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1921423677
Short name T186
Test name
Test status
Simulation time 160253120116 ps
CPU time 176.77 seconds
Started Feb 29 01:16:18 PM PST 24
Finished Feb 29 01:19:15 PM PST 24
Peak memory 201392 kb
Host smart-d901cb34-092f-4212-aec2-3b0abfff3607
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921423677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1921423677
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1217388875
Short name T124
Test name
Test status
Simulation time 324135462725 ps
CPU time 224.3 seconds
Started Feb 29 01:16:01 PM PST 24
Finished Feb 29 01:19:46 PM PST 24
Peak memory 201440 kb
Host smart-1130bff3-f90a-4be5-a35b-5713ee4f2f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217388875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1217388875
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2420960588
Short name T757
Test name
Test status
Simulation time 166848046294 ps
CPU time 382.97 seconds
Started Feb 29 01:16:00 PM PST 24
Finished Feb 29 01:22:23 PM PST 24
Peak memory 201452 kb
Host smart-dbe382bb-c682-458c-b721-bee22be2f3ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420960588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2420960588
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.576220777
Short name T173
Test name
Test status
Simulation time 494136185218 ps
CPU time 239.27 seconds
Started Feb 29 01:16:00 PM PST 24
Finished Feb 29 01:19:59 PM PST 24
Peak memory 201372 kb
Host smart-9ce2ff96-5ad9-435e-9377-6c6ae1424b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576220777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.576220777
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1772168580
Short name T694
Test name
Test status
Simulation time 327147710199 ps
CPU time 180.48 seconds
Started Feb 29 01:15:58 PM PST 24
Finished Feb 29 01:18:59 PM PST 24
Peak memory 201476 kb
Host smart-4317ed2d-afeb-4b59-8949-30bdf6a16b73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772168580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1772168580
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4147747808
Short name T279
Test name
Test status
Simulation time 171170807735 ps
CPU time 107.19 seconds
Started Feb 29 01:16:00 PM PST 24
Finished Feb 29 01:17:47 PM PST 24
Peak memory 201384 kb
Host smart-cf0a8763-ed95-4cb2-8a66-2cdade2ee6f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147747808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4147747808
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1032724310
Short name T411
Test name
Test status
Simulation time 167382642555 ps
CPU time 358.61 seconds
Started Feb 29 01:16:00 PM PST 24
Finished Feb 29 01:21:59 PM PST 24
Peak memory 201376 kb
Host smart-85d9e000-4a7d-4133-8860-b2a32b9573b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032724310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1032724310
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3844431949
Short name T227
Test name
Test status
Simulation time 105295391865 ps
CPU time 593.51 seconds
Started Feb 29 01:16:15 PM PST 24
Finished Feb 29 01:26:09 PM PST 24
Peak memory 201776 kb
Host smart-41341c2d-40fc-4075-b6c0-4cc4dbd35ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844431949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3844431949
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2913476633
Short name T472
Test name
Test status
Simulation time 36989422496 ps
CPU time 20.39 seconds
Started Feb 29 01:16:21 PM PST 24
Finished Feb 29 01:16:42 PM PST 24
Peak memory 201236 kb
Host smart-ec32763b-4b56-4335-9157-9c5c51b51b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913476633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2913476633
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3700719203
Short name T613
Test name
Test status
Simulation time 5105799312 ps
CPU time 3.55 seconds
Started Feb 29 01:16:20 PM PST 24
Finished Feb 29 01:16:24 PM PST 24
Peak memory 201244 kb
Host smart-d727298c-364b-43d4-9fc8-4273d9ed8f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700719203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3700719203
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1422369905
Short name T755
Test name
Test status
Simulation time 5886851744 ps
CPU time 7.11 seconds
Started Feb 29 01:15:58 PM PST 24
Finished Feb 29 01:16:06 PM PST 24
Peak memory 201004 kb
Host smart-e36fcbae-b4ba-4a74-94f6-548c96c4802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422369905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1422369905
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.620771983
Short name T320
Test name
Test status
Simulation time 338861622890 ps
CPU time 200.53 seconds
Started Feb 29 01:16:17 PM PST 24
Finished Feb 29 01:19:38 PM PST 24
Peak memory 201592 kb
Host smart-8c0bd302-7054-44bf-9679-206fe9f88c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620771983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
620771983
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3829543152
Short name T206
Test name
Test status
Simulation time 262811976757 ps
CPU time 335.01 seconds
Started Feb 29 01:16:21 PM PST 24
Finished Feb 29 01:21:57 PM PST 24
Peak memory 210124 kb
Host smart-c2ce7f4c-a101-4c88-84b9-f2d79670f87e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829543152 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3829543152
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2683126547
Short name T731
Test name
Test status
Simulation time 331843788 ps
CPU time 0.72 seconds
Started Feb 29 01:16:17 PM PST 24
Finished Feb 29 01:16:18 PM PST 24
Peak memory 201116 kb
Host smart-cfc39459-920f-45ed-9283-2d46715008d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683126547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2683126547
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1171693343
Short name T321
Test name
Test status
Simulation time 166978609516 ps
CPU time 204.82 seconds
Started Feb 29 01:16:17 PM PST 24
Finished Feb 29 01:19:42 PM PST 24
Peak memory 201312 kb
Host smart-cc6edd30-ca97-4e77-a99d-f46ca56b34a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171693343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1171693343
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2650763547
Short name T241
Test name
Test status
Simulation time 156816672628 ps
CPU time 379.57 seconds
Started Feb 29 01:16:17 PM PST 24
Finished Feb 29 01:22:37 PM PST 24
Peak memory 201384 kb
Host smart-2e23d37e-e4e4-4c12-b7eb-a08389d51790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650763547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2650763547
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3754197902
Short name T547
Test name
Test status
Simulation time 485889182022 ps
CPU time 523.59 seconds
Started Feb 29 01:16:15 PM PST 24
Finished Feb 29 01:25:00 PM PST 24
Peak memory 201408 kb
Host smart-4c29cefd-9385-4cc2-b660-9b38a7f1f85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754197902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3754197902
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.91348202
Short name T152
Test name
Test status
Simulation time 169377678562 ps
CPU time 75.62 seconds
Started Feb 29 01:16:15 PM PST 24
Finished Feb 29 01:17:31 PM PST 24
Peak memory 201396 kb
Host smart-df84fcf8-f448-430d-82c0-d237c7f86143
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=91348202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt
_fixed.91348202
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.4120829753
Short name T654
Test name
Test status
Simulation time 158510945475 ps
CPU time 183.49 seconds
Started Feb 29 01:16:16 PM PST 24
Finished Feb 29 01:19:20 PM PST 24
Peak memory 201476 kb
Host smart-9e48bc4e-8e57-4a8e-93ca-307fd5ae536f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120829753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.4120829753
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.3330489165
Short name T718
Test name
Test status
Simulation time 493401467169 ps
CPU time 493.61 seconds
Started Feb 29 01:16:16 PM PST 24
Finished Feb 29 01:24:30 PM PST 24
Peak memory 201592 kb
Host smart-e2862b3b-28a6-461b-8f96-6908cc57e50b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330489165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.3330489165
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.356824181
Short name T690
Test name
Test status
Simulation time 323663496374 ps
CPU time 761.82 seconds
Started Feb 29 01:16:27 PM PST 24
Finished Feb 29 01:29:09 PM PST 24
Peak memory 201380 kb
Host smart-2fbce1d5-8820-4d18-ade8-18976808922f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356824181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.356824181
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.634578481
Short name T196
Test name
Test status
Simulation time 119654549378 ps
CPU time 431.19 seconds
Started Feb 29 01:16:16 PM PST 24
Finished Feb 29 01:23:28 PM PST 24
Peak memory 201640 kb
Host smart-ae17fe31-28bf-4ec7-bdfc-b0ceca174b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634578481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.634578481
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1197468602
Short name T384
Test name
Test status
Simulation time 34417133393 ps
CPU time 77.09 seconds
Started Feb 29 01:16:17 PM PST 24
Finished Feb 29 01:17:35 PM PST 24
Peak memory 201152 kb
Host smart-c765c814-eee8-48fc-b585-c3117d7bb9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197468602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1197468602
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3661071398
Short name T470
Test name
Test status
Simulation time 4317258909 ps
CPU time 3.27 seconds
Started Feb 29 01:16:15 PM PST 24
Finished Feb 29 01:16:18 PM PST 24
Peak memory 201220 kb
Host smart-8fdf693c-3e1f-482b-8ac6-da21b09d90d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661071398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3661071398
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.673937356
Short name T582
Test name
Test status
Simulation time 5828324945 ps
CPU time 4.82 seconds
Started Feb 29 01:16:14 PM PST 24
Finished Feb 29 01:16:19 PM PST 24
Peak memory 201220 kb
Host smart-9c5300c7-a7b8-41e2-9d37-b06d5f705920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673937356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.673937356
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.497669969
Short name T54
Test name
Test status
Simulation time 40539978916 ps
CPU time 123.98 seconds
Started Feb 29 01:16:14 PM PST 24
Finished Feb 29 01:18:19 PM PST 24
Peak memory 210032 kb
Host smart-a147ef48-d5ec-4664-b3a1-50dfa45ac6a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497669969 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.497669969
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2660721896
Short name T388
Test name
Test status
Simulation time 501719798 ps
CPU time 1.74 seconds
Started Feb 29 01:16:35 PM PST 24
Finished Feb 29 01:16:36 PM PST 24
Peak memory 201144 kb
Host smart-de64ed13-2435-4cf0-9476-274be4ec4904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660721896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2660721896
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.637321439
Short name T287
Test name
Test status
Simulation time 330262524591 ps
CPU time 94.29 seconds
Started Feb 29 01:16:34 PM PST 24
Finished Feb 29 01:18:08 PM PST 24
Peak memory 201472 kb
Host smart-44b96cd8-3f1c-4b7c-a0ef-499f37cd78bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637321439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.637321439
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2979033667
Short name T131
Test name
Test status
Simulation time 160385797151 ps
CPU time 22.79 seconds
Started Feb 29 01:16:36 PM PST 24
Finished Feb 29 01:16:59 PM PST 24
Peak memory 201492 kb
Host smart-483a06a3-24fd-4143-b92f-2f768e40d50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979033667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2979033667
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2531846700
Short name T719
Test name
Test status
Simulation time 166023109940 ps
CPU time 396.45 seconds
Started Feb 29 01:16:14 PM PST 24
Finished Feb 29 01:22:51 PM PST 24
Peak memory 201512 kb
Host smart-de485d45-a4a1-48a1-bbeb-f4ef86ecda72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531846700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2531846700
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.4047272001
Short name T403
Test name
Test status
Simulation time 325005982722 ps
CPU time 360.94 seconds
Started Feb 29 01:16:16 PM PST 24
Finished Feb 29 01:22:18 PM PST 24
Peak memory 201396 kb
Host smart-4e94a40f-f428-493c-afd8-a872ccc449ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047272001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.4047272001
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1089092856
Short name T588
Test name
Test status
Simulation time 491091355269 ps
CPU time 168.88 seconds
Started Feb 29 01:16:16 PM PST 24
Finished Feb 29 01:19:05 PM PST 24
Peak memory 201452 kb
Host smart-6481be42-0933-46ba-86eb-222871e0e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089092856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1089092856
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3600657067
Short name T761
Test name
Test status
Simulation time 161030624139 ps
CPU time 101.17 seconds
Started Feb 29 01:16:17 PM PST 24
Finished Feb 29 01:17:58 PM PST 24
Peak memory 201436 kb
Host smart-11471e6d-986a-4bf5-b7ab-9d27923fe260
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600657067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3600657067
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1581077337
Short name T52
Test name
Test status
Simulation time 159030277765 ps
CPU time 83.76 seconds
Started Feb 29 01:16:18 PM PST 24
Finished Feb 29 01:17:42 PM PST 24
Peak memory 201600 kb
Host smart-b9c95b21-1e56-47fb-a837-ee55cf6211e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581077337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1581077337
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1396841577
Short name T420
Test name
Test status
Simulation time 75546617642 ps
CPU time 295.72 seconds
Started Feb 29 01:16:34 PM PST 24
Finished Feb 29 01:21:30 PM PST 24
Peak memory 201692 kb
Host smart-d62c916c-e200-4119-8d85-8b6d4aa26037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396841577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1396841577
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3033320095
Short name T393
Test name
Test status
Simulation time 36141093606 ps
CPU time 83.86 seconds
Started Feb 29 01:16:38 PM PST 24
Finished Feb 29 01:18:02 PM PST 24
Peak memory 201192 kb
Host smart-0926bc62-1cd3-48f8-8d35-50b16a1640c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033320095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3033320095
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4190272305
Short name T651
Test name
Test status
Simulation time 3456800669 ps
CPU time 8.32 seconds
Started Feb 29 01:16:37 PM PST 24
Finished Feb 29 01:16:45 PM PST 24
Peak memory 201244 kb
Host smart-a18deaf7-1934-4462-a45c-5160a9632cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190272305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4190272305
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1800998101
Short name T743
Test name
Test status
Simulation time 5863555845 ps
CPU time 14.29 seconds
Started Feb 29 01:16:15 PM PST 24
Finished Feb 29 01:16:30 PM PST 24
Peak memory 201184 kb
Host smart-fe695b75-d7fe-44b2-9ecd-a7b75afaab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800998101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1800998101
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.4108861435
Short name T649
Test name
Test status
Simulation time 44447316588 ps
CPU time 22.4 seconds
Started Feb 29 01:16:35 PM PST 24
Finished Feb 29 01:16:57 PM PST 24
Peak memory 201212 kb
Host smart-cc506d3c-b286-4981-a8a4-9bc44210d73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108861435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.4108861435
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3782471638
Short name T212
Test name
Test status
Simulation time 35717466529 ps
CPU time 24.54 seconds
Started Feb 29 01:16:35 PM PST 24
Finished Feb 29 01:17:00 PM PST 24
Peak memory 201504 kb
Host smart-0b4fd333-97fd-47a7-a6f4-642401e6f7fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782471638 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3782471638
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1259029462
Short name T563
Test name
Test status
Simulation time 423540463 ps
CPU time 1.04 seconds
Started Feb 29 01:16:47 PM PST 24
Finished Feb 29 01:16:49 PM PST 24
Peak memory 201124 kb
Host smart-3ae7c0d2-f2eb-479f-b7b0-2a0c24521639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259029462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1259029462
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3527430955
Short name T776
Test name
Test status
Simulation time 163297869080 ps
CPU time 26.57 seconds
Started Feb 29 01:16:39 PM PST 24
Finished Feb 29 01:17:06 PM PST 24
Peak memory 201436 kb
Host smart-c435e198-1392-42cb-9f39-7da4b04da0da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527430955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3527430955
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1898624200
Short name T133
Test name
Test status
Simulation time 331366829813 ps
CPU time 169.68 seconds
Started Feb 29 01:16:38 PM PST 24
Finished Feb 29 01:19:28 PM PST 24
Peak memory 201416 kb
Host smart-dadef393-def5-4580-a6de-6c8e72e0a40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898624200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1898624200
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2734296841
Short name T154
Test name
Test status
Simulation time 328658272553 ps
CPU time 780.19 seconds
Started Feb 29 01:16:35 PM PST 24
Finished Feb 29 01:29:36 PM PST 24
Peak memory 201440 kb
Host smart-e746c3e3-4acb-44e5-8206-4714092b5190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734296841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2734296841
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.305083382
Short name T662
Test name
Test status
Simulation time 165980310944 ps
CPU time 386.57 seconds
Started Feb 29 01:16:36 PM PST 24
Finished Feb 29 01:23:03 PM PST 24
Peak memory 201432 kb
Host smart-0a42baf5-5b72-498e-b656-5a057e8e3ca4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=305083382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.305083382
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3833515008
Short name T346
Test name
Test status
Simulation time 329580386214 ps
CPU time 793.49 seconds
Started Feb 29 01:16:35 PM PST 24
Finished Feb 29 01:29:48 PM PST 24
Peak memory 201500 kb
Host smart-dc9b932c-8a2c-45e7-803f-aa55ae326e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833515008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3833515008
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.735779160
Short name T700
Test name
Test status
Simulation time 495443756065 ps
CPU time 296.88 seconds
Started Feb 29 01:16:38 PM PST 24
Finished Feb 29 01:21:35 PM PST 24
Peak memory 201380 kb
Host smart-6e5fb88e-b35f-45d9-8a38-aaf2b3958ee3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=735779160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.735779160
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.668945261
Short name T742
Test name
Test status
Simulation time 329139781238 ps
CPU time 433.81 seconds
Started Feb 29 01:16:38 PM PST 24
Finished Feb 29 01:23:53 PM PST 24
Peak memory 201348 kb
Host smart-3ee9090b-71e4-4968-afc9-585bf2e14920
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668945261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.668945261
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2282310902
Short name T716
Test name
Test status
Simulation time 324206099752 ps
CPU time 789.65 seconds
Started Feb 29 01:16:39 PM PST 24
Finished Feb 29 01:29:48 PM PST 24
Peak memory 201448 kb
Host smart-4686e926-dce0-4852-ae6a-6d7c57a689bd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282310902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2282310902
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.2494086012
Short name T385
Test name
Test status
Simulation time 68666367120 ps
CPU time 370.79 seconds
Started Feb 29 01:16:37 PM PST 24
Finished Feb 29 01:22:48 PM PST 24
Peak memory 201656 kb
Host smart-61964974-837f-4d0a-8f9b-357ed1c6a9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494086012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.2494086012
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.207167809
Short name T520
Test name
Test status
Simulation time 46930708171 ps
CPU time 24.34 seconds
Started Feb 29 01:16:38 PM PST 24
Finished Feb 29 01:17:03 PM PST 24
Peak memory 201164 kb
Host smart-ce51372d-ccda-4c03-9451-85a1103f7347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207167809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.207167809
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3754543722
Short name T461
Test name
Test status
Simulation time 4582486923 ps
CPU time 6.81 seconds
Started Feb 29 01:16:39 PM PST 24
Finished Feb 29 01:16:45 PM PST 24
Peak memory 201164 kb
Host smart-1253fb1a-345a-4b2d-8269-ffbc00644289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754543722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3754543722
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.110713179
Short name T710
Test name
Test status
Simulation time 5991493947 ps
CPU time 3.88 seconds
Started Feb 29 01:16:35 PM PST 24
Finished Feb 29 01:16:39 PM PST 24
Peak memory 201104 kb
Host smart-d0adbe08-ec39-478f-bbc5-11f3de265dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110713179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.110713179
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3777202648
Short name T208
Test name
Test status
Simulation time 175056135792 ps
CPU time 386.48 seconds
Started Feb 29 01:16:38 PM PST 24
Finished Feb 29 01:23:05 PM PST 24
Peak memory 201444 kb
Host smart-87ef1c2b-27ee-490a-a2ba-7b4b111b4dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777202648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3777202648
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2146460932
Short name T297
Test name
Test status
Simulation time 89814516342 ps
CPU time 52.74 seconds
Started Feb 29 01:16:36 PM PST 24
Finished Feb 29 01:17:29 PM PST 24
Peak memory 209992 kb
Host smart-67126839-0e7e-415d-8c16-70ae92635205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146460932 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2146460932
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3421112446
Short name T665
Test name
Test status
Simulation time 505434501 ps
CPU time 1.2 seconds
Started Feb 29 01:16:57 PM PST 24
Finished Feb 29 01:16:59 PM PST 24
Peak memory 201136 kb
Host smart-8f30f140-7eff-4d3e-befb-a806af451cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421112446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3421112446
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2559577295
Short name T267
Test name
Test status
Simulation time 494619743218 ps
CPU time 1101.27 seconds
Started Feb 29 01:16:56 PM PST 24
Finished Feb 29 01:35:17 PM PST 24
Peak memory 201452 kb
Host smart-ba8737b3-1ffc-4ea3-839a-5321884933c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559577295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2559577295
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3104531779
Short name T181
Test name
Test status
Simulation time 496425626506 ps
CPU time 338.84 seconds
Started Feb 29 01:16:57 PM PST 24
Finished Feb 29 01:22:36 PM PST 24
Peak memory 201344 kb
Host smart-cb292db7-e49d-4cd8-9c4b-7d755462b4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104531779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3104531779
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.160242021
Short name T306
Test name
Test status
Simulation time 328789999444 ps
CPU time 746.18 seconds
Started Feb 29 01:16:38 PM PST 24
Finished Feb 29 01:29:05 PM PST 24
Peak memory 201400 kb
Host smart-d832d127-18cf-462a-a5c1-3cde3e698975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160242021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.160242021
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4097307926
Short name T774
Test name
Test status
Simulation time 492758025578 ps
CPU time 1080.32 seconds
Started Feb 29 01:16:40 PM PST 24
Finished Feb 29 01:34:41 PM PST 24
Peak memory 201348 kb
Host smart-3f499b23-9094-4172-9df3-0b694ac93bb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097307926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.4097307926
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1925494933
Short name T263
Test name
Test status
Simulation time 489417594746 ps
CPU time 263.26 seconds
Started Feb 29 01:16:39 PM PST 24
Finished Feb 29 01:21:03 PM PST 24
Peak memory 201308 kb
Host smart-3762972b-99d7-462b-abfd-48877ad2a296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925494933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1925494933
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3512959232
Short name T661
Test name
Test status
Simulation time 490285359141 ps
CPU time 82.56 seconds
Started Feb 29 01:16:40 PM PST 24
Finished Feb 29 01:18:03 PM PST 24
Peak memory 201300 kb
Host smart-438c9098-f75e-4b6a-8cf1-3375c9e0da7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512959232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3512959232
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1467229669
Short name T259
Test name
Test status
Simulation time 167077254409 ps
CPU time 393.59 seconds
Started Feb 29 01:16:57 PM PST 24
Finished Feb 29 01:23:31 PM PST 24
Peak memory 201412 kb
Host smart-ac466c42-783b-40ec-9141-32be01427209
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467229669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1467229669
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2478935427
Short name T624
Test name
Test status
Simulation time 325875181661 ps
CPU time 390.4 seconds
Started Feb 29 01:16:55 PM PST 24
Finished Feb 29 01:23:26 PM PST 24
Peak memory 201400 kb
Host smart-ceab653c-73c9-40c1-a6b1-82750bf2cdc2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478935427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2478935427
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3439713557
Short name T775
Test name
Test status
Simulation time 95864108286 ps
CPU time 277.68 seconds
Started Feb 29 01:16:57 PM PST 24
Finished Feb 29 01:21:34 PM PST 24
Peak memory 201652 kb
Host smart-51685c93-c74f-4cdb-b7f1-e188b1d9706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439713557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3439713557
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2375099776
Short name T650
Test name
Test status
Simulation time 42614994479 ps
CPU time 24.49 seconds
Started Feb 29 01:16:56 PM PST 24
Finished Feb 29 01:17:20 PM PST 24
Peak memory 201196 kb
Host smart-a8f909ae-bb66-4b99-a730-62a95fa2e3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375099776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2375099776
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.837664548
Short name T119
Test name
Test status
Simulation time 4327220482 ps
CPU time 1.77 seconds
Started Feb 29 01:16:56 PM PST 24
Finished Feb 29 01:16:58 PM PST 24
Peak memory 201148 kb
Host smart-3fa3aaee-6a87-464c-93b9-f623ca9f7187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837664548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.837664548
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1933848
Short name T144
Test name
Test status
Simulation time 5960909753 ps
CPU time 7.87 seconds
Started Feb 29 01:16:41 PM PST 24
Finished Feb 29 01:16:49 PM PST 24
Peak memory 201140 kb
Host smart-2d00e830-50ff-4e6a-a64c-9f95083a32f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1933848
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3668067966
Short name T236
Test name
Test status
Simulation time 181955142792 ps
CPU time 381.25 seconds
Started Feb 29 01:16:57 PM PST 24
Finished Feb 29 01:23:18 PM PST 24
Peak memory 201284 kb
Host smart-d1afe7ea-6484-46a4-a3aa-ed0f9dc7a72e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668067966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3668067966
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.381425067
Short name T606
Test name
Test status
Simulation time 68505266861 ps
CPU time 64.21 seconds
Started Feb 29 01:16:55 PM PST 24
Finished Feb 29 01:18:00 PM PST 24
Peak memory 210476 kb
Host smart-57b0d475-4310-4086-b654-873e1e0ae6bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381425067 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.381425067
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3591296707
Short name T701
Test name
Test status
Simulation time 387838563 ps
CPU time 0.76 seconds
Started Feb 29 01:17:01 PM PST 24
Finished Feb 29 01:17:02 PM PST 24
Peak memory 201140 kb
Host smart-654217b7-8183-4804-8610-1471c7095b72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591296707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3591296707
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1283419064
Short name T275
Test name
Test status
Simulation time 503791302756 ps
CPU time 115.06 seconds
Started Feb 29 01:16:58 PM PST 24
Finished Feb 29 01:18:54 PM PST 24
Peak memory 201348 kb
Host smart-f89d319a-d205-49d4-8c02-f9527c0d1ec6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283419064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1283419064
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.137811458
Short name T293
Test name
Test status
Simulation time 162997548943 ps
CPU time 356.7 seconds
Started Feb 29 01:16:55 PM PST 24
Finished Feb 29 01:22:53 PM PST 24
Peak memory 201468 kb
Host smart-2aee0557-7bbe-4827-91e2-94f69c3c7abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137811458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.137811458
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.6808410
Short name T123
Test name
Test status
Simulation time 494390300948 ps
CPU time 267.52 seconds
Started Feb 29 01:16:57 PM PST 24
Finished Feb 29 01:21:24 PM PST 24
Peak memory 201472 kb
Host smart-89803c58-ceb0-4367-9872-2336f3b4e4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6808410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.6808410
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3223949512
Short name T475
Test name
Test status
Simulation time 498851996600 ps
CPU time 569.65 seconds
Started Feb 29 01:16:56 PM PST 24
Finished Feb 29 01:26:26 PM PST 24
Peak memory 201392 kb
Host smart-5b83a341-5798-45fe-b591-728fdd844ce9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223949512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3223949512
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.409862757
Short name T130
Test name
Test status
Simulation time 327843181461 ps
CPU time 405.77 seconds
Started Feb 29 01:16:56 PM PST 24
Finished Feb 29 01:23:42 PM PST 24
Peak memory 201460 kb
Host smart-fb65408f-f603-4063-9d81-20148fc83222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409862757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.409862757
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3573638966
Short name T575
Test name
Test status
Simulation time 495090050380 ps
CPU time 1163.87 seconds
Started Feb 29 01:17:09 PM PST 24
Finished Feb 29 01:36:33 PM PST 24
Peak memory 201436 kb
Host smart-c3696efd-a03c-4cb4-a6ee-f445abbde239
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573638966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3573638966
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.3823214635
Short name T720
Test name
Test status
Simulation time 161293313049 ps
CPU time 366.51 seconds
Started Feb 29 01:16:58 PM PST 24
Finished Feb 29 01:23:05 PM PST 24
Peak memory 201412 kb
Host smart-9e5bbf44-bba6-4779-b475-ad16070cce1b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823214635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.3823214635
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.4281853493
Short name T450
Test name
Test status
Simulation time 165359870858 ps
CPU time 196.03 seconds
Started Feb 29 01:16:55 PM PST 24
Finished Feb 29 01:20:11 PM PST 24
Peak memory 201484 kb
Host smart-135a4f12-f2f9-493d-bdce-e6887a88eaab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281853493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.4281853493
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3391570770
Short name T22
Test name
Test status
Simulation time 124519579192 ps
CPU time 474.51 seconds
Started Feb 29 01:16:55 PM PST 24
Finished Feb 29 01:24:50 PM PST 24
Peak memory 201732 kb
Host smart-3f1aec7d-ab65-44c5-8380-1974d9ecfa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391570770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3391570770
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3563247448
Short name T741
Test name
Test status
Simulation time 41483182091 ps
CPU time 89.47 seconds
Started Feb 29 01:16:54 PM PST 24
Finished Feb 29 01:18:24 PM PST 24
Peak memory 201252 kb
Host smart-e7f68593-a950-471a-b9a5-962e786ccb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563247448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3563247448
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1053917671
Short name T143
Test name
Test status
Simulation time 4986978138 ps
CPU time 11.86 seconds
Started Feb 29 01:16:55 PM PST 24
Finished Feb 29 01:17:07 PM PST 24
Peak memory 201404 kb
Host smart-aff8824c-b8ab-47ad-a8de-6f1d2618ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053917671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1053917671
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.52741896
Short name T177
Test name
Test status
Simulation time 5964950838 ps
CPU time 2.41 seconds
Started Feb 29 01:16:54 PM PST 24
Finished Feb 29 01:16:57 PM PST 24
Peak memory 201052 kb
Host smart-43a0c665-5ce7-42bd-a577-68b135bda82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52741896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.52741896
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2120483190
Short name T122
Test name
Test status
Simulation time 330114327628 ps
CPU time 672.2 seconds
Started Feb 29 01:16:55 PM PST 24
Finished Feb 29 01:28:08 PM PST 24
Peak memory 201392 kb
Host smart-e989eba8-44d2-4ac9-b82c-eb9cfced16b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120483190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2120483190
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1937518791
Short name T65
Test name
Test status
Simulation time 428160737 ps
CPU time 1.22 seconds
Started Feb 29 01:17:02 PM PST 24
Finished Feb 29 01:17:03 PM PST 24
Peak memory 201056 kb
Host smart-24969ea7-d8f1-4669-95dc-185c8a30c4ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937518791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1937518791
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2907931967
Short name T255
Test name
Test status
Simulation time 329280536701 ps
CPU time 696.67 seconds
Started Feb 29 01:17:03 PM PST 24
Finished Feb 29 01:28:39 PM PST 24
Peak memory 201512 kb
Host smart-f13b4971-df6c-462b-a531-cd409693cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907931967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2907931967
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3567625962
Short name T291
Test name
Test status
Simulation time 161523950910 ps
CPU time 105.05 seconds
Started Feb 29 01:16:55 PM PST 24
Finished Feb 29 01:18:41 PM PST 24
Peak memory 201460 kb
Host smart-c4168997-8827-47ec-b6a3-87f94802f2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567625962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3567625962
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.329821878
Short name T419
Test name
Test status
Simulation time 486106361656 ps
CPU time 464.49 seconds
Started Feb 29 01:16:56 PM PST 24
Finished Feb 29 01:24:41 PM PST 24
Peak memory 201452 kb
Host smart-fc72f0de-49f6-4776-91ac-8502235fb1d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=329821878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.329821878
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1281819503
Short name T229
Test name
Test status
Simulation time 481496345150 ps
CPU time 1021.58 seconds
Started Feb 29 01:16:54 PM PST 24
Finished Feb 29 01:33:56 PM PST 24
Peak memory 201500 kb
Host smart-f993f681-c48e-4589-8e4f-c2b3e5287bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281819503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1281819503
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1225673316
Short name T412
Test name
Test status
Simulation time 327127361995 ps
CPU time 201.97 seconds
Started Feb 29 01:16:56 PM PST 24
Finished Feb 29 01:20:19 PM PST 24
Peak memory 201456 kb
Host smart-d79e8dbf-c0c2-48c3-a222-821b031c9f84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225673316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1225673316
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3645277552
Short name T637
Test name
Test status
Simulation time 162590338254 ps
CPU time 99.17 seconds
Started Feb 29 01:17:13 PM PST 24
Finished Feb 29 01:18:53 PM PST 24
Peak memory 201380 kb
Host smart-bb8e5060-8eaf-415c-9bb6-f80ae753f208
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645277552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3645277552
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.365553664
Short name T534
Test name
Test status
Simulation time 493663823497 ps
CPU time 624.66 seconds
Started Feb 29 01:17:04 PM PST 24
Finished Feb 29 01:27:29 PM PST 24
Peak memory 201408 kb
Host smart-78bae147-97a1-4648-a023-4d0c875d1969
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365553664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.365553664
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3087726865
Short name T164
Test name
Test status
Simulation time 29684650862 ps
CPU time 32.53 seconds
Started Feb 29 01:17:01 PM PST 24
Finished Feb 29 01:17:34 PM PST 24
Peak memory 201176 kb
Host smart-e0f9f67c-b2e4-4b22-a075-b35983b2e537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087726865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3087726865
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.165049322
Short name T567
Test name
Test status
Simulation time 3107633803 ps
CPU time 8.38 seconds
Started Feb 29 01:17:04 PM PST 24
Finished Feb 29 01:17:12 PM PST 24
Peak memory 201148 kb
Host smart-d5dfdfeb-cebf-4761-99cc-b59b20b5ebe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165049322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.165049322
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4014121217
Short name T166
Test name
Test status
Simulation time 5781088833 ps
CPU time 4.25 seconds
Started Feb 29 01:16:58 PM PST 24
Finished Feb 29 01:17:03 PM PST 24
Peak memory 201108 kb
Host smart-85fd9ef6-d99f-4111-8b20-dfafb2bb33eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014121217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4014121217
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3828156927
Short name T362
Test name
Test status
Simulation time 187721621269 ps
CPU time 606.33 seconds
Started Feb 29 01:17:04 PM PST 24
Finished Feb 29 01:27:11 PM PST 24
Peak memory 201708 kb
Host smart-3c9ba70f-3133-442f-a14c-1afbe3554897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828156927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3828156927
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3566168103
Short name T355
Test name
Test status
Simulation time 43922053345 ps
CPU time 44.26 seconds
Started Feb 29 01:17:13 PM PST 24
Finished Feb 29 01:17:57 PM PST 24
Peak memory 210060 kb
Host smart-e7a04e1c-ddf6-45dd-aba4-eab35c47bf37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566168103 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3566168103
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.874480660
Short name T64
Test name
Test status
Simulation time 530206192 ps
CPU time 0.71 seconds
Started Feb 29 01:12:45 PM PST 24
Finished Feb 29 01:12:46 PM PST 24
Peak memory 201136 kb
Host smart-d2586256-1066-4848-8c25-4b5347be6bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874480660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.874480660
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3295337934
Short name T157
Test name
Test status
Simulation time 329048702537 ps
CPU time 198.56 seconds
Started Feb 29 01:12:44 PM PST 24
Finished Feb 29 01:16:02 PM PST 24
Peak memory 201364 kb
Host smart-525c87b8-f164-4e93-838c-5401b5230c92
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295337934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3295337934
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.287982403
Short name T531
Test name
Test status
Simulation time 329442638116 ps
CPU time 230.08 seconds
Started Feb 29 01:12:45 PM PST 24
Finished Feb 29 01:16:35 PM PST 24
Peak memory 201456 kb
Host smart-174bd89a-c36b-4d6d-81c9-10207f697cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287982403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.287982403
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1805255868
Short name T344
Test name
Test status
Simulation time 499404647229 ps
CPU time 1219.63 seconds
Started Feb 29 01:12:45 PM PST 24
Finished Feb 29 01:33:05 PM PST 24
Peak memory 201476 kb
Host smart-cee5adbe-b2b7-4010-b987-7be10f8f01cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805255868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1805255868
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1665432717
Short name T451
Test name
Test status
Simulation time 322255037622 ps
CPU time 178.76 seconds
Started Feb 29 01:12:44 PM PST 24
Finished Feb 29 01:15:43 PM PST 24
Peak memory 201436 kb
Host smart-adcfc8b0-0ea2-4c37-90ef-297bf72f21cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665432717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1665432717
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1662347885
Short name T128
Test name
Test status
Simulation time 324695198674 ps
CPU time 765.85 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:25:32 PM PST 24
Peak memory 201308 kb
Host smart-df9df487-0eb6-488b-8b68-3e38bccfb9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662347885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1662347885
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1970542535
Short name T585
Test name
Test status
Simulation time 162471738899 ps
CPU time 105.82 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:14:33 PM PST 24
Peak memory 201532 kb
Host smart-f0ba0a0e-675d-4b7f-80a8-36b90fb266f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970542535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1970542535
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2994792594
Short name T677
Test name
Test status
Simulation time 165191972049 ps
CPU time 305.35 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:17:52 PM PST 24
Peak memory 201252 kb
Host smart-69c7a6bd-207a-4eda-8695-59aa69383e95
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994792594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2994792594
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2579568783
Short name T604
Test name
Test status
Simulation time 504734404329 ps
CPU time 1097.39 seconds
Started Feb 29 01:12:49 PM PST 24
Finished Feb 29 01:31:06 PM PST 24
Peak memory 201412 kb
Host smart-079d34fa-f22b-4f5e-badc-9fd4e1219ff7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579568783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2579568783
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2117497679
Short name T9
Test name
Test status
Simulation time 99840270789 ps
CPU time 321.24 seconds
Started Feb 29 01:12:45 PM PST 24
Finished Feb 29 01:18:06 PM PST 24
Peak memory 201696 kb
Host smart-f07dfa14-8ce2-484d-b2e6-1e522a17181b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117497679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2117497679
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1314402250
Short name T709
Test name
Test status
Simulation time 24049583186 ps
CPU time 16.42 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:13:03 PM PST 24
Peak memory 201160 kb
Host smart-770b6d86-efe5-4617-ade9-21098ab5dbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314402250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1314402250
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2506280099
Short name T766
Test name
Test status
Simulation time 5043867768 ps
CPU time 13.54 seconds
Started Feb 29 01:12:44 PM PST 24
Finished Feb 29 01:12:58 PM PST 24
Peak memory 201216 kb
Host smart-665a3236-1514-46b8-b1df-a2070dc9105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506280099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2506280099
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3436938339
Short name T488
Test name
Test status
Simulation time 6138646997 ps
CPU time 5.58 seconds
Started Feb 29 01:12:45 PM PST 24
Finished Feb 29 01:12:51 PM PST 24
Peak memory 201096 kb
Host smart-c33cec75-0bd6-4151-b0fa-1bcb51fdf830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436938339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3436938339
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.18092878
Short name T244
Test name
Test status
Simulation time 493469611915 ps
CPU time 196.84 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:16:03 PM PST 24
Peak memory 201432 kb
Host smart-0d03ffc6-336e-4da9-9509-bc035bd556c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18092878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.18092878
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.2209436198
Short name T717
Test name
Test status
Simulation time 252708869052 ps
CPU time 169.73 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:15:37 PM PST 24
Peak memory 210084 kb
Host smart-9e7ccf4b-8d05-4c1a-8265-72ca12dc27a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209436198 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.2209436198
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3177836252
Short name T438
Test name
Test status
Simulation time 311244043 ps
CPU time 1.4 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:12:48 PM PST 24
Peak memory 201188 kb
Host smart-f7bbd169-5ff1-4a7c-9a30-a9dc31f3cdaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177836252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3177836252
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2236027356
Short name T192
Test name
Test status
Simulation time 339321965985 ps
CPU time 180.02 seconds
Started Feb 29 01:12:43 PM PST 24
Finished Feb 29 01:15:43 PM PST 24
Peak memory 201332 kb
Host smart-78a3475a-3f65-4dc7-92b9-aeefaa6cff01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236027356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2236027356
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2715909374
Short name T235
Test name
Test status
Simulation time 175652504605 ps
CPU time 211.39 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:16:18 PM PST 24
Peak memory 201340 kb
Host smart-3bdc5122-1a74-4655-bc30-0ad68f1f155d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715909374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2715909374
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.211312775
Short name T740
Test name
Test status
Simulation time 491889155856 ps
CPU time 1196.82 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:32:43 PM PST 24
Peak memory 201392 kb
Host smart-5b2d82af-9df5-463f-bac6-73a71daaf18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211312775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.211312775
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1996194435
Short name T760
Test name
Test status
Simulation time 326137932599 ps
CPU time 165.65 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:15:33 PM PST 24
Peak memory 201432 kb
Host smart-e2d184ff-23a7-4c7b-8e42-37b56ee87851
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996194435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1996194435
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.393787816
Short name T512
Test name
Test status
Simulation time 492320306280 ps
CPU time 396.45 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:19:22 PM PST 24
Peak memory 201456 kb
Host smart-d6efc52e-95a8-4bcc-b4f8-bc3bf03e3a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393787816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.393787816
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1713625369
Short name T59
Test name
Test status
Simulation time 322816076239 ps
CPU time 115.16 seconds
Started Feb 29 01:12:49 PM PST 24
Finished Feb 29 01:14:44 PM PST 24
Peak memory 201384 kb
Host smart-6408de9c-3632-427f-aef7-33ff73dc9800
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713625369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1713625369
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2621422945
Short name T11
Test name
Test status
Simulation time 529656602427 ps
CPU time 323.97 seconds
Started Feb 29 01:12:44 PM PST 24
Finished Feb 29 01:18:09 PM PST 24
Peak memory 201392 kb
Host smart-74e96d25-e628-4d03-8aff-647e12c54796
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621422945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2621422945
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.173868421
Short name T515
Test name
Test status
Simulation time 326567835208 ps
CPU time 370.31 seconds
Started Feb 29 01:12:48 PM PST 24
Finished Feb 29 01:18:59 PM PST 24
Peak memory 201456 kb
Host smart-41da7d1c-4c28-4ab9-b8df-b8f8a002c51f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173868421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.173868421
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3904572094
Short name T409
Test name
Test status
Simulation time 66036243087 ps
CPU time 384.25 seconds
Started Feb 29 01:12:48 PM PST 24
Finished Feb 29 01:19:13 PM PST 24
Peak memory 201676 kb
Host smart-21b8adbe-f21c-4c4e-8f54-f6a96a44102c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904572094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3904572094
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3767324984
Short name T455
Test name
Test status
Simulation time 23184394748 ps
CPU time 50.22 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:13:37 PM PST 24
Peak memory 201064 kb
Host smart-04f72225-6b3e-4cb0-9e64-e5aefec1da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767324984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3767324984
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2726047884
Short name T184
Test name
Test status
Simulation time 4572842207 ps
CPU time 6.67 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:12:54 PM PST 24
Peak memory 201196 kb
Host smart-964e079d-6d7c-45c3-977c-bbc7f4e6c55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726047884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2726047884
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2608093188
Short name T499
Test name
Test status
Simulation time 5743995338 ps
CPU time 14.92 seconds
Started Feb 29 01:12:43 PM PST 24
Finished Feb 29 01:12:58 PM PST 24
Peak memory 201184 kb
Host smart-66dec511-8fee-4ce4-924f-2e4bb88bef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608093188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2608093188
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.355293284
Short name T535
Test name
Test status
Simulation time 199046045875 ps
CPU time 129.42 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:14:56 PM PST 24
Peak memory 210028 kb
Host smart-08737bfa-a75f-4c19-bb6c-a389a2f686f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355293284 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.355293284
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.244991619
Short name T398
Test name
Test status
Simulation time 277895831 ps
CPU time 1.23 seconds
Started Feb 29 01:13:01 PM PST 24
Finished Feb 29 01:13:02 PM PST 24
Peak memory 201140 kb
Host smart-4280fe82-8938-4537-b2f0-90c5500bbb11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244991619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.244991619
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1063412251
Short name T274
Test name
Test status
Simulation time 511797931020 ps
CPU time 164.6 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:15:32 PM PST 24
Peak memory 201376 kb
Host smart-ad6a511e-4b44-4d0f-9f1a-375f02ac67e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063412251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1063412251
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2360951778
Short name T622
Test name
Test status
Simulation time 493327543460 ps
CPU time 1120.11 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:31:26 PM PST 24
Peak memory 201432 kb
Host smart-821b5a50-0636-4c95-8362-e4e487bc0cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360951778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2360951778
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2793761733
Short name T605
Test name
Test status
Simulation time 326742105728 ps
CPU time 140.25 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:15:06 PM PST 24
Peak memory 201456 kb
Host smart-4f13195a-6abe-44d4-ab59-95cdcc27b42c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793761733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2793761733
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.258393785
Short name T565
Test name
Test status
Simulation time 161685724516 ps
CPU time 372.44 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:19:00 PM PST 24
Peak memory 201408 kb
Host smart-a0c98c98-778b-459b-ab4b-3b7cf1f482fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258393785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.258393785
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3406713939
Short name T5
Test name
Test status
Simulation time 494519364873 ps
CPU time 600.03 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:22:46 PM PST 24
Peak memory 201392 kb
Host smart-cd7f9616-26e2-4b00-8629-2b694fdf5a03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406713939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3406713939
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.936759799
Short name T300
Test name
Test status
Simulation time 161367347345 ps
CPU time 355.64 seconds
Started Feb 29 01:12:46 PM PST 24
Finished Feb 29 01:18:41 PM PST 24
Peak memory 201472 kb
Host smart-c744fac8-e662-4607-880e-c5d7dd7e9207
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936759799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_w
akeup.936759799
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2280244981
Short name T611
Test name
Test status
Simulation time 331269102691 ps
CPU time 206.54 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:16:14 PM PST 24
Peak memory 201444 kb
Host smart-070ce707-a960-4fb1-9845-c6a6a3baec86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280244981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2280244981
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.984078000
Short name T71
Test name
Test status
Simulation time 125527410635 ps
CPU time 669.93 seconds
Started Feb 29 01:12:47 PM PST 24
Finished Feb 29 01:23:57 PM PST 24
Peak memory 201832 kb
Host smart-6d666673-c6eb-4ba7-8972-c7294ca61445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984078000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.984078000
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2477583465
Short name T667
Test name
Test status
Simulation time 28716401893 ps
CPU time 16.99 seconds
Started Feb 29 01:12:48 PM PST 24
Finished Feb 29 01:13:05 PM PST 24
Peak memory 201160 kb
Host smart-e06cf879-107d-4f04-83d1-47ee9a5720e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477583465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2477583465
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3219263933
Short name T683
Test name
Test status
Simulation time 3963418256 ps
CPU time 10.54 seconds
Started Feb 29 01:12:48 PM PST 24
Finished Feb 29 01:12:59 PM PST 24
Peak memory 201144 kb
Host smart-c8adb7e6-7176-45da-a108-2ce596e07837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219263933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3219263933
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1919045960
Short name T553
Test name
Test status
Simulation time 5616999939 ps
CPU time 5.71 seconds
Started Feb 29 01:12:49 PM PST 24
Finished Feb 29 01:12:54 PM PST 24
Peak memory 201148 kb
Host smart-ff10419d-208b-4b87-a104-5f2a5f226bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919045960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1919045960
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.47940354
Short name T351
Test name
Test status
Simulation time 165286850147 ps
CPU time 95.52 seconds
Started Feb 29 01:13:00 PM PST 24
Finished Feb 29 01:14:36 PM PST 24
Peak memory 201220 kb
Host smart-638e0ae5-f15f-4ee2-9d47-eaadce43bab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47940354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.47940354
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2742775596
Short name T55
Test name
Test status
Simulation time 162995743501 ps
CPU time 81.6 seconds
Started Feb 29 01:13:02 PM PST 24
Finished Feb 29 01:14:24 PM PST 24
Peak memory 202396 kb
Host smart-7add16d5-4ca2-4a9d-9325-31f0f32a8e9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742775596 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2742775596
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2368216172
Short name T674
Test name
Test status
Simulation time 360211229 ps
CPU time 0.83 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:13:04 PM PST 24
Peak memory 201140 kb
Host smart-41a563bc-94de-4ad4-95b8-bf5693e8c3d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368216172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2368216172
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.4099711981
Short name T550
Test name
Test status
Simulation time 182124321587 ps
CPU time 381.72 seconds
Started Feb 29 01:13:02 PM PST 24
Finished Feb 29 01:19:23 PM PST 24
Peak memory 201368 kb
Host smart-aa8d82f4-4a51-4a49-9241-e0f3d3faf012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099711981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.4099711981
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2801514304
Short name T318
Test name
Test status
Simulation time 335973227284 ps
CPU time 793.28 seconds
Started Feb 29 01:12:59 PM PST 24
Finished Feb 29 01:26:13 PM PST 24
Peak memory 201368 kb
Host smart-55f0835a-e2da-4963-a1a1-701737e751e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801514304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2801514304
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1175302788
Short name T200
Test name
Test status
Simulation time 488597576102 ps
CPU time 264.3 seconds
Started Feb 29 01:12:59 PM PST 24
Finished Feb 29 01:17:24 PM PST 24
Peak memory 201360 kb
Host smart-0f7b86ba-a78e-49ee-ba9f-2db49dc8dac9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175302788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1175302788
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3355190428
Short name T323
Test name
Test status
Simulation time 334861490071 ps
CPU time 364.52 seconds
Started Feb 29 01:13:00 PM PST 24
Finished Feb 29 01:19:05 PM PST 24
Peak memory 201396 kb
Host smart-3550dbb5-d623-4cfc-ac2f-c224ce822bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355190428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3355190428
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3191166547
Short name T482
Test name
Test status
Simulation time 160684629385 ps
CPU time 88.48 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:14:33 PM PST 24
Peak memory 201244 kb
Host smart-faa13120-e0a6-4591-80fd-f81be4e6f06a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191166547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3191166547
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.660504772
Short name T234
Test name
Test status
Simulation time 164554770532 ps
CPU time 70.66 seconds
Started Feb 29 01:13:01 PM PST 24
Finished Feb 29 01:14:11 PM PST 24
Peak memory 201360 kb
Host smart-5ef47595-605b-4b25-8baf-940fce52aee5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660504772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.660504772
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.240788434
Short name T688
Test name
Test status
Simulation time 159384849622 ps
CPU time 58.87 seconds
Started Feb 29 01:13:01 PM PST 24
Finished Feb 29 01:14:00 PM PST 24
Peak memory 201372 kb
Host smart-54f8ebb3-a739-4757-83db-9d5f5a86f7a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240788434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.240788434
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.282105402
Short name T416
Test name
Test status
Simulation time 53832237435 ps
CPU time 203.06 seconds
Started Feb 29 01:13:02 PM PST 24
Finished Feb 29 01:16:25 PM PST 24
Peak memory 201700 kb
Host smart-4a8a72c6-eb69-40e9-aa67-082b9dbd647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282105402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.282105402
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1683655934
Short name T529
Test name
Test status
Simulation time 22439374687 ps
CPU time 25.04 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:13:28 PM PST 24
Peak memory 201200 kb
Host smart-81721503-986b-4370-8784-8f6c906ee124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683655934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1683655934
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3843650319
Short name T668
Test name
Test status
Simulation time 5361491026 ps
CPU time 2.77 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:13:06 PM PST 24
Peak memory 201208 kb
Host smart-4cbc3aa5-0def-46eb-9e57-3b7f1cc1609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843650319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3843650319
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3270499635
Short name T603
Test name
Test status
Simulation time 5524477716 ps
CPU time 4.42 seconds
Started Feb 29 01:13:00 PM PST 24
Finished Feb 29 01:13:05 PM PST 24
Peak memory 201196 kb
Host smart-3eca863f-2194-4a9a-a8dd-96b991b04b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270499635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3270499635
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3107054075
Short name T639
Test name
Test status
Simulation time 43669120951 ps
CPU time 25.06 seconds
Started Feb 29 01:13:00 PM PST 24
Finished Feb 29 01:13:26 PM PST 24
Peak memory 201056 kb
Host smart-ae655b03-a2ef-4b2b-a83a-624d90e1887e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107054075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3107054075
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2647849655
Short name T204
Test name
Test status
Simulation time 53543330817 ps
CPU time 157.14 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:15:41 PM PST 24
Peak memory 218192 kb
Host smart-e9d481a1-5357-4570-ab96-ea03fdd8a392
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647849655 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2647849655
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1208181286
Short name T646
Test name
Test status
Simulation time 385178411 ps
CPU time 0.84 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:13:08 PM PST 24
Peak memory 201040 kb
Host smart-b496a0df-fd09-46de-b419-d2537b8eb2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208181286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1208181286
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.434894788
Short name T289
Test name
Test status
Simulation time 162293560791 ps
CPU time 195.1 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:16:19 PM PST 24
Peak memory 201452 kb
Host smart-4a5f9f22-e62d-4eea-b5c6-b38ce22aeeda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434894788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.434894788
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3177403864
Short name T296
Test name
Test status
Simulation time 490070843112 ps
CPU time 497.24 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:21:24 PM PST 24
Peak memory 201480 kb
Host smart-b86c5ed3-5347-415f-9e35-49ef385f2672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177403864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3177403864
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1228058266
Short name T715
Test name
Test status
Simulation time 162385813542 ps
CPU time 48.26 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:13:51 PM PST 24
Peak memory 201448 kb
Host smart-ad01b0fd-5399-433e-ad77-f55453bc83b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228058266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1228058266
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3369959112
Short name T557
Test name
Test status
Simulation time 484300405998 ps
CPU time 221.8 seconds
Started Feb 29 01:13:03 PM PST 24
Finished Feb 29 01:16:45 PM PST 24
Peak memory 201500 kb
Host smart-2b5d7739-7045-4a20-a1a9-6b3ab0acb25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369959112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3369959112
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1341214576
Short name T643
Test name
Test status
Simulation time 324086154266 ps
CPU time 753.62 seconds
Started Feb 29 01:13:02 PM PST 24
Finished Feb 29 01:25:36 PM PST 24
Peak memory 201504 kb
Host smart-a880d0bb-371f-436c-b0be-e0b4415df185
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341214576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1341214576
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3613107356
Short name T616
Test name
Test status
Simulation time 163488275807 ps
CPU time 43.11 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:13:47 PM PST 24
Peak memory 201436 kb
Host smart-efcc9908-4ac8-4765-b6ec-e807692badc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613107356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3613107356
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2440681058
Short name T375
Test name
Test status
Simulation time 491352526771 ps
CPU time 301.18 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:18:05 PM PST 24
Peak memory 201500 kb
Host smart-575bd56f-25d4-4dc9-b085-17109f7cfe72
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440681058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2440681058
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2101109093
Short name T367
Test name
Test status
Simulation time 131627684050 ps
CPU time 551.59 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:22:16 PM PST 24
Peak memory 201764 kb
Host smart-f53ca2b2-1621-4eb1-ad07-c77d244c9b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101109093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2101109093
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4242582657
Short name T621
Test name
Test status
Simulation time 41471307251 ps
CPU time 80.68 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:14:25 PM PST 24
Peak memory 201404 kb
Host smart-33dae973-aaf1-4d5a-9d56-dc10d6701918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242582657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4242582657
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4065030793
Short name T446
Test name
Test status
Simulation time 3207020192 ps
CPU time 7.85 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:13:12 PM PST 24
Peak memory 201080 kb
Host smart-c49f428c-55f3-488e-89d3-c69f2f7cf3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065030793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4065030793
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.4102663523
Short name T564
Test name
Test status
Simulation time 5866622020 ps
CPU time 14.12 seconds
Started Feb 29 01:13:01 PM PST 24
Finished Feb 29 01:13:15 PM PST 24
Peak memory 201188 kb
Host smart-740ef46e-5cb4-4742-8e3e-b8747e8748bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102663523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.4102663523
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2512319461
Short name T371
Test name
Test status
Simulation time 204114718553 ps
CPU time 423.89 seconds
Started Feb 29 01:13:07 PM PST 24
Finished Feb 29 01:20:11 PM PST 24
Peak memory 201668 kb
Host smart-e3f971e6-86bf-4419-9147-c472c23ce708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512319461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2512319461
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2791522508
Short name T57
Test name
Test status
Simulation time 107626283278 ps
CPU time 65.56 seconds
Started Feb 29 01:13:04 PM PST 24
Finished Feb 29 01:14:09 PM PST 24
Peak memory 210072 kb
Host smart-b1f023b2-32ed-42a4-a296-3b687d40fb18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791522508 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2791522508
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%