Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6780	1			T2	20		T8	93		T21	8
testmodes[AdcCtrlTestmodeNormal]	5621	1			T1	3		T3	1		T4	3
testmodes[AdcCtrlTestmodeLowpower]	5734	1			T5	3		T8	25		T10	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3625	1			T2	19		T8	65		T21	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1737	1			T8	16		T21	2		T144	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1301	1			T8	12		T22	15		T25	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1736	1			T8	20		T21	3		T144	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2122	1			T1	2		T4	2		T8	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1437	1			T8	6		T22	13		T25	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1306	1			T8	8		T22	11		T25	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1437	1			T8	9		T22	17		T17	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2743	1			T5	2		T8	7		T10	2