Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22488

1

T1

2

T2

20

T4

6

auto[ADC_CTRL_FILTER_COND_OUT]

3404

1

T1

1

T3

29

T4

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19908

1

T1

1

T2

20

T4

3

auto[1]

5984

1

T1

2

T3

29

T4

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	393	1			T8	3		T22	4		T25	1
values[0]	1	1			T218	1		-	-		-	-
values[1]	588	1			T4	3		T6	15		T7	1
values[2]	2735	1			T1	1		T5	32		T9	20
values[3]	642	1			T1	1		T18	11		T155	14
values[4]	659	1			T39	1		T152	1		T169	9
values[5]	777	1			T3	29		T9	5		T47	1
values[6]	761	1			T47	1		T17	16		T146	18
values[7]	714	1			T4	4		T168	1		T17	21
values[8]	684	1			T1	1		T8	8		T9	1
values[9]	1065	1			T4	3		T16	28		T146	1
minimum	16873	1			T2	20		T8	153		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	791	1			T4	3		T6	15		T7	1
values[1]	2703	1			T1	2		T5	32		T9	20
values[2]	594	1			T18	11		T155	14		T148	1
values[3]	700	1			T149	3		T39	1		T152	1
values[4]	866	1			T9	5		T47	2		T17	16
values[5]	807	1			T3	29		T168	1		T17	21
values[6]	532	1			T1	1		T4	4		T8	3
values[7]	692	1			T8	5		T9	1		T149	16
values[8]	840	1			T4	3		T16	28		T146	1
values[9]	110	1			T149	5		T151	1		T39	4
minimum	17257	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T7	1		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	8		T219	1		T154	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T1	1		T5	32		T10	32
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	1		T9	1		T157	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T18	11		T148	1		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T155	14		T220	14		T72	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T149	3		T152	1		T13	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	1		T14	3		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T146	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T47	2		T17	14		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T168	1		T198	18		T169	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	14		T17	10		T18	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T8	2		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	1		T62	1		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T8	3		T9	1		T222	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T149	16		T151	1		T38	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	1		T16	14		T147	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T146	1		T19	5		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T149	5		T151	1		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T39	2		T159	1		T110	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T2	20		T8	156		T21	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	2		T14	16		T224	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	7		T219	12		T76	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T19	7		T150	20		T225	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	19		T158	12		T73	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	1		T102	5		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T220	15		T72	16		T226	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	4		T227	2		T73	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	5		T63	2		T228	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	4		T146	14		T73	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	2		T146	2		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T229	14		T57	17		T230	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	15		T17	11		T187	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	1		T108	12		T76	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T4	3		T161	5		T183	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	2		T222	14		T231	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T38	12		T12	1		T134	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	2		T16	14		T13	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T19	4		T39	6		T232	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T233	13		T200	2		T234	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T39	2		T110	13		T235	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T8	3		T22	4		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T218	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	1		T7	1		T198	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	8		T159	1		T236	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1360	1			T1	1		T5	32		T10	32
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T219	1		T154	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T18	11		T148	1		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	1		T155	14		T220	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T152	1		T169	9		T227	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T39	1		T63	5		T72	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	1		T149	3		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	14		T47	1		T108	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	1		T198	18		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T47	1		T17	14		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T168	1		T18	6		T147	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T4	1		T17	10		T18	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T1	1		T8	5		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T62	1		T149	16		T38	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T4	1		T16	14		T147	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T146	1		T19	5		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16714	1			T2	20		T8	153		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T237	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T4	2		T14	16		T224	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	7		T76	16		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T19	7		T150	20		T225	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	19		T219	12		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	1		T102	5		T239	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T220	15		T73	10		T226	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T227	2		T161	13		T240	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T63	2		T72	16		T228	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	4		T13	4		T73	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	15		T108	11		T14	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	14		T73	1		T229	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T17	2		T146	2		T187	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T108	12		T76	12		T164	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	3		T17	11		T241	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	3		T222	14		T199	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T38	12		T12	1		T161	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T4	2		T16	14		T13	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T19	4		T39	8		T232	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	3		T7	1		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T6	8		T219	13		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T1	1		T5	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T9	20		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T18	1		T148	1		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T155	1		T220	16		T72	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T149	1		T152	1		T13	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T39	1		T14	6		T221	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	5		T146	15		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T47	2		T17	3		T146	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T168	1		T198	2		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	16		T17	12		T18	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T8	2		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	4		T62	1		T19	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T8	5		T9	1		T222	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T149	1		T151	1		T38	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	3		T16	16		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T146	1		T19	5		T39	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T149	1		T151	1		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T39	3		T159	1		T110	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17257	1			T2	20		T8	156		T21	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T198	11		T12	7		T157	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	7		T154	11		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T5	29		T10	29		T19	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T157	2		T73	9		T229	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T18	10		T12	1		T102	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T155	13		T220	13		T72	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T149	2		T13	9		T227	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	2		T63	2		T182	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T169	8		T73	2		T167	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T17	13		T108	5		T74	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T198	16		T169	9		T229	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	13		T17	9		T18	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	1		T18	5		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T154	7		T161	5		T55	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T222	12		T242	7		T243	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T149	15		T38	15		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	12		T147	4		T13	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	4		T157	8		T167	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T149	4		T233	12		T234	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T39	1		T244	11		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	392	1			T8	3		T22	4		T25	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T218	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	3		T7	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	8		T159	1		T236	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T1	1		T5	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	20		T219	13		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T18	1		T148	1		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	1		T155	1		T220	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T152	1		T169	1		T227	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T39	1		T63	5		T72	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T9	5		T149	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	16		T47	1		T108	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T146	15		T198	2		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T47	1		T17	3		T146	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T168	1		T18	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	4		T17	12		T18	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T8	7		T9	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T62	1		T149	1		T38	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T4	3		T16	16		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T146	1		T19	5		T151	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16873	1			T2	20		T8	153		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T237	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T198	11		T12	7		T224	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	7		T236	11		T76	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T5	29		T10	29		T19	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T154	11		T229	7		T238	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T18	10		T12	1		T102	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T155	13		T220	13		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T169	8		T227	12		T161	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T63	2		T72	14		T181	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T149	2		T13	9		T73	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T3	13		T108	5		T14	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T198	16		T169	9		T73	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T17	13		T187	13		T190	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T18	5		T147	7		T169	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T17	9		T18	11		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T222	12		T242	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T149	15		T38	15		T227	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T16	12		T147	4		T149	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T19	4		T39	1		T134	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22413

1

T1

1

T2

20

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3479

1

T1

2

T4

7

T8

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20152

1

T1

1

T2

20

T3

29

auto[1]

5740

1

T1

2

T4

3

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T244	12		T241	13		T245	18
values[0]	1	1			T246	1		-	-		-	-
values[1]	683	1			T8	3		T9	5		T146	15
values[2]	702	1			T198	9		T39	4		T12	2
values[3]	774	1			T17	16		T18	11		T146	3
values[4]	573	1			T3	29		T47	1		T18	6
values[5]	632	1			T4	3		T8	5		T9	20
values[6]	764	1			T6	15		T7	1		T168	1
values[7]	553	1			T1	2		T147	8		T148	1
values[8]	2795	1			T5	32		T10	32		T11	1
values[9]	1116	1			T1	1		T4	7		T9	1
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	884	1			T8	3		T9	5		T146	15
values[1]	677	1			T148	1		T198	21		T39	4
values[2]	765	1			T17	16		T18	11		T146	4
values[3]	548	1			T3	29		T4	3		T47	1
values[4]	692	1			T6	15		T8	5		T9	20
values[5]	749	1			T1	2		T7	1		T19	9
values[6]	2720	1			T5	32		T10	32		T11	1
values[7]	627	1			T62	1		T16	21		T47	1
values[8]	856	1			T4	7		T9	1		T16	7
values[9]	118	1			T1	1		T155	14		T149	5
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T20	15		T12	1		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T8	2		T9	1		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T148	1		T198	9		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T198	12		T39	2		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	11		T148	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T17	14		T146	2		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	14		T47	1		T18	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T4	1		T162	13		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	8		T8	3		T19	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	1		T168	2		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T7	1		T19	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	1		T148	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T5	32		T10	32		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T156	1		T222	13		T108	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T62	1		T47	1		T17	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T16	11		T149	16		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T4	1		T9	1		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T4	1		T187	14		T247	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T149	5		T39	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T1	1		T155	14		T242	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T108	12		T76	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	1		T9	4		T146	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T110	13		T238	3		T240	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	2		T161	5		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T38	12		T229	11		T248	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T17	2		T146	2		T39	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	15		T13	10		T249	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	2		T170	10		T250	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	7		T8	2		T19	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	19		T190	17		T102	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T19	4		T219	5		T167	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T220	15		T134	3		T73	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1067	1			T150	20		T225	24		T251	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T222	14		T108	11		T14	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T17	11		T73	1		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	10		T161	13		T170	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	2		T16	4		T14	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	3		T187	7		T247	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T65	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T252	9		T65	1		T253	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T244	12		T245	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T241	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T246	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T20	15		T108	10		T76	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	2		T9	1		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T198	9		T12	1		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T39	2		T133	1		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T18	11		T148	1		T38	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T17	14		T146	1		T198	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	14		T47	1		T18	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T146	1		T149	3		T162	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	3		T147	5		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	1		T9	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T6	8		T7	1		T19	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T168	1		T151	1		T220	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T1	1		T147	8		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	1		T148	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T5	32		T10	32		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T16	11		T152	1		T154	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T4	1		T9	1		T16	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T1	1		T4	1		T155	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T245	5		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T241	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T108	12		T76	12		T240	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T9	4		T146	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	1		T110	13		T238	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T39	2		T232	2		T13	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T38	12		T229	11		T248	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T17	2		T146	2		T39	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	15		T182	4		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T170	10		T255	3		T205	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	2		T13	10		T227	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T4	2		T9	19		T190	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	7		T19	11		T219	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T220	15		T134	3		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T219	5		T158	12		T167	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T222	14		T14	16		T76	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T150	20		T225	24		T251	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	10		T108	11		T57	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	2		T16	4		T17	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T4	3		T187	7		T247	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4