Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22565

1

T1

2

T2

20

T4

10

auto[ADC_CTRL_FILTER_COND_OUT]

3327

1

T1

1

T3

29

T7

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20179

1

T1

2

T2

20

T3

29

auto[1]

5713

1

T1

1

T4

7

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	74	1			T13	21		T301	18		T311	26
values[0]	41	1			T13	14		T14	8		T285	1
values[1]	635	1			T4	3		T9	5		T62	1
values[2]	646	1			T1	1		T9	1		T16	7
values[3]	708	1			T1	1		T8	5		T16	21
values[4]	626	1			T9	20		T17	21		T20	15
values[5]	552	1			T6	15		T146	15		T38	28
values[6]	758	1			T18	11		T146	3		T147	8
values[7]	701	1			T7	1		T47	1		T147	5
values[8]	758	1			T1	1		T4	4		T18	6
values[9]	3137	1			T3	29		T4	3		T5	32
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	781	1			T1	1		T4	3		T9	5
values[1]	740	1			T9	1		T16	7		T19	9
values[2]	664	1			T1	1		T8	5		T16	21
values[3]	548	1			T9	20		T20	15		T38	28
values[4]	617	1			T18	11		T146	15		T161	26
values[5]	733	1			T6	15		T146	3		T169	19
values[6]	2956	1			T1	1		T4	4		T5	32
values[7]	619	1			T8	3		T18	6		T19	18
values[8]	788	1			T3	29		T4	3		T168	1
values[9]	187	1			T156	1		T159	1		T230	13
minimum	17259	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T1	1		T4	1		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	1		T62	1		T18	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	1		T155	14		T198	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	3		T19	5		T149	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	1		T17	10		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	3		T16	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T20	15		T232	1		T134	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	1		T38	16		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T72	15		T260	3		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T18	11		T146	1		T161	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	8		T146	1		T108	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T169	19		T102	10		T227	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1422	1			T4	1		T5	32		T10	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	1		T7	1		T147	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T187	14		T156	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	2		T18	6		T19	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T151	1		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	14		T168	1		T149	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T159	1		T310	15		T294	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T156	1		T230	1		T255	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T265	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T4	2		T17	2		T219	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	4		T232	2		T108	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T224	16		T228	1		T61	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T16	4		T19	4		T12	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T17	11		T73	1		T167	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	2		T16	10		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T134	3		T63	2		T249	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	19		T38	12		T240	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T72	16		T170	10		T267	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T146	14		T161	13		T224	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	7		T146	2		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T102	5		T73	5		T55	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T4	3		T190	17		T150	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T220	15		T222	14		T110	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T187	7		T224	2		T239	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	1		T19	7		T39	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	2		T247	3		T219	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	15		T13	10		T76	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T313	16		T103	1		T312	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T230	12		T255	3		T298	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T13	11		T301	10		T311	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T13	10		T285	1		T193	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T14	3		T263	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T4	1		T168	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	1		T62	1		T18	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	1		T9	1		T155	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T16	3		T19	5		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T198	12		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	3		T16	11		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T17	10		T20	15		T134	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	1		T152	1		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	8		T232	1		T72	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T146	1		T38	16		T169	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T146	1		T161	6		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T18	11		T147	8		T169	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T47	1		T108	6		T14	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	1		T147	5		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	1		T190	15		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T18	6		T19	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T4	1		T5	32		T10	32
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	14		T8	2		T168	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T13	10		T301	8		T311	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T13	4		T193	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T14	5		T263	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T4	2		T17	2		T219	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	4		T108	12		T167	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T167	4		T229	10		T228	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T16	4		T19	4		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T73	1		T224	16		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	2		T16	10		T12	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T17	11		T134	3		T63	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	19		T240	4		T319	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T6	7		T72	16		T164	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T146	14		T38	12		T161	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T146	2		T161	5		T170	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T102	5		T73	5		T224	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T108	11		T14	16		T315	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T110	13		T76	15		T259	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	3		T190	17		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T19	7		T39	6		T220	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T4	2		T187	7		T150	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	15		T8	1		T226	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	1		T4	3		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	5		T62	1		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T9	1		T155	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	5		T19	5		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T17	12		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T8	5		T16	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T20	1		T232	1		T134	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	20		T38	13		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T72	17		T260	1		T170	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T18	1		T146	15		T161	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T6	8		T146	3		T108	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T169	2		T102	10		T227	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1478	1			T4	4		T5	3		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T7	1		T147	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T187	8		T156	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	2		T18	1		T19	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T4	3		T151	1		T247	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	16		T168	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T159	1		T310	1		T294	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T156	1		T230	13		T255	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T265	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T17	13		T198	8		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T18	11		T149	2		T108	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T155	13		T198	11		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T16	2		T19	4		T149	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T17	9		T236	11		T73	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	10		T264	8		T302	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T20	14		T134	2		T63	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T38	15		T257	6		T320	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T72	14		T260	2		T170	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T18	10		T161	12		T224	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	7		T108	5		T161	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T169	17		T102	5		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1083	1			T5	29		T10	29		T281	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T147	11		T220	13		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T187	13		T157	2		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	1		T18	5		T19	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T72	2		T73	9		T76	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	13		T149	4		T13	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T310	14		T294	6		T313	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T255	8		T284	4		T311	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T13	11		T301	9		T311	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T13	5		T285	1		T193	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T14	6		T263	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	3		T168	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	5		T62	1		T18	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	1		T9	1		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	5		T19	5		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	1		T198	1		T247	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	5		T16	11		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T17	12		T20	1		T134	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	20		T152	1		T275	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T6	8		T232	1		T72	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T146	15		T38	13		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T146	3		T161	6		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T18	1		T147	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T47	1		T108	12		T14	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T147	1		T110	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T4	4		T190	18		T178	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T18	1		T19	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T4	3		T5	3		T10	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	16		T8	2		T168	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	10		T301	9		T311	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T13	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T14	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	13		T198	8		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T18	11		T149	2		T108	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T155	13		T154	7		T169	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T16	2		T19	4		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T198	11		T236	11		T73	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T16	10		T149	15		T12	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T17	9		T20	14		T134	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T240	13		T298	10		T257	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T6	7		T72	14		T260	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T38	15		T169	9		T161	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T161	5		T170	2		T261	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T18	10		T147	7		T169	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T108	5		T157	2		T315	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T147	4		T76	12		T182	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T190	14		T227	12		T73	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T18	5		T19	10		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1146	1			T5	29		T10	29		T281	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	13		T8	1		T149	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7