Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22478

1

T1

1

T2

20

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3414

1

T1

2

T4

7

T8

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20053

1

T1

1

T2

20

T3

29

auto[1]

5839

1

T1

2

T4

3

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	229	1			T4	4		T16	7		T149	5
values[0]	26	1			T311	26		-	-		-	-
values[1]	613	1			T8	3		T9	5		T20	15
values[2]	787	1			T146	15		T198	9		T39	4
values[3]	735	1			T17	16		T18	11		T146	4
values[4]	552	1			T3	29		T47	1		T18	6
values[5]	642	1			T4	3		T8	5		T9	20
values[6]	763	1			T1	1		T6	15		T7	1
values[7]	575	1			T1	1		T147	8		T219	6
values[8]	2804	1			T5	32		T10	32		T11	1
values[9]	910	1			T1	1		T4	3		T9	1
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	691	1			T8	3		T9	5		T146	15
values[1]	714	1			T148	1		T198	21		T39	4
values[2]	726	1			T17	16		T18	11		T146	4
values[3]	531	1			T3	29		T4	3		T47	1
values[4]	682	1			T6	15		T8	5		T9	20
values[5]	752	1			T1	2		T7	1		T19	27
values[6]	2833	1			T5	32		T10	32		T11	1
values[7]	578	1			T62	1		T16	21		T47	1
values[8]	807	1			T1	1		T4	7		T9	1
values[9]	133	1			T155	14		T149	5		T39	1
minimum	17445	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T20	15		T12	1		T108	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	2		T9	1		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T148	1		T198	9		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T198	12		T39	2		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T18	11		T148	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T17	14		T146	2		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T3	14		T47	1		T18	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T4	1		T149	3		T162	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	8		T8	3		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T168	1		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	1		T7	1		T19	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T148	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T5	32		T10	32		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T156	1		T154	12		T222	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T62	1		T47	1		T17	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	11		T149	16		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T4	1		T9	1		T16	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T4	1		T187	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T149	5		T39	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T155	14		T221	1		T242	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17150	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T12	2		T321	15		T316	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T108	12		T224	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T8	1		T9	4		T146	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T110	13		T238	3		T254	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	2		T161	5		T55	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	12		T229	11		T248	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T17	2		T146	2		T39	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	15		T249	14		T182	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	2		T170	10		T276	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	7		T8	2		T219	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T9	19		T190	17		T102	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	11		T219	5		T167	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T220	15		T134	3		T73	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T150	20		T225	24		T251	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T222	14		T108	11		T14	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T17	11		T73	1		T238	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	10		T161	13		T170	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T4	2		T16	4		T14	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	3		T187	7		T247	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T69	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T252	9		T253	12		T322	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T132	3		T133	2		T134	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T12	1		T321	14		T311	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T16	3		T149	5		T72	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T4	1		T221	1		T315	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T311	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T20	15		T12	1		T108	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T8	2		T9	1		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T198	9		T232	1		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T146	1		T39	2		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T18	11		T148	1		T38	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T17	14		T146	2		T198	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	14		T47	1		T18	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T149	3		T162	13		T170	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	3		T168	1		T147	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T4	1		T9	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T6	8		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T148	1		T151	1		T220	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T147	8		T219	1		T157	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T156	1		T154	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T5	32		T10	32		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	11		T152	1		T154	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	1		T9	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T1	1		T155	14		T149	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T16	4		T72	16		T231	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T4	3		T315	4		T298	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T311	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T108	12		T240	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T8	1		T9	4		T12	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T110	13		T224	2		T238	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T146	14		T39	2		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T38	12		T229	11		T248	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T17	2		T146	2		T39	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T3	15		T182	4		T254	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T170	10		T205	3		T276	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	2		T219	12		T13	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T4	2		T9	19		T190	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	7		T19	11		T323	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T220	15		T134	3		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T219	5		T158	12		T167	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T222	14		T14	16		T73	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T150	20		T225	24		T251	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T16	10		T108	11		T170	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	2		T17	11		T14	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T187	7		T247	3		T161	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T20	1		T12	2		T108	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	2		T9	5		T146	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T148	1		T198	1		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T198	1		T39	3		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T18	1		T148	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T17	3		T146	4		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	16		T47	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T4	3		T149	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	8		T8	5		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	20		T168	1		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T1	1		T7	1		T19	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	1		T148	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T5	3		T10	3		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T156	1		T154	1		T222	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T62	1		T47	1		T17	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	11		T149	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T4	3		T9	1		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	1		T4	4		T187	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T149	1		T39	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T155	1		T221	1		T242	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17292	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T12	2		T321	15		T316	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T20	14		T108	9		T224	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	1		T12	7		T13	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T198	8		T157	2		T238	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T198	11		T39	1		T161	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T18	10		T38	15		T229	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T17	13		T74	13		T256	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	13		T18	5		T227	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T149	2		T162	12		T170	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	7		T147	4		T236	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T190	14		T102	5		T167	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T19	14		T198	8		T157	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T220	13		T134	2		T73	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T5	29		T10	29		T18	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T154	11		T222	12		T108	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T17	9		T73	2		T181	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T16	10		T149	15		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T16	2		T14	2		T63	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T187	13		T157	2		T73	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T149	4		T69	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T155	13		T242	7		T252	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T228	7		T270	10		T324	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T12	1		T321	14		T311	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T16	5		T149	1		T72	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T4	4		T221	1		T315	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T311	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T20	1		T12	2		T108	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T8	2		T9	5		T178	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T198	1		T232	1		T110	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T146	15		T39	3		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T18	1		T148	1		T38	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T17	3		T146	4		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	16		T47	1		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T149	1		T162	1		T170	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	5		T168	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T4	3		T9	20		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T1	1		T6	8		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T148	1		T151	1		T220	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T147	1		T219	6		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	1		T156	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T5	3		T10	3		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T16	11		T152	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	3		T9	1		T47	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T1	1		T155	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T16	2		T149	4		T72	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T315	13		T252	2		T325	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T311	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T20	14		T108	9		T228	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T8	1		T12	8		T76	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T198	8		T157	2		T224	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T39	1		T13	9		T161	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T18	10		T38	15		T229	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	13		T198	11		T74	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	13		T18	5		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T149	2		T162	12		T170	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T147	4		T236	11		T13	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T190	14		T61	10		T255	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	7		T19	14		T198	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T220	13		T134	2		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T147	7		T157	8		T162	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T154	11		T222	12		T73	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T5	29		T10	29		T18	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	10		T154	7		T169	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T17	9		T14	2		T63	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T155	13		T149	15		T187	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7