Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22655

1

T1

2

T2

20

T4

7

auto[ADC_CTRL_FILTER_COND_OUT]

3237

1

T1

1

T3

29

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20255

1

T1

3

T2

20

T3

29

auto[1]

5637

1

T4

6

T5

32

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	324	1			T16	21		T151	1		T224	7
values[0]	36	1			T200	8		T274	28		-	-
values[1]	677	1			T6	15		T8	5		T9	1
values[2]	652	1			T1	2		T147	5		T220	29
values[3]	821	1			T18	6		T198	12		T178	1
values[4]	2765	1			T3	29		T4	6		T5	32
values[5]	573	1			T7	1		T18	11		T247	1
values[6]	728	1			T9	20		T168	1		T47	1
values[7]	504	1			T4	4		T8	3		T9	5
values[8]	642	1			T1	1		T47	1		T18	12
values[9]	914	1			T20	15		T190	32		T38	28
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	603	1			T6	15		T8	5		T9	1
values[1]	674	1			T1	2		T147	5		T39	1
values[2]	808	1			T3	29		T4	3		T18	6
values[3]	2788	1			T4	3		T5	32		T7	1
values[4]	543	1			T9	20		T18	11		T146	4
values[5]	672	1			T4	4		T8	3		T168	1
values[6]	541	1			T9	5		T149	3		T198	9
values[7]	562	1			T1	1		T47	1		T18	12
values[8]	1082	1			T20	15		T190	32		T151	1
values[9]	104	1			T16	21		T12	2		T152	1
minimum	17515	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	3		T62	1		T16	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T6	8		T9	1		T198	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	1		T147	5		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T133	1		T264	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T18	6		T152	1		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	14		T4	1		T198	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1409	1			T4	1		T5	32		T10	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T7	1		T17	10		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T18	11		T146	1		T19	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T9	1		T146	1		T134	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T8	2		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	14		T147	8		T155	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T259	1		T249	14		T238	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	1		T149	3		T198	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T47	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T18	12		T19	11		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T20	15		T151	1		T38	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	346	1			T190	15		T178	1		T154	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T12	1		T152	1		T224	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T16	11		T310	5		T193	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17108	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T157	9		T72	15		T76	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	2		T16	4		T187	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	7		T74	15		T167	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T220	15		T73	5		T229	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T264	10		T298	1		T270	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T232	2		T108	12		T170	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	15		T4	2		T219	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T4	2		T150	20		T225	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	11		T146	14		T76	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T19	4		T231	2		T240	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	19		T146	2		T134	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	3		T8	1		T13	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T17	2		T267	13		T255	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T259	7		T249	14		T238	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T9	4		T222	14		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T247	3		T102	5		T72	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T19	7		T39	2		T12	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T38	12		T55	2		T292	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T190	17		T14	5		T182	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T12	1		T224	2		T299	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T16	10		T193	17		T277	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T132	3		T133	2		T134	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T72	16		T76	12		T326	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T151	1		T224	5		T327	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T16	11		T238	11		T310	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T200	1		T274	13		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	3		T62	1		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T6	8		T9	1		T198	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T147	5		T220	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	1		T133	1		T300	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T18	6		T39	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T198	12		T178	1		T219	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T4	1		T5	32		T10	32
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	14		T4	1		T17	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T18	11		T247	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	1		T134	5		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T168	1		T47	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	1		T146	1		T147	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	1		T8	2		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	1		T17	14		T149	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T47	1		T247	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T18	12		T19	11		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T20	15		T38	16		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T190	15		T178	1		T12	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T224	2		T55	2		T292	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T16	10		T238	11		T328	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T200	7		T274	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	2		T16	4		T187	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	7		T72	16		T74	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T220	15		T73	5		T167	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T298	1		T270	9		T329	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T232	2		T108	12		T224	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T219	17		T39	6		T108	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T4	2		T150	20		T225	24
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	15		T4	2		T17	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T231	2		T240	4		T301	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T134	3		T229	14		T57	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T19	4		T13	4		T63	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	19		T146	2		T267	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	3		T8	1		T249	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T9	4		T17	2		T222	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T247	3		T102	5		T72	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T19	7		T39	2		T14	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T38	12		T12	1		T240	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T190	17		T12	1		T14	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	5		T62	1		T16	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	8		T9	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T147	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T133	1		T264	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T18	1		T152	1		T232	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	16		T4	3		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T4	3		T5	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	1		T17	12		T146	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T18	1		T146	1		T19	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	20		T146	3		T134	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	4		T8	2		T168	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T17	3		T147	1		T155	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T259	8		T249	15		T238	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	5		T149	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	1		T47	1		T247	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T18	1		T19	8		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T20	1		T151	1		T38	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T190	18		T178	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T12	2		T152	1		T224	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T16	11		T310	1		T193	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17288	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T157	1		T72	17		T76	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	2		T187	13		T161	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T6	7		T198	8		T74	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T147	4		T220	13		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T264	12		T300	6		T302	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T18	5		T108	9		T170	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	13		T198	11		T108	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1063	1			T5	29		T10	29		T281	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T17	9		T76	14		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T18	10		T19	4		T149	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T134	2		T217	14		T317	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	1		T13	9		T63	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T17	13		T147	7		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T249	13		T238	2		T256	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T149	2		T198	8		T222	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T102	5		T72	2		T73	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T18	11		T19	10		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T20	14		T38	15		T169	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T190	14		T154	11		T169	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T224	4		T303	13		T299	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T16	10		T310	4		T277	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T170	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T157	8		T72	14		T76	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T151	1		T224	3		T327	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T16	11		T238	12		T310	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T200	8		T274	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	5		T62	1		T16	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	8		T9	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	1		T147	1		T220	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	1		T133	1		T300	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T18	1		T39	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T198	1		T178	1		T219	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T4	3		T5	3		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	16		T4	3		T17	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T18	1		T247	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	1		T134	6		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T168	1		T47	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	20		T146	3		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T4	4		T8	2		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T9	5		T17	3		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	1		T47	1		T247	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T18	1		T19	8		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T20	1		T38	13		T12	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T190	18		T178	1		T12	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T224	4		T55	10		T292	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T16	10		T238	10		T310	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T274	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T16	2		T187	13		T161	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	7		T198	8		T157	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T147	4		T220	13		T154	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T300	6		T302	2		T296	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T18	5		T108	9		T224	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T198	11		T108	5		T164	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T5	29		T10	29		T281	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	13		T17	9		T13	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T18	10		T242	7		T240	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T134	2		T229	14		T57	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T19	4		T149	4		T13	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T147	7		T155	13		T267	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	1		T249	13		T239	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T17	13		T149	2		T198	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T102	5		T72	2		T73	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T18	11		T19	10		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T20	14		T38	15		T169	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T190	14		T12	1		T154	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7