Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22561

1

T1

1

T2

20

T4

7

auto[ADC_CTRL_FILTER_COND_OUT]

3331

1

T1

2

T3

29

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20205

1

T1

1

T2

20

T3

29

auto[1]

5687

1

T1

2

T4

6

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	389	1			T3	29		T16	7		T47	1
values[0]	8	1			T152	1		T206	7		-	-
values[1]	757	1			T4	3		T8	5		T62	1
values[2]	606	1			T149	16		T190	32		T39	1
values[3]	742	1			T16	21		T47	1		T18	12
values[4]	582	1			T1	1		T4	7		T148	1
values[5]	2653	1			T5	32		T9	1		T10	32
values[6]	744	1			T1	2		T17	21		T20	15
values[7]	709	1			T6	15		T7	1		T9	5
values[8]	544	1			T9	20		T168	1		T149	3
values[9]	902	1			T8	3		T17	16		T18	6
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	716	1			T4	3		T8	5		T62	1
values[1]	664	1			T16	21		T47	1		T187	21
values[2]	600	1			T4	3		T18	12		T146	16
values[3]	2776	1			T1	1		T4	4		T5	32
values[4]	558	1			T1	1		T149	5		T178	1
values[5]	678	1			T1	1		T7	1		T9	5
values[6]	744	1			T6	15		T17	21		T19	9
values[7]	472	1			T9	20		T168	1		T149	3
values[8]	966	1			T3	29		T8	3		T16	7
values[9]	235	1			T17	16		T38	28		T170	11
minimum	17483	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T62	1		T155	14		T149	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	1		T8	3		T147	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T47	1		T232	1		T154	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T16	11		T187	14		T190	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	1		T146	2		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T18	12		T156	1		T227	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T1	1		T4	1		T5	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T198	12		T178	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T178	1		T39	2		T169	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	1		T149	5		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	1		T9	1		T20	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T151	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T17	10		T19	5		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	8		T147	5		T220	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T168	1		T149	3		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T9	1		T12	8		T180	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	3		T47	1		T18	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T3	14		T8	2		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T17	14		T38	16		T243	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T170	5		T285	1		T97	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17161	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T19	11		T152	1		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T255	3		T199	8		T265	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	2		T8	2		T222	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T72	2		T228	15		T226	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T16	10		T187	7		T190	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T4	2		T146	14		T39	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T227	2		T161	13		T30	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1096	1			T4	3		T150	20		T225	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T219	12		T238	5		T326	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T39	2		T108	12		T72	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T241	12		T248	5		T172	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	4		T63	2		T224	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T158	12		T229	25		T192	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T17	11		T19	4		T219	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	7		T220	15		T232	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T247	3		T12	2		T170	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T9	19		T238	11		T202	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T16	4		T108	11		T224	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	15		T8	1		T146	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T17	2		T38	12		T265	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T170	6		T268	15		T284	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T132	3		T133	2		T134	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T19	7		T73	5		T230	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T16	3		T47	1		T18	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	14		T260	3		T170	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T206	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T152	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T62	1		T168	1		T155	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T4	1		T8	3		T19	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T149	16		T232	1		T154	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T190	15		T39	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	1		T146	2		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T16	11		T18	12		T187	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T4	2		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T198	12		T178	1		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1341	1			T5	32		T9	1		T10	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T149	5		T159	1		T326	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T17	10		T20	15		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	2		T151	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	1		T9	1		T19	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	8		T147	5		T154	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T168	1		T149	3		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T9	1		T12	8		T220	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T17	14		T18	6		T38	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T8	2		T146	1		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T16	4		T108	11		T202	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T3	15		T170	6		T323	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T206	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	14		T255	3		T199	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	2		T8	2		T19	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T228	15		T30	1		T81	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T190	17		T222	14		T292	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T146	14		T39	6		T72	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T16	10		T187	7		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T4	5		T14	16		T76	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T219	12		T238	5		T286	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T150	20		T225	24		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T326	13		T245	9		T248	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T17	11		T63	2		T72	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T229	14		T241	12		T192	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	4		T19	4		T219	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	7		T14	5		T158	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T247	3		T12	1		T110	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T9	19		T220	15		T232	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T17	2		T38	12		T12	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	1		T146	2		T134	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T62	1		T155	1		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T4	3		T8	5		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	1		T232	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T16	11		T187	8		T190	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T4	3		T146	16		T39	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T18	1		T156	1		T227	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T1	1		T4	4		T5	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T198	1		T178	1		T219	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T178	1		T39	3		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	1		T149	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	1		T9	5		T20	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T151	1		T158	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T17	12		T19	5		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	8		T147	1		T220	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T168	1		T149	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	20		T12	1		T180	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T16	5		T47	1		T18	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	16		T8	2		T146	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T17	3		T38	13		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T170	7		T285	1		T97	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17328	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T19	8		T152	1		T13	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T155	13		T149	15		T198	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	7		T222	12		T102	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T154	11		T72	2		T228	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T16	10		T187	13		T190	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T227	7		T157	2		T162	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	11		T227	12		T161	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T5	29		T10	29		T281	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T198	11		T238	11		T256	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T39	1		T169	8		T108	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T149	4		T181	9		T296	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T20	14		T63	2		T224	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T242	7		T229	17		T310	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T17	9		T19	4		T198	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	7		T147	4		T220	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T149	2		T12	1		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T12	7		T238	10		T254	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T16	2		T18	15		T108	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T3	13		T8	1		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T17	13		T38	15		T243	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T170	4		T97	3		T101	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T13	19		T276	9		T81	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T19	10		T157	2		T73	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T16	5		T47	1		T18	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T3	16		T260	1		T170	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T206	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T152	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T62	1		T168	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T4	3		T8	5		T19	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T149	1		T232	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T190	18		T39	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T47	1		T146	16		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T16	11		T18	1		T187	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T4	7		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T198	1		T178	1		T219	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T5	3		T9	1		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T149	1		T159	1		T326	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T17	12		T20	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	2		T151	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T9	5		T19	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	8		T147	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T168	1		T149	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	20		T12	1		T220	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T17	3		T18	1		T38	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	2		T146	3		T19	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T16	2		T18	10		T108	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	13		T260	2		T170	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T155	13		T198	8		T13	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T19	10		T147	7		T102	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T149	15		T154	11		T228	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T190	14		T222	12		T157	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T227	7		T157	2		T72	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T16	10		T18	11		T187	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T169	13		T236	11		T76	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T198	11		T238	11		T256	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T5	29		T10	29		T281	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T149	4		T245	5		T296	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T17	9		T20	14		T63	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T181	9		T242	7		T229	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T19	4		T198	8		T229	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	7		T147	4		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T149	2		T169	9		T170	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T12	7		T220	13		T73	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	13		T18	5		T38	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T8	1		T134	2		T76	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7