Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22486

1

T1

1

T2

20

T4

6

auto[ADC_CTRL_FILTER_COND_OUT]

3406

1

T1

2

T3

29

T4

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20183

1

T1

2

T2

20

T4

7

auto[1]

5709

1

T1

1

T3

29

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	621	1			T8	3		T16	28		T22	4
values[0]	22	1			T218	1		T277	21		-	-
values[1]	618	1			T4	3		T6	15		T7	1
values[2]	2750	1			T1	2		T5	32		T9	20
values[3]	593	1			T18	11		T155	14		T148	1
values[4]	624	1			T39	1		T152	1		T169	9
values[5]	824	1			T3	29		T9	5		T47	1
values[6]	774	1			T47	1		T17	37		T146	18
values[7]	699	1			T4	4		T168	2		T18	18
values[8]	633	1			T1	1		T8	8		T9	1
values[9]	861	1			T4	3		T19	9		T151	1
minimum	16873	1			T2	20		T8	153		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	592	1			T148	1		T154	12		T236	12
values[1]	2752	1			T1	2		T5	32		T9	20
values[2]	588	1			T18	11		T155	14		T148	1
values[3]	749	1			T149	3		T39	1		T152	1
values[4]	861	1			T3	29		T9	5		T47	2
values[5]	719	1			T168	1		T17	21		T18	12
values[6]	640	1			T4	4		T8	3		T62	1
values[7]	634	1			T1	1		T8	5		T9	1
values[8]	842	1			T4	3		T16	28		T146	1
values[9]	101	1			T149	5		T159	1		T223	1
minimum	17414	1			T2	20		T4	3		T6	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T148	1		T236	12		T157	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T154	12		T76	15		T238	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T5	32		T10	32		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	2		T9	1		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T18	11		T148	1		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T155	14		T161	13		T72	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T13	10		T275	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T149	3		T39	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T148	1		T156	1		T169	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T3	14		T9	1		T47	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T168	1		T17	10		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T18	12		T219	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	2		T62	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	1		T19	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T8	3		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	1		T149	16		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	1		T16	14		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T147	5		T39	6		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T149	5		T223	1		T233	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T159	1		T244	12		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17148	1			T2	20		T4	1		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T6	8		T12	8		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T60	4		T250	9		T199	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T76	16		T238	5		T55	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T19	7		T150	20		T225	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	19		T219	12		T158	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T12	1		T220	15		T102	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T161	13		T72	16		T226	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	4		T63	2		T73	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	5		T227	2		T61	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T74	15		T167	2		T224	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	15		T9	4		T17	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T17	11		T146	14		T190	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T219	5		T229	14		T61	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	1		T222	14		T108	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	3		T161	5		T292	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	2		T38	12		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T134	3		T224	2		T261	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	2		T16	14		T19	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T39	8		T232	2		T13	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T233	13		T274	11		T237	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T241	12		T235	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	2		T132	3		T133	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T6	7		T224	2		T238	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	441	1			T8	3		T16	14		T22	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T147	5		T39	4		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T277	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	1		T7	1		T198	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	8		T12	8		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T5	32		T10	32		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T1	2		T9	1		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T18	11		T148	1		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T155	14		T161	13		T275	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T169	9		T275	1		T63	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	1		T152	1		T227	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T148	1		T13	10		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	14		T9	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T17	10		T146	1		T190	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T47	1		T17	14		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T168	2		T18	6		T147	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T4	1		T18	12		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T1	1		T8	5		T62	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T149	16		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T4	1		T19	5		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T39	2		T152	1		T232	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16714	1			T2	20		T8	153		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T16	14		T250	8		T233	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T39	6		T55	2		T241	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T277	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	2		T14	16		T250	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	7		T76	16		T224	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T19	7		T150	20		T225	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	19		T219	12		T158	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T12	1		T220	15		T102	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T161	13		T73	10		T239	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T63	2		T228	1		T304	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T227	2		T72	16		T61	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	4		T73	5		T74	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	15		T9	4		T108	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T17	11		T146	14		T190	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	2		T146	2		T187	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T108	12		T76	12		T164	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	3		T292	14		T241	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	3		T38	12		T12	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T161	5		T224	2		T261	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	2		T19	4		T110	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T39	2		T232	2		T134	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T148	1		T236	1		T157	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T154	1		T76	17		T238	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T5	3		T10	3		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T1	2		T9	20		T219	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T18	1		T148	1		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T155	1		T161	14		T72	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	5		T275	1		T221	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T149	1		T39	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T148	1		T156	1		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T3	16		T9	5		T47	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T168	1		T17	12		T146	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	1		T219	6		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	2		T62	1		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	4		T19	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	1		T8	5		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	1		T149	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T4	3		T16	16		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T147	1		T39	13		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T149	1		T223	1		T233	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T159	1		T244	1		T241	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17307	1			T2	20		T4	3		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T6	8		T12	1		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T236	11		T157	2		T60	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T154	11		T76	14		T238	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	998	1			T5	29		T10	29		T19	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T157	2		T73	9		T76	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T18	10		T12	1		T220	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T155	13		T161	12		T72	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	9		T63	2		T73	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	2		T14	2		T227	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T169	8		T74	13		T167	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	13		T17	13		T187	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T17	9		T190	14		T198	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T18	11		T162	12		T260	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	1		T18	5		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T154	7		T169	13		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T38	15		T242	7		T267	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T149	15		T134	2		T227	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	12		T19	4		T170	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T147	4		T39	1		T13	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T149	4		T233	12		T274	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T244	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T198	11		T91	10		T194	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T6	7		T12	7		T224	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	469	1			T8	3		T16	16		T22	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T147	1		T39	10		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T218	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T277	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	3		T7	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	8		T12	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1349	1			T5	3		T10	3		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	2		T9	20		T219	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T18	1		T148	1		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T155	1		T161	14		T275	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T169	1		T275	1		T63	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	1		T152	1		T227	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T148	1		T13	5		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	16		T9	5		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T17	12		T146	15		T190	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T47	1		T17	3		T146	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T168	2		T18	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	4		T18	1		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	1		T8	7		T62	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T9	1		T149	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	3		T19	5		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T39	3		T152	1		T232	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16873	1			T2	20		T8	153		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T16	12		T149	4		T250	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T147	4		T55	10		T244	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T277	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T198	11		T236	11		T276	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	7		T12	7		T76	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T5	29		T10	29		T19	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T154	11		T157	2		T76	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T18	10		T12	1		T220	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T155	13		T161	12		T73	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T169	8		T63	2		T310	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T227	12		T72	14		T181	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	9		T73	4		T74	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	13		T149	2		T108	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T17	9		T190	14		T198	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T17	13		T187	13		T73	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T18	5		T147	7		T198	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T18	11		T154	7		T169	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	1		T38	15		T222	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T149	15		T227	7		T161	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T19	4		T170	6		T267	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	1		T134	2		T13	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7