Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22447

1

T1

3

T2

20

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3445

1

T3

29

T4

7

T8

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20062

1

T1

2

T2

20

T4

10

auto[1]

5830

1

T1

1

T3

29

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	359	1			T19	1		T187	21		T38	28
values[0]	35	1			T272	1		T273	5		T274	28
values[1]	565	1			T6	15		T9	20		T168	1
values[2]	2650	1			T3	29		T5	32		T10	32
values[3]	510	1			T1	1		T4	4		T8	3
values[4]	724	1			T8	5		T47	1		T17	16
values[5]	825	1			T1	1		T4	3		T7	1
values[6]	708	1			T1	1		T9	1		T168	1
values[7]	639	1			T4	3		T16	7		T18	11
values[8]	639	1			T62	1		T146	3		T19	27
values[9]	982	1			T18	6		T149	3		T151	1
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	550	1			T6	15		T9	20		T247	1
values[1]	2696	1			T3	29		T5	32		T8	3
values[2]	468	1			T1	1		T4	4		T47	1
values[3]	777	1			T4	3		T8	5		T9	5
values[4]	729	1			T1	2		T7	1		T146	1
values[5]	743	1			T9	1		T16	7		T168	1
values[6]	728	1			T4	3		T62	1		T19	9
values[7]	541	1			T146	3		T19	18		T219	13
values[8]	969	1			T149	3		T187	21		T178	1
values[9]	237	1			T18	6		T19	1		T151	1
minimum	17454	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	8		T9	1		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T247	1		T154	8		T63	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T5	32		T10	32		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	14		T8	2		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	1		T47	1		T13	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	1		T147	5		T219	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	1		T9	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	3		T16	11		T17	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	2		T7	1		T148	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T146	1		T155	14		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T16	3		T168	1		T17	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	1		T18	23		T147	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T19	5		T149	21		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	1		T62	1		T20	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T146	1		T156	1		T73	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T19	11		T219	1		T12	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T149	3		T178	1		T232	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T187	14		T169	14		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T151	1		T38	16		T276	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T18	6		T19	1		T102	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17145	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T247	1		T241	1		T330	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	7		T9	19		T55	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T63	2		T73	10		T259	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1053	1			T150	20		T225	24		T251	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	15		T8	1		T39	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	10		T229	25		T250	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T4	3		T219	5		T12	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	2		T9	4		T146	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	2		T16	10		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T222	14		T72	2		T183	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T227	2		T249	14		T267	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	4		T17	11		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T190	17		T12	1		T14	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T19	4		T76	16		T170	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	2		T220	15		T161	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T146	2		T73	5		T230	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T19	7		T219	12		T134	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T232	2		T13	4		T161	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T187	7		T14	16		T74	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T38	12		T276	6		T65	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T102	5		T72	16		T61	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T132	3		T133	2		T134	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T247	3		T241	12		T172	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T38	16		T161	13		T229	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T19	1		T187	14		T169	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T272	1		T273	1		T274	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T288	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	8		T9	1		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T247	2		T63	5		T73	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T5	32		T10	32		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	14		T148	1		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T1	1		T169	9		T13	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	1		T8	2		T147	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T47	1		T39	2		T108	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	3		T17	14		T198	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	1		T4	1		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T16	11		T146	1		T190	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T168	1		T17	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	1		T18	12		T147	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	3		T149	16		T157	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	1		T18	11		T20	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T146	1		T19	5		T149	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T62	1		T19	11		T198	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T149	3		T151	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T18	6		T159	1		T134	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T38	12		T161	13		T229	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T187	7		T102	5		T167	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T273	4		T274	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T6	7		T9	19		T240	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T247	3		T63	2		T73	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1060	1			T150	20		T225	24		T251	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	15		T39	6		T262	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	10		T229	14		T250	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	3		T8	1		T219	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T39	2		T108	12		T167	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T8	2		T17	2		T76	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	2		T9	4		T146	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T16	10		T190	17		T227	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T17	11		T108	11		T110	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	1		T14	5		T226	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	4		T76	31		T261	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T4	2		T220	15		T161	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T146	2		T19	4		T73	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T19	7		T219	12		T238	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T232	2		T13	4		T158	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T134	3		T14	16		T72	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	8		T9	20		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T247	1		T154	1		T63	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T5	3		T10	3		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	16		T8	2		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	1		T47	1		T13	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	4		T147	1		T219	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T4	3		T9	5		T146	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	5		T16	11		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	2		T7	1		T148	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T146	1		T155	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T16	5		T168	1		T17	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	1		T18	2		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T19	5		T149	2		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	3		T62	1		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T146	3		T156	1		T73	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T19	8		T219	13		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T149	1		T178	1		T232	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T187	8		T169	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T151	1		T38	13		T276	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T18	1		T19	1		T102	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17334	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T247	4		T241	13		T330	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T6	7		T260	2		T256	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T154	7		T63	2		T73	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T5	29		T10	29		T281	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	13		T8	1		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T13	10		T229	17		T306	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T147	4		T12	1		T76	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T39	1		T108	9		T167	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T16	10		T17	13		T198	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T222	12		T157	2		T72	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T155	13		T227	12		T249	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T16	2		T17	9		T154	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T18	21		T147	7		T190	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T19	4		T149	19		T76	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T20	14		T198	19		T220	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T73	4		T298	10		T330	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T19	10		T12	7		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T149	2		T13	9		T161	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T187	13		T169	13		T74	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T38	15		T276	4		T257	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T18	5		T102	5		T72	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T331	6		T332	11		T333	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T234	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T38	13		T161	14		T229	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T19	1		T187	8		T169	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T272	1		T273	5		T274	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T288	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	8		T9	20		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T247	5		T63	5		T73	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1395	1			T5	3		T10	3		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	16		T148	1		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	1		T169	1		T13	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	4		T8	2		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T47	1		T39	3		T108	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	5		T17	3		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T4	3		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T16	11		T146	1		T190	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	1		T168	1		T17	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T18	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T16	5		T149	1		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	3		T18	1		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T146	3		T19	5		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T62	1		T19	8		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T149	1		T151	1		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T18	1		T159	1		T134	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T38	15		T161	12		T229	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T187	13		T169	13		T102	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T274	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	7		T260	2		T256	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T63	2		T73	9		T224	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T5	29		T10	29		T281	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T3	13		T154	7		T182	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T169	8		T13	10		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	1		T147	4		T12	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T39	1		T108	9		T167	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T17	13		T198	8		T169	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T222	12		T72	2		T238	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T16	10		T190	14		T227	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T17	9		T154	11		T108	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T18	11		T147	7		T155	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T16	2		T149	15		T157	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T18	10		T20	14		T198	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T19	4		T149	4		T73	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T19	10		T198	11		T12	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T149	2		T13	9		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T18	5		T134	2		T72	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7