Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22600

1

T1

2

T2

20

T3

29

auto[ADC_CTRL_FILTER_COND_OUT]

3292

1

T1

1

T4

7

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19967

1

T1

1

T2

20

T4

10

auto[1]

5925

1

T1

2

T3

29

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	270	1			T39	10		T220	29		T227	8
values[0]	35	1			T202	17		T265	4		T303	14
values[1]	701	1			T7	1		T8	3		T62	1
values[2]	663	1			T4	3		T9	1		T16	7
values[3]	690	1			T18	12		T146	1		T19	9
values[4]	555	1			T1	1		T148	1		T151	1
values[5]	2727	1			T4	4		T5	32		T8	5
values[6]	719	1			T168	1		T146	3		T151	2
values[7]	728	1			T4	3		T9	20		T18	11
values[8]	797	1			T1	1		T3	29		T168	1
values[9]	751	1			T1	1		T6	15		T47	1
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	751	1			T7	1		T8	3		T9	1
values[1]	556	1			T4	3		T16	7		T18	12
values[2]	665	1			T1	1		T19	9		T148	1
values[3]	2695	1			T4	4		T5	32		T9	5
values[4]	536	1			T8	5		T148	1		T38	28
values[5]	933	1			T4	3		T168	1		T18	11
values[6]	553	1			T1	1		T9	20		T47	1
values[7]	824	1			T3	29		T6	15		T168	1
values[8]	670	1			T1	1		T47	1		T18	6
values[9]	178	1			T39	10		T220	29		T73	12
minimum	17531	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	1		T9	1		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	2		T178	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	1		T16	3		T18	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T146	1		T39	2		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	1		T178	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T19	5		T148	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T5	32		T10	32		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T4	1		T9	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	3		T13	1		T259	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T148	1		T38	16		T198	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T18	11		T19	11		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T4	1		T168	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T47	1		T198	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T9	1		T152	1		T169	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	14		T187	14		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T6	8		T168	1		T12	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T47	1		T18	6		T149	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	1		T152	1		T227	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T224	5		T228	13		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T39	4		T220	14		T73	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17176	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T219	1		T14	3		T238	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T146	14		T76	16		T255	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T219	12		T134	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	2		T16	4		T190	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T39	2		T170	10		T249	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T222	14		T60	4		T262	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T19	4		T13	4		T74	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1119	1			T16	10		T17	2		T150	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T4	3		T9	4		T239	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T8	2		T259	7		T255	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	12		T72	2		T224	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T19	7		T247	3		T13	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	2		T146	2		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T227	2		T229	11		T263	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T9	19		T264	10		T304	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	15		T187	7		T167	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	7		T12	1		T161	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T232	2		T14	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T76	12		T164	1		T229	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T224	2		T228	15		T226	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T39	6		T220	15		T73	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T17	11		T132	3		T133	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T219	5		T14	5		T238	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T224	5		T228	13		T286	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T39	4		T220	14		T227	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T202	6		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T265	2		T303	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T62	1		T17	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	2		T178	1		T219	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T9	1		T16	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T39	2		T110	1		T162	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T18	12		T190	15		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T146	1		T19	5		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	1		T159	1		T73	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T148	1		T151	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T5	32		T8	3		T10	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	1		T9	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T247	1		T13	11		T73	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T168	1		T146	1		T151	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T18	11		T19	11		T198	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T4	1		T9	1		T20	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T3	14		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T168	1		T12	9		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T47	1		T18	6		T149	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	1		T6	8		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T224	2		T228	15		T286	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T39	6		T220	15		T73	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T202	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T265	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T17	11		T146	14		T76	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	1		T219	17		T134	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	2		T16	4		T108	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T39	2		T110	13		T170	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T190	17		T222	14		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T19	4		T13	4		T74	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T73	10		T254	11		T85	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T224	2		T57	17		T240	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1093	1			T8	2		T16	10		T17	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T4	3		T9	4		T38	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T247	3		T13	10		T73	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T146	2		T224	16		T229	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T19	7		T158	12		T229	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	2		T9	19		T102	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	15		T227	2		T167	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T161	5		T63	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T187	7		T12	1		T232	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T6	7		T164	1		T229	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	1		T9	1		T62	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	2		T178	1		T219	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	3		T16	5		T18	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T146	1		T39	3		T221	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T178	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T19	5		T148	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T5	3		T10	3		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T4	4		T9	5		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	5		T13	1		T259	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T148	1		T38	13		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T18	1		T19	8		T247	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T4	3		T168	1		T146	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T1	1		T47	1		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	20		T152	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	16		T187	8		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	8		T168	1		T12	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T47	1		T18	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	1		T152	1		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T224	3		T228	16		T226	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T39	10		T220	16		T73	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17337	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T219	6		T14	6		T238	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T147	4		T155	13		T149	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	1		T134	2		T161	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T16	2		T18	11		T190	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T39	1		T170	2		T249	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T222	12		T60	3		T300	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	4		T13	9		T74	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T5	29		T10	29		T16	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T239	3		T269	13		T57	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T256	4		T255	8		T101	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T38	15		T198	11		T72	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T18	10		T19	10		T13	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T20	14		T154	18		T236	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T198	8		T227	12		T229	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T169	9		T228	7		T264	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	13		T187	13		T167	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	7		T12	7		T161	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T18	5		T149	15		T12	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T227	7		T76	10		T260	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T224	4		T228	12		T334	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T220	13		T73	4		T270	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T17	9		T267	12		T261	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T14	2		T238	10		T301	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T224	3		T228	16		T286	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T39	10		T220	16		T227	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T202	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T265	3		T303	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	1		T62	1		T17	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	2		T178	1		T219	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T4	3		T9	1		T16	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T39	3		T110	14		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T18	1		T190	18		T178	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T146	1		T19	5		T247	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	1		T159	1		T73	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T148	1		T151	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T5	3		T8	5		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	4		T9	5		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T247	4		T13	11		T73	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T168	1		T146	3		T151	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T18	1		T19	8		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	3		T9	20		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	1		T3	16		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T168	1		T12	3		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T47	1		T18	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	1		T6	8		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T224	4		T228	12		T286	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T220	13		T227	7		T73	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T202	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T265	1		T303	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T17	9		T147	4		T149	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	1		T134	2		T14	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	2		T155	13		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T39	1		T162	12		T170	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T18	11		T190	14		T169	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T19	4		T13	9		T74	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T73	9		T254	11		T85	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T224	9		T269	13		T57	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T5	29		T10	29		T16	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T38	15		T72	2		T162	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	10		T73	2		T264	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T198	11		T154	11		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T18	10		T19	10		T198	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T20	14		T154	7		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	13		T227	12		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	7		T161	5		T63	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T18	5		T149	15		T187	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	7		T260	2		T164	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7