Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T20	1		T12	2		T232	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T8	2		T9	5		T146	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T148	1		T198	1		T110	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T198	1		T39	3		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T18	1		T148	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T17	3		T146	4		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	16		T47	1		T18	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	3		T162	1		T170	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	8		T8	5		T19	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	20		T168	2		T19	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T7	1		T19	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	1		T148	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1404	1			T5	3		T10	3		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T156	1		T222	15		T108	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T62	1		T47	1		T17	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T16	11		T149	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T4	3		T9	1		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T4	4		T187	8		T247	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T149	1		T39	1		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T1	1		T155	1		T242	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T20	14		T108	9		T76	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	1		T12	8		T13	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T198	8		T157	2		T238	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T198	11		T39	1		T161	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T18	10		T38	15		T229	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	13		T74	13		T256	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	13		T18	5		T13	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T162	12		T170	2		T207	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	7		T19	10		T147	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T149	2		T190	14		T102	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T19	4		T198	8		T157	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T220	13		T134	2		T73	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T5	29		T10	29		T18	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T222	12		T108	5		T76	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T17	9		T169	8		T73	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	10		T149	15		T154	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	2		T14	2		T63	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T187	13		T157	2		T73	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T149	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T155	13		T242	7		T252	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T244	1		T245	6		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T241	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T246	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T20	1		T108	13		T76	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	2		T9	5		T146	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T198	1		T12	2		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T39	3		T133	1		T232	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T18	1		T148	1		T38	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T17	3		T146	3		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	16		T47	1		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T146	1		T149	1		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	5		T147	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	3		T9	20		T168	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T6	8		T7	1		T19	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T168	1		T151	1		T220	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T147	1		T219	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	1		T148	1		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T5	3		T10	3		T11	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T16	11		T152	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T4	3		T9	1		T16	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T1	1		T4	4		T155	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T244	11		T245	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T20	14		T108	9		T76	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T8	1		T12	8		T81	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T198	8		T157	2		T238	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T39	1		T13	9		T161	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T18	10		T38	15		T229	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T17	13		T198	11		T74	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	13		T18	5		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T149	2		T162	12		T170	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T147	4		T236	11		T13	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T190	14		T164	1		T61	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	7		T19	14		T198	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T220	13		T134	2		T102	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T147	7		T162	3		T167	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T154	11		T222	12		T76	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1069	1			T5	29		T10	29		T18	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T16	10		T154	7		T108	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T16	2		T17	9		T149	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T155	13		T149	15		T187	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7