Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22448

1

T1

3

T2

20

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3444

1

T3

29

T4

7

T8

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20090

1

T1

2

T2

20

T4

10

auto[1]

5802

1

T1

1

T3

29

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	38	1			T19	1		T151	1		T162	4
values[0]	57	1			T272	1		T273	5		T274	28
values[1]	508	1			T6	15		T9	20		T168	1
values[2]	2686	1			T3	29		T5	32		T10	32
values[3]	499	1			T1	1		T4	4		T8	3
values[4]	815	1			T8	5		T47	1		T17	16
values[5]	793	1			T1	1		T4	3		T7	1
values[6]	664	1			T1	1		T9	1		T168	1
values[7]	601	1			T4	3		T16	7		T18	11
values[8]	724	1			T62	1		T146	3		T19	27
values[9]	1251	1			T18	6		T149	3		T187	21
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	709	1			T6	15		T9	20		T168	1
values[1]	2701	1			T3	29		T5	32		T8	3
values[2]	523	1			T1	1		T47	1		T147	5
values[3]	741	1			T4	7		T8	5		T9	5
values[4]	725	1			T1	2		T7	1		T146	1
values[5]	695	1			T9	1		T16	7		T168	1
values[6]	716	1			T4	3		T62	1		T19	9
values[7]	627	1			T146	3		T19	18		T219	13
values[8]	880	1			T149	3		T187	21		T178	1
values[9]	300	1			T18	6		T19	1		T151	1
minimum	17275	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	8		T9	1		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T247	1		T154	8		T63	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T5	32		T10	32		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	14		T8	2		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T47	1		T13	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T147	5		T219	1		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T4	1		T9	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	1		T8	3		T16	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	2		T7	1		T148	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T146	1		T155	14		T190	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T16	3		T168	1		T17	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T18	23		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T19	5		T149	21		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T62	1		T20	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T146	1		T156	1		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	11		T219	1		T12	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T149	3		T178	1		T161	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T187	14		T169	14		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T151	1		T38	16		T276	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T18	6		T19	1		T102	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T247	1		T277	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	7		T9	19		T73	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T63	2		T259	7		T224	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T150	20		T225	24		T251	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	15		T8	1		T39	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T13	10		T167	2		T229	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T219	5		T12	1		T108	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	2		T9	4		T146	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	3		T8	2		T16	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T222	14		T72	2		T164	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T190	17		T227	2		T249	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	4		T17	11		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	5		T226	1		T61	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T19	4		T76	31		T170	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T4	2		T12	1		T220	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T146	2		T232	2		T13	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T19	7		T219	12		T134	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T161	13		T158	12		T170	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T187	7		T14	16		T74	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T38	12		T276	6		T65	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T102	5		T72	16		T61	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T247	3		T277	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T151	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T19	1		T162	4		T276	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T272	1		T273	1		T274	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	8		T9	1		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T247	2		T63	5		T73	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T5	32		T10	32		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	14		T148	1		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	1		T169	9		T13	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	1		T8	2		T147	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T47	1		T146	1		T198	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	3		T17	14		T169	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T4	1		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T16	11		T146	1		T190	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	1		T168	1		T17	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	1		T18	12		T147	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T16	3		T149	21		T157	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	1		T18	11		T20	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T146	1		T19	5		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T62	1		T19	11		T198	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T149	3		T38	16		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	430	1			T18	6		T187	14		T12	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T276	9		T278	7		T279	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T273	4		T274	15		T280	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T6	7		T9	19		T55	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T247	3		T63	2		T73	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1055	1			T150	20		T225	24		T251	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	15		T39	6		T259	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	10		T229	14		T250	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	3		T8	1		T219	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T146	14		T39	2		T72	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T8	2		T17	2		T108	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	2		T9	4		T222	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T16	10		T190	17		T227	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T17	11		T108	11		T110	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	1		T14	5		T226	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	4		T76	31		T255	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	2		T220	15		T161	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T146	2		T19	4		T73	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T19	7		T219	12		T134	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T38	12		T232	2		T13	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T187	7		T102	5		T14	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	8		T9	20		T168	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T247	1		T154	1		T63	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T5	3		T10	3		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	16		T8	2		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	1		T47	1		T13	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T147	1		T219	6		T12	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T4	3		T9	5		T146	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T4	4		T8	5		T16	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	2		T7	1		T148	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T146	1		T155	1		T190	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T16	5		T168	1		T17	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	1		T18	2		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T19	5		T149	2		T275	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T4	3		T62	1		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T146	3		T156	1		T232	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T19	8		T219	13		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T149	1		T178	1		T161	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T187	8		T169	1		T14	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T151	1		T38	13		T276	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T18	1		T19	1		T102	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T247	4		T277	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T6	7		T73	2		T260	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T154	7		T63	2		T224	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T5	29		T10	29		T281	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	13		T8	1		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	10		T167	4		T229	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T147	4		T12	1		T108	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T198	8		T39	1		T224	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T16	10		T17	13		T169	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T222	12		T157	2		T72	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T155	13		T190	14		T227	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T16	2		T17	9		T154	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T18	21		T14	2		T243	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T19	4		T149	19		T76	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	14		T147	7		T198	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	9		T73	4		T224	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T19	10		T12	7		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T149	2		T161	12		T157	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T187	13		T169	13		T74	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T38	15		T276	4		T257	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T18	5		T102	5		T72	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T277	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T151	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T19	1		T162	1		T276	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T272	1		T273	5		T274	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	8		T9	20		T168	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T247	5		T63	5		T73	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T5	3		T10	3		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	16		T148	1		T39	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	1		T169	1		T13	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T4	4		T8	2		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T47	1		T146	15		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T8	5		T17	3		T169	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T4	3		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T16	11		T146	1		T190	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T168	1		T17	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	1		T18	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T16	5		T149	2		T157	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	3		T18	1		T20	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T146	3		T19	5		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T62	1		T19	8		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T149	1		T38	13		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T18	1		T187	8		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T162	3		T276	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T274	12		T282	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	7		T260	2		T256	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T63	2		T73	9		T224	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T5	29		T10	29		T281	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	13		T154	7		T242	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T169	8		T13	10		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	1		T147	4		T12	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T198	8		T39	1		T72	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T17	13		T169	9		T108	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T222	12		T162	12		T238	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	10		T190	14		T227	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T17	9		T154	11		T108	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T18	11		T147	7		T155	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	2		T149	19		T157	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T18	10		T20	14		T198	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T19	4		T73	4		T170	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	10		T198	11		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T149	2		T38	15		T13	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T18	5		T187	13		T12	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7