Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22400

1

T1

1

T2

20

T4

7

auto[ADC_CTRL_FILTER_COND_OUT]

3492

1

T1

2

T3

29

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20163

1

T2

20

T3

29

T4

7

auto[1]

5729

1

T1

3

T4

3

T5

32

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	49	1			T243	14		T283	18		T284	17
values[0]	43	1			T152	1		T262	17		T206	7
values[1]	802	1			T4	3		T8	5		T62	1
values[2]	538	1			T187	21		T190	32		T39	1
values[3]	730	1			T16	21		T47	1		T18	12
values[4]	572	1			T1	1		T4	7		T148	1
values[5]	2668	1			T5	32		T9	1		T10	32
values[6]	706	1			T1	2		T17	21		T20	15
values[7]	734	1			T7	1		T9	5		T168	1
values[8]	558	1			T6	15		T9	20		T19	1
values[9]	1236	1			T3	29		T8	3		T16	7
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	881	1			T4	3		T8	5		T62	1
values[1]	744	1			T16	21		T47	1		T146	1
values[2]	605	1			T4	3		T18	12		T146	15
values[3]	2731	1			T1	1		T4	4		T5	32
values[4]	630	1			T20	15		T149	5		T151	1
values[5]	642	1			T1	2		T7	1		T9	5
values[6]	696	1			T6	15		T168	1		T17	21
values[7]	492	1			T9	20		T146	3		T149	3
values[8]	1012	1			T3	29		T8	3		T47	1
values[9]	203	1			T16	7		T17	16		T38	28
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T62	1		T168	1		T19	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T4	1		T8	3		T147	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T146	1		T187	14		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T16	11		T47	1		T190	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	1		T146	1		T198	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T18	12		T156	1		T227	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T1	1		T4	1		T5	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T178	1		T219	1		T238	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T20	15		T39	2		T169	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T149	5		T151	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	1		T9	1		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	2		T242	8		T229	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	8		T168	1		T17	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T147	5		T220	14		T232	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T149	3		T148	1		T247	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T9	1		T146	1		T12	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T47	1		T18	17		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T3	14		T8	2		T134	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T16	3		T17	14		T38	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T285	1		T264	9		T97	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T19	7		T13	14		T57	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T4	2		T8	2		T222	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T187	7		T72	2		T226	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	10		T190	17		T161	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	2		T146	14		T39	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T227	2		T161	13		T30	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1061	1			T4	3		T150	20		T225	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T219	12		T238	5		T286	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T39	2		T108	12		T73	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T72	16		T241	12		T287	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	4		T158	12		T63	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T229	14		T192	21		T81	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	7		T17	11		T19	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T220	15		T232	2		T14	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T247	3		T12	2		T170	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T9	19		T146	2		T238	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T224	16		T261	5		T202	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T3	15		T8	1		T134	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T16	4		T17	2		T38	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T264	2		T284	9		T288	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T243	14		T284	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T283	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T206	2		T289	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T152	1		T262	1		T290	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T62	1		T168	1		T19	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T4	1		T8	3		T147	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T187	14		T232	1		T291	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T190	15		T39	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T146	2		T39	4		T154	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T16	11		T47	1		T18	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T4	2		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T178	1		T219	1		T238	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T5	32		T9	1		T10	32
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T149	5		T178	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T17	10		T20	15		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	2		T151	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	1		T9	1		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T154	8		T76	11		T259	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	8		T19	1		T149	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	1		T147	5		T12	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T16	3		T47	1		T17	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	430	1			T3	14		T8	2		T146	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T284	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T283	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T206	5		T289	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T262	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T19	7		T13	14		T57	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	2		T8	2		T222	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T187	7		T199	8		T240	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T190	17		T228	15		T292	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T146	14		T39	6		T72	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	10		T227	2		T161	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T4	5		T14	16		T76	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T219	12		T238	5		T286	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T150	20		T225	24		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T245	9		T293	14		T287	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T17	11		T158	12		T63	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T72	16		T229	14		T241	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	4		T19	4		T219	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T76	12		T259	7		T239	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	7		T247	3		T12	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T9	19		T220	15		T232	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T16	4		T17	2		T38	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T3	15		T8	1		T146	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T62	1		T168	1		T19	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T4	3		T8	5		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T146	1		T187	8		T232	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T16	11		T47	1		T190	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	3		T146	15		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T18	1		T156	1		T227	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T1	1		T4	4		T5	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T178	1		T219	13		T238	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T20	1		T39	3		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T149	1		T151	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	1		T9	5		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	2		T242	1		T229	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T6	8		T168	1		T17	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T147	1		T220	16		T232	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T149	1		T148	1		T247	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T9	20		T146	3		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T47	1		T18	2		T19	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T3	16		T8	2		T134	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T16	5		T17	3		T38	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T285	1		T264	3		T97	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T19	10		T13	19		T57	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T147	7		T155	13		T149	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T187	13		T154	11		T72	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T16	10		T190	14		T161	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T198	11		T227	7		T224	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T18	11		T227	12		T161	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T5	29		T10	29		T281	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T238	11		T256	14		T286	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T20	14		T39	1		T169	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T149	4		T72	14		T181	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T63	2		T229	3		T238	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T242	7		T229	14		T257	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	7		T17	9		T19	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T147	4		T220	13		T154	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T149	2		T12	1		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T12	7		T238	10		T254	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T18	15		T224	16		T261	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T3	13		T8	1		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T16	2		T17	13		T38	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T264	8		T97	3		T294	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T243	1		T284	13		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T283	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T206	7		T289	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T152	1		T262	17		T290	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T62	1		T168	1		T19	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T4	3		T8	5		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T187	8		T232	1		T291	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T190	18		T39	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T146	16		T39	10		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T16	11		T47	1		T18	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	1		T4	7		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T178	1		T219	13		T238	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T5	3		T9	1		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T149	1		T178	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T17	12		T20	1		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	2		T151	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T7	1		T9	5		T168	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T154	1		T76	13		T259	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	8		T19	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	20		T147	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T16	5		T47	1		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	397	1			T3	16		T8	2		T146	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T243	13		T284	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T283	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T289	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T19	10		T13	19		T57	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T147	7		T155	13		T149	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T187	13		T81	1		T295	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T190	14		T157	8		T228	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T154	11		T227	7		T72	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T16	10		T18	11		T227	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T198	11		T169	13		T236	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T238	11		T256	14		T286	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T5	29		T10	29		T281	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T149	4		T245	5		T296	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T17	9		T20	14		T63	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T72	14		T181	9		T242	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T19	4		T198	8		T229	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T154	7		T76	10		T239	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T6	7		T149	2		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T147	4		T12	7		T220	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T16	2		T17	13		T18	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T3	13		T8	1		T134	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7