Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25892

1

T1

3

T2

20

T3

29

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20109

1

T1

2

T2

20

T4

7

auto[ADC_CTRL_FILTER_COND_OUT]

5783

1

T1

1

T3

29

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20252

1

T1

2

T2

20

T4

6

auto[1]

5640

1

T1

1

T3

29

T4

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21867

1

T1

3

T2

20

T3

14

auto[1]

4025

1

T3

15

T4

7

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	175	1			T168	1		T148	1		T169	9
values[0]	3	1			T316	1		T308	2		-	-
values[1]	559	1			T4	6		T7	1		T9	1
values[2]	767	1			T4	4		T8	5		T151	1
values[3]	674	1			T18	11		T146	16		T147	5
values[4]	625	1			T6	15		T62	1		T47	1
values[5]	807	1			T9	20		T17	16		T147	8
values[6]	800	1			T1	1		T8	3		T9	5
values[7]	531	1			T3	29		T47	1		T155	14
values[8]	625	1			T16	21		T168	1		T18	6
values[9]	3070	1			T1	2		T5	32		T10	32
minimum	17256	1			T2	20		T8	156		T21	15

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	638	1			T4	6		T17	21		T18	12
values[1]	2712	1			T4	4		T5	32		T8	5
values[2]	800	1			T146	15		T19	18		T147	5
values[3]	582	1			T6	15		T9	20		T62	1
values[4]	835	1			T8	3		T17	16		T147	8
values[5]	773	1			T1	1		T9	5		T155	14
values[6]	541	1			T3	29		T47	1		T39	4
values[7]	632	1			T16	21		T168	1		T18	6
values[8]	814	1			T1	2		T168	1		T190	32
values[9]	121	1			T16	7		T148	1		T169	9
minimum	17444	1			T2	20		T7	1		T8	156

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

3732

1

T3

13

T5

29

T6

7

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	1		T17	10		T187	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	1		T18	12		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	1		T8	3		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1354	1			T5	32		T10	32		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T147	5		T149	5		T198	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T146	1		T19	11		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	8		T9	1		T19	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T62	1		T47	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	2		T147	8		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T17	14		T149	16		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T9	1		T155	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T148	1		T39	1		T232	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T47	1		T39	2		T12	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	14		T232	1		T275	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T168	1		T18	6		T20	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T16	11		T108	6		T224	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	1		T168	1		T198	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T190	15		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T148	1		T169	9		T315	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T16	3		T226	1		T307	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17117	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T7	1		T9	1		T73	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	2		T17	11		T187	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	2		T146	2		T205	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T4	3		T8	2		T219	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1094	1			T150	20		T225	24		T251	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T247	3		T230	4		T85	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T146	14		T19	7		T220	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	7		T9	19		T19	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	16		T317	2		T233	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	1		T13	4		T292	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T17	2		T102	5		T76	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	4		T12	1		T108	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T232	2		T14	5		T72	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T39	2		T12	1		T245	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	15		T76	16		T261	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T38	12		T134	3		T13	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T16	10		T108	11		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T222	14		T73	10		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T190	17		T219	12		T76	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T315	4		T250	9		T31	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T16	4		T226	1		T307	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T132	3		T133	2		T134	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T73	1		T229	14		T30	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T168	1		T148	1		T169	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T163	1		T242	8		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T316	1		T308	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	1		T17	10		T187	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	1		T7	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T8	3		T219	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T151	1		T198	9		T12	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T147	5		T198	12		T247	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T18	11		T146	2		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T6	8		T19	6		T149	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T62	1		T47	1		T19	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	1		T147	8		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T17	14		T149	16		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	1		T8	2		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T39	1		T227	8		T167	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T47	1		T155	14		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	14		T148	1		T232	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T168	1		T18	6		T38	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	11		T108	6		T76	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	1		T20	15		T198	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1469	1			T1	1		T5	32		T10	32
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T224	2		T315	4		T182	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T226	1		T286	9		T318	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T308	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T17	11		T187	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T4	2		T146	2		T73	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	3		T8	2		T219	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T110	13		T255	9		T304	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T247	3		T63	2		T55	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T146	14		T220	15		T161	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	7		T19	4		T39	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T19	7		T72	2		T224	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	19		T13	4		T238	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T17	2		T102	5		T14	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	1		T9	4		T12	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T167	4		T249	14		T261	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T39	2		T12	1		T229	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T3	15		T232	2		T14	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T38	12		T134	3		T13	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	10		T108	11		T76	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T222	14		T73	10		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1262	1			T16	4		T190	17		T150	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T132	3		T133	2		T134	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T4	3		T17	12		T187	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	3		T18	1		T146	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	4		T8	5		T247	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1429	1			T5	3		T10	3		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T147	1		T149	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T146	15		T19	8		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	8		T9	20		T19	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T62	1		T47	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	2		T147	1		T13	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T17	3		T149	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	1		T9	5		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T148	1		T39	1		T232	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	1		T39	3		T12	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	16		T232	1		T275	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T168	1		T18	1		T20	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T16	11		T108	12		T224	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	1		T168	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T1	1		T190	18		T219	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T148	1		T169	1		T315	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T16	5		T226	2		T307	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17286	1			T2	20		T8	156		T21	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	1		T9	1		T73	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T17	9		T187	13		T73	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T18	11		T149	2		T236	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T227	12		T63	2		T167	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1019	1			T5	29		T10	29		T18	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T147	4		T149	4		T198	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T19	10		T220	13		T154	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	7		T19	4		T161	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T302	2		T94	9		T101	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	1		T147	7		T13	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T17	13		T149	15		T102	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T155	13		T12	1		T169	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	2		T227	7		T72	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T39	1		T154	11		T245	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	13		T76	14		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T18	5		T20	14		T38	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T16	10		T108	5		T224	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T198	8		T222	12		T157	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T190	14		T76	12		T162	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T169	8		T315	13		T56	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T16	2		T307	2		T318	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T157	2		T170	2		T91	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T73	2		T229	14		T30	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T168	1		T148	1		T169	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T163	1		T242	1		T226	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T316	1		T308	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	3		T17	12		T187	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	3		T7	1		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	4		T8	5		T219	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T151	1		T198	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T147	1		T198	1		T247	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T18	1		T146	16		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	8		T19	6		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T62	1		T47	1		T19	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	20		T147	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T17	3		T149	1		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	1		T8	2		T9	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T39	1		T227	1		T167	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T47	1		T155	1		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	16		T148	1		T232	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T168	1		T18	1		T38	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T16	11		T108	12		T76	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	1		T20	1		T198	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1613	1			T1	1		T5	3		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17256	1			T2	20		T8	156		T21	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T169	8		T162	12		T224	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T242	7		T286	9		T318	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T17	9		T187	13		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T18	11		T149	2		T73	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T227	12		T167	4		T60	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T198	8		T12	7		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T147	4		T198	11		T63	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T18	10		T220	13		T154	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T6	7		T19	4		T149	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T19	10		T169	9		T72	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T147	7		T13	9		T157	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	13		T149	15		T102	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	1		T12	1		T169	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T227	7		T167	11		T249	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T155	13		T39	1		T154	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T3	13		T14	2		T72	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T18	5		T38	15		T134	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T16	10		T108	5		T76	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T20	14		T198	8		T222	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1118	1			T5	29		T10	29		T16	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22160

1

T1

3

T2

20

T3

16

auto[1]

auto[0]

3732

1

T3

13

T5

29

T6

7