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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.47 98.98 95.69 100.00 100.00 98.18 98.64 90.82


Total test records in report: 912
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T34 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3044715663 Mar 03 12:32:12 PM PST 24 Mar 03 12:32:20 PM PST 24 4191066395 ps
T35 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3655669199 Mar 03 12:31:50 PM PST 24 Mar 03 12:31:59 PM PST 24 2328100450 ps
T792 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4228027338 Mar 03 12:32:40 PM PST 24 Mar 03 12:32:42 PM PST 24 336863429 ps
T112 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1338719853 Mar 03 12:32:05 PM PST 24 Mar 03 12:32:08 PM PST 24 505186287 ps
T793 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2751160868 Mar 03 12:32:17 PM PST 24 Mar 03 12:32:19 PM PST 24 287945909 ps
T794 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.456228714 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:12 PM PST 24 407137756 ps
T128 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4013627013 Mar 03 12:32:57 PM PST 24 Mar 03 12:32:59 PM PST 24 911950565 ps
T113 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.939627511 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:15 PM PST 24 468102918 ps
T795 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2712214246 Mar 03 12:32:18 PM PST 24 Mar 03 12:32:19 PM PST 24 477025574 ps
T40 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1781160201 Mar 03 12:31:53 PM PST 24 Mar 03 12:31:57 PM PST 24 509563760 ps
T41 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2018938963 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:11 PM PST 24 8846472678 ps
T42 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1653815141 Mar 03 12:32:00 PM PST 24 Mar 03 12:32:04 PM PST 24 5101413193 ps
T82 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.29291882 Mar 03 12:32:00 PM PST 24 Mar 03 12:32:02 PM PST 24 448890858 ps
T114 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2368834280 Mar 03 12:32:28 PM PST 24 Mar 03 12:32:30 PM PST 24 432338804 ps
T125 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2508851414 Mar 03 12:31:51 PM PST 24 Mar 03 12:32:01 PM PST 24 2344000799 ps
T796 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1179552185 Mar 03 12:32:11 PM PST 24 Mar 03 12:32:13 PM PST 24 438524967 ps
T36 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.147225207 Mar 03 12:31:58 PM PST 24 Mar 03 12:32:04 PM PST 24 2281667089 ps
T43 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3755172996 Mar 03 12:32:00 PM PST 24 Mar 03 12:32:19 PM PST 24 7742377343 ps
T797 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.132843085 Mar 03 12:33:06 PM PST 24 Mar 03 12:33:07 PM PST 24 461726744 ps
T798 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2247772737 Mar 03 12:31:46 PM PST 24 Mar 03 12:31:48 PM PST 24 416319532 ps
T93 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2950152458 Mar 03 12:32:02 PM PST 24 Mar 03 12:32:05 PM PST 24 515053104 ps
T799 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3467528982 Mar 03 12:32:15 PM PST 24 Mar 03 12:32:17 PM PST 24 407825404 ps
T44 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.14425127 Mar 03 12:31:58 PM PST 24 Mar 03 12:32:01 PM PST 24 394051236 ps
T139 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1757463773 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:08 PM PST 24 4415421011 ps
T129 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.269509726 Mar 03 12:31:40 PM PST 24 Mar 03 12:31:42 PM PST 24 470074219 ps
T800 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2597920679 Mar 03 12:31:35 PM PST 24 Mar 03 12:31:37 PM PST 24 359811106 ps
T801 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.294921093 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:11 PM PST 24 340509893 ps
T802 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3276503345 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:15 PM PST 24 355286231 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1967568953 Mar 03 12:31:41 PM PST 24 Mar 03 12:31:51 PM PST 24 4209005960 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3839679576 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:07 PM PST 24 411417290 ps
T335 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2368804694 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:14 PM PST 24 4160212518 ps
T803 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3294767382 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:35 PM PST 24 910634985 ps
T804 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3314697728 Mar 03 12:32:11 PM PST 24 Mar 03 12:32:13 PM PST 24 377820643 ps
T130 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3985644090 Mar 03 12:32:00 PM PST 24 Mar 03 12:32:02 PM PST 24 747548318 ps
T805 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.157537141 Mar 03 12:32:11 PM PST 24 Mar 03 12:32:13 PM PST 24 465464425 ps
T131 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2752985617 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:30 PM PST 24 8395097466 ps
T141 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.25705445 Mar 03 12:32:04 PM PST 24 Mar 03 12:32:11 PM PST 24 7989045494 ps
T116 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2619483542 Mar 03 12:32:04 PM PST 24 Mar 03 12:32:06 PM PST 24 387145375 ps
T117 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2516092269 Mar 03 12:31:38 PM PST 24 Mar 03 12:32:12 PM PST 24 51832635247 ps
T806 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.964050653 Mar 03 12:31:52 PM PST 24 Mar 03 12:31:53 PM PST 24 404316355 ps
T140 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3495245997 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:20 PM PST 24 8375661403 ps
T142 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.431806624 Mar 03 12:31:59 PM PST 24 Mar 03 12:32:03 PM PST 24 4600981516 ps
T807 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3677087519 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:08 PM PST 24 662101858 ps
T808 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3584208673 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:15 PM PST 24 319605855 ps
T118 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3007810434 Mar 03 12:31:34 PM PST 24 Mar 03 12:31:37 PM PST 24 799151028 ps
T127 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1940899184 Mar 03 12:32:02 PM PST 24 Mar 03 12:32:06 PM PST 24 2315767594 ps
T137 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2223100991 Mar 03 12:32:30 PM PST 24 Mar 03 12:32:33 PM PST 24 604538143 ps
T809 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3566132226 Mar 03 12:31:38 PM PST 24 Mar 03 12:31:40 PM PST 24 338979143 ps
T810 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.169786805 Mar 03 12:32:21 PM PST 24 Mar 03 12:32:23 PM PST 24 495823686 ps
T811 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1356227625 Mar 03 12:31:43 PM PST 24 Mar 03 12:31:46 PM PST 24 412305295 ps
T812 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3005361636 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:16 PM PST 24 2652972489 ps
T119 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1680495282 Mar 03 12:31:51 PM PST 24 Mar 03 12:31:55 PM PST 24 1165408282 ps
T813 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.729672401 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:16 PM PST 24 505322089 ps
T814 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2119504821 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:13 PM PST 24 334093213 ps
T815 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.253716883 Mar 03 12:32:16 PM PST 24 Mar 03 12:32:17 PM PST 24 562142496 ps
T816 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.565151475 Mar 03 12:32:18 PM PST 24 Mar 03 12:32:20 PM PST 24 391278046 ps
T817 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4112189978 Mar 03 12:32:18 PM PST 24 Mar 03 12:32:20 PM PST 24 474978854 ps
T138 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2469383422 Mar 03 12:31:57 PM PST 24 Mar 03 12:32:01 PM PST 24 527012497 ps
T818 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2281822808 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:14 PM PST 24 4310550484 ps
T819 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4251326259 Mar 03 12:32:05 PM PST 24 Mar 03 12:32:12 PM PST 24 4818299474 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.384992521 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:06 PM PST 24 485617002 ps
T120 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3754693853 Mar 03 12:32:01 PM PST 24 Mar 03 12:32:02 PM PST 24 488595308 ps
T821 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1706372884 Mar 03 12:32:17 PM PST 24 Mar 03 12:32:18 PM PST 24 625891555 ps
T135 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2736348119 Mar 03 12:31:39 PM PST 24 Mar 03 12:31:42 PM PST 24 1982839488 ps
T336 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1554755037 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:25 PM PST 24 8103726577 ps
T121 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3548095274 Mar 03 12:31:45 PM PST 24 Mar 03 12:31:46 PM PST 24 412003302 ps
T822 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1889014591 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:12 PM PST 24 409667093 ps
T136 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4048548371 Mar 03 12:31:53 PM PST 24 Mar 03 12:31:57 PM PST 24 610027423 ps
T823 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.386835833 Mar 03 12:32:40 PM PST 24 Mar 03 12:32:46 PM PST 24 1724274392 ps
T824 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1099314930 Mar 03 12:32:18 PM PST 24 Mar 03 12:32:19 PM PST 24 397688688 ps
T825 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3516115762 Mar 03 12:32:38 PM PST 24 Mar 03 12:32:39 PM PST 24 446277397 ps
T122 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2579155844 Mar 03 12:33:01 PM PST 24 Mar 03 12:33:18 PM PST 24 19892506337 ps
T826 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3839868309 Mar 03 12:31:57 PM PST 24 Mar 03 12:32:01 PM PST 24 1331152671 ps
T827 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.808348574 Mar 03 12:32:12 PM PST 24 Mar 03 12:32:15 PM PST 24 484729530 ps
T828 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4073981676 Mar 03 12:31:45 PM PST 24 Mar 03 12:31:57 PM PST 24 4819952754 ps
T829 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2008549298 Mar 03 12:31:59 PM PST 24 Mar 03 12:32:01 PM PST 24 1267208814 ps
T830 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.365852347 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:09 PM PST 24 455924525 ps
T831 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3207104255 Mar 03 12:31:40 PM PST 24 Mar 03 12:31:48 PM PST 24 449136625 ps
T832 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1930659334 Mar 03 12:32:01 PM PST 24 Mar 03 12:32:03 PM PST 24 1032314330 ps
T833 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2629416726 Mar 03 12:31:57 PM PST 24 Mar 03 12:31:59 PM PST 24 2333180913 ps
T834 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.193166113 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:12 PM PST 24 465502609 ps
T835 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2866358800 Mar 03 12:32:24 PM PST 24 Mar 03 12:32:26 PM PST 24 470358687 ps
T123 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1876885557 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:12 PM PST 24 318890162 ps
T836 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2648049759 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:06 PM PST 24 478415857 ps
T837 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4095072276 Mar 03 12:32:11 PM PST 24 Mar 03 12:32:13 PM PST 24 445900838 ps
T838 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1808242735 Mar 03 12:31:51 PM PST 24 Mar 03 12:31:56 PM PST 24 4675228481 ps
T839 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2342961353 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:35 PM PST 24 578013570 ps
T337 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2518990094 Mar 03 12:31:50 PM PST 24 Mar 03 12:31:56 PM PST 24 8787831523 ps
T840 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.659566756 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:08 PM PST 24 494173024 ps
T841 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4258330656 Mar 03 12:32:04 PM PST 24 Mar 03 12:32:06 PM PST 24 579341285 ps
T842 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3586115481 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:15 PM PST 24 402601500 ps
T843 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1736626046 Mar 03 12:33:02 PM PST 24 Mar 03 12:33:06 PM PST 24 494847613 ps
T844 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.752510205 Mar 03 12:32:04 PM PST 24 Mar 03 12:32:07 PM PST 24 535594597 ps
T845 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3254982797 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:06 PM PST 24 305231222 ps
T846 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2714548186 Mar 03 12:32:12 PM PST 24 Mar 03 12:32:13 PM PST 24 522298572 ps
T847 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3629337493 Mar 03 12:32:02 PM PST 24 Mar 03 12:32:05 PM PST 24 2982030931 ps
T848 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1241482528 Mar 03 12:31:44 PM PST 24 Mar 03 12:31:48 PM PST 24 4692352142 ps
T849 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3628412981 Mar 03 12:32:21 PM PST 24 Mar 03 12:32:23 PM PST 24 491927021 ps
T850 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1341945398 Mar 03 12:32:15 PM PST 24 Mar 03 12:32:16 PM PST 24 333123618 ps
T851 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2134767688 Mar 03 12:31:36 PM PST 24 Mar 03 12:31:38 PM PST 24 298957862 ps
T852 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2589838449 Mar 03 12:31:59 PM PST 24 Mar 03 12:32:00 PM PST 24 366751233 ps
T853 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3918898357 Mar 03 12:32:00 PM PST 24 Mar 03 12:32:04 PM PST 24 2800207626 ps
T854 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.65976803 Mar 03 12:32:02 PM PST 24 Mar 03 12:33:56 PM PST 24 52210243307 ps
T855 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.652378367 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:23 PM PST 24 4496686073 ps
T856 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3076901409 Mar 03 12:32:15 PM PST 24 Mar 03 12:32:19 PM PST 24 551716529 ps
T857 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3529724083 Mar 03 12:31:46 PM PST 24 Mar 03 12:31:53 PM PST 24 480075743 ps
T858 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2865398745 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:12 PM PST 24 284067301 ps
T124 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4187358387 Mar 03 12:32:12 PM PST 24 Mar 03 12:32:14 PM PST 24 345092475 ps
T859 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3672817282 Mar 03 12:31:55 PM PST 24 Mar 03 12:32:00 PM PST 24 4551173688 ps
T860 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.950987853 Mar 03 12:32:01 PM PST 24 Mar 03 12:32:03 PM PST 24 522032187 ps
T861 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3985501355 Mar 03 12:32:12 PM PST 24 Mar 03 12:32:14 PM PST 24 2834523234 ps
T862 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2534881912 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:13 PM PST 24 392209250 ps
T863 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1908669095 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:09 PM PST 24 572601639 ps
T864 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.852511569 Mar 03 12:31:56 PM PST 24 Mar 03 12:32:00 PM PST 24 437330016 ps
T865 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4052511098 Mar 03 12:31:54 PM PST 24 Mar 03 12:32:41 PM PST 24 27428331505 ps
T866 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.24402031 Mar 03 12:32:05 PM PST 24 Mar 03 12:32:09 PM PST 24 435634281 ps
T867 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.444617306 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:28 PM PST 24 7945019587 ps
T868 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2584346668 Mar 03 12:31:50 PM PST 24 Mar 03 12:31:55 PM PST 24 838724172 ps
T869 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1629529421 Mar 03 12:32:11 PM PST 24 Mar 03 12:32:22 PM PST 24 7954477554 ps
T870 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2209823682 Mar 03 12:32:19 PM PST 24 Mar 03 12:32:20 PM PST 24 521025412 ps
T871 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3099166359 Mar 03 12:32:10 PM PST 24 Mar 03 12:32:12 PM PST 24 429770406 ps
T872 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.71524866 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:12 PM PST 24 501034927 ps
T873 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1303374974 Mar 03 12:32:02 PM PST 24 Mar 03 12:32:04 PM PST 24 422818593 ps
T874 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3813726962 Mar 03 12:31:41 PM PST 24 Mar 03 12:31:43 PM PST 24 465260201 ps
T875 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1119101479 Mar 03 12:32:10 PM PST 24 Mar 03 12:32:13 PM PST 24 437210379 ps
T876 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.997672315 Mar 03 12:32:07 PM PST 24 Mar 03 12:32:10 PM PST 24 435061143 ps
T877 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4294560097 Mar 03 12:32:21 PM PST 24 Mar 03 12:32:22 PM PST 24 504670796 ps
T878 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3633439073 Mar 03 12:32:22 PM PST 24 Mar 03 12:32:26 PM PST 24 2519112088 ps
T879 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1789983123 Mar 03 12:32:07 PM PST 24 Mar 03 12:32:08 PM PST 24 359338000 ps
T880 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3164581750 Mar 03 12:32:05 PM PST 24 Mar 03 12:32:06 PM PST 24 478250975 ps
T881 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.821222149 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:09 PM PST 24 343149924 ps
T882 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.957506889 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:35 PM PST 24 328878117 ps
T883 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3890744758 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:15 PM PST 24 451481864 ps
T884 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2819088214 Mar 03 12:31:35 PM PST 24 Mar 03 12:31:39 PM PST 24 1257106727 ps
T885 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1715874123 Mar 03 12:32:10 PM PST 24 Mar 03 12:32:12 PM PST 24 342081951 ps
T886 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.942343216 Mar 03 12:31:36 PM PST 24 Mar 03 12:31:40 PM PST 24 1075474024 ps
T887 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4230718568 Mar 03 12:31:38 PM PST 24 Mar 03 12:32:00 PM PST 24 8342774959 ps
T888 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1809983121 Mar 03 12:32:02 PM PST 24 Mar 03 12:32:07 PM PST 24 4003530575 ps
T889 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.695747296 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:20 PM PST 24 4356705417 ps
T890 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1941547523 Mar 03 12:33:04 PM PST 24 Mar 03 12:33:06 PM PST 24 498624205 ps
T891 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.665280588 Mar 03 12:31:46 PM PST 24 Mar 03 12:31:48 PM PST 24 465246293 ps
T892 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1432995062 Mar 03 12:32:11 PM PST 24 Mar 03 12:32:13 PM PST 24 452188479 ps
T893 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3289949613 Mar 03 12:32:09 PM PST 24 Mar 03 12:32:13 PM PST 24 494315173 ps
T894 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4246995392 Mar 03 12:31:51 PM PST 24 Mar 03 12:31:55 PM PST 24 3197754574 ps
T895 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3453136313 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:08 PM PST 24 498530780 ps
T896 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.621337658 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:06 PM PST 24 2278884462 ps
T897 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1918687096 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:07 PM PST 24 456435006 ps
T898 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1031721392 Mar 03 12:32:12 PM PST 24 Mar 03 12:32:34 PM PST 24 5175919944 ps
T899 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.947153909 Mar 03 12:31:32 PM PST 24 Mar 03 12:31:35 PM PST 24 458520472 ps
T900 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3723291686 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:15 PM PST 24 294550018 ps
T901 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.164664188 Mar 03 12:31:31 PM PST 24 Mar 03 12:31:49 PM PST 24 572654369 ps
T902 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1204253385 Mar 03 12:32:02 PM PST 24 Mar 03 12:32:06 PM PST 24 365919994 ps
T903 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3274998969 Mar 03 12:32:03 PM PST 24 Mar 03 12:32:07 PM PST 24 4208929122 ps
T904 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2970108981 Mar 03 12:32:05 PM PST 24 Mar 03 12:32:06 PM PST 24 383568455 ps
T905 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3257890365 Mar 03 12:31:47 PM PST 24 Mar 03 12:31:48 PM PST 24 466062090 ps
T906 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3924625918 Mar 03 12:32:13 PM PST 24 Mar 03 12:32:15 PM PST 24 339679822 ps
T907 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.982389956 Mar 03 12:32:06 PM PST 24 Mar 03 12:32:07 PM PST 24 472479873 ps
T908 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.971452941 Mar 03 12:32:01 PM PST 24 Mar 03 12:32:03 PM PST 24 516400746 ps
T909 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1469560846 Mar 03 12:31:38 PM PST 24 Mar 03 12:31:41 PM PST 24 792718189 ps
T910 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3331005513 Mar 03 12:31:33 PM PST 24 Mar 03 12:31:37 PM PST 24 590235406 ps
T911 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2745633880 Mar 03 12:32:08 PM PST 24 Mar 03 12:32:11 PM PST 24 525076623 ps
T912 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1990158712 Mar 03 12:32:05 PM PST 24 Mar 03 12:32:07 PM PST 24 514492383 ps

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3437820831
Short name T8
Test name
Test status
Simulation time 101260884328 ps
CPU time 354.98 seconds
Started Mar 03 04:16:38 PM PST 24
Finished Mar 03 04:22:33 PM PST 24
Peak memory 217796 kb
Host smart-ae4c2c29-0265-4aca-96da-875d1763fd06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437820831 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3437820831
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.373643812
Short name T18
Test name
Test status
Simulation time 493798944815 ps
CPU time 1124.03 seconds
Started Mar 03 04:19:21 PM PST 24
Finished Mar 03 04:38:05 PM PST 24
Peak memory 200900 kb
Host smart-fdae2709-17b4-48e5-9e59-c0deaebc3cf9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373643812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.373643812
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.858373487
Short name T9
Test name
Test status
Simulation time 489017683343 ps
CPU time 282.23 seconds
Started Mar 03 04:20:56 PM PST 24
Finished Mar 03 04:25:39 PM PST 24
Peak memory 200932 kb
Host smart-ab7fa7ca-ee99-4198-9d30-c917b493fc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858373487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.858373487
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.359866416
Short name T73
Test name
Test status
Simulation time 262859973416 ps
CPU time 319.47 seconds
Started Mar 03 04:23:27 PM PST 24
Finished Mar 03 04:28:47 PM PST 24
Peak memory 217352 kb
Host smart-9d7d9c85-bce9-4901-b805-54f0dd80a159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359866416 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.359866416
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2932496973
Short name T149
Test name
Test status
Simulation time 500770288380 ps
CPU time 303.78 seconds
Started Mar 03 04:23:16 PM PST 24
Finished Mar 03 04:28:20 PM PST 24
Peak memory 200984 kb
Host smart-38637762-17eb-4db7-a85a-1b2df23815a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932496973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2932496973
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3260464915
Short name T224
Test name
Test status
Simulation time 496607217042 ps
CPU time 314.52 seconds
Started Mar 03 04:17:44 PM PST 24
Finished Mar 03 04:22:59 PM PST 24
Peak memory 201000 kb
Host smart-279095e1-b966-4e01-be2f-3abc9fa329f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260464915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3260464915
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.28516282
Short name T76
Test name
Test status
Simulation time 536912503003 ps
CPU time 632.2 seconds
Started Mar 03 04:20:47 PM PST 24
Finished Mar 03 04:31:19 PM PST 24
Peak memory 200968 kb
Host smart-c0df0fa7-f963-4a83-89d4-c4fd8a3115ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28516282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.28516282
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.2333403870
Short name T39
Test name
Test status
Simulation time 291639939340 ps
CPU time 122.98 seconds
Started Mar 03 04:21:17 PM PST 24
Finished Mar 03 04:23:21 PM PST 24
Peak memory 209648 kb
Host smart-2f6fde06-30e0-4206-834b-dbbe79e1888f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333403870 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.2333403870
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2254038677
Short name T67
Test name
Test status
Simulation time 334954774973 ps
CPU time 205.08 seconds
Started Mar 03 04:19:28 PM PST 24
Finished Mar 03 04:22:53 PM PST 24
Peak memory 209264 kb
Host smart-59955fa0-4c19-4119-a545-f080cfc36715
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254038677 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2254038677
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3918705076
Short name T133
Test name
Test status
Simulation time 26140438747 ps
CPU time 51.61 seconds
Started Mar 03 04:22:41 PM PST 24
Finished Mar 03 04:23:34 PM PST 24
Peak memory 209672 kb
Host smart-dbf6b9d7-664a-450f-82f2-bc0519d1a6ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918705076 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3918705076
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2369808404
Short name T238
Test name
Test status
Simulation time 492110223961 ps
CPU time 288.98 seconds
Started Mar 03 04:23:10 PM PST 24
Finished Mar 03 04:28:00 PM PST 24
Peak memory 200956 kb
Host smart-894dc6cb-9f38-430e-91d5-428be544ec8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369808404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2369808404
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1916703078
Short name T16
Test name
Test status
Simulation time 336500555798 ps
CPU time 218.95 seconds
Started Mar 03 04:15:53 PM PST 24
Finished Mar 03 04:19:32 PM PST 24
Peak memory 200964 kb
Host smart-d506d07a-18db-42a3-ac91-bdac4e731194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916703078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1916703078
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1781160201
Short name T40
Test name
Test status
Simulation time 509563760 ps
CPU time 3.57 seconds
Started Mar 03 12:31:53 PM PST 24
Finished Mar 03 12:31:57 PM PST 24
Peak memory 217496 kb
Host smart-702dfa7a-8b71-4fa6-b4b0-b1579d79a8c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781160201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1781160201
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1259837878
Short name T229
Test name
Test status
Simulation time 494254726370 ps
CPU time 119.48 seconds
Started Mar 03 04:19:21 PM PST 24
Finished Mar 03 04:21:20 PM PST 24
Peak memory 200892 kb
Host smart-0e6ac90e-9026-4c2d-9108-eeb01e5404ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259837878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1259837878
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.4193650332
Short name T14
Test name
Test status
Simulation time 515410128469 ps
CPU time 1478.38 seconds
Started Mar 03 04:21:29 PM PST 24
Finished Mar 03 04:46:09 PM PST 24
Peak memory 209552 kb
Host smart-754ac7b6-4da8-40ee-8372-0bf47ca3cfe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193650332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.4193650332
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2609171559
Short name T19
Test name
Test status
Simulation time 492282190475 ps
CPU time 1192.12 seconds
Started Mar 03 04:20:17 PM PST 24
Finished Mar 03 04:40:10 PM PST 24
Peak memory 200976 kb
Host smart-da93f573-cb6b-44d6-a9f6-dda848b78b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609171559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2609171559
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1338719853
Short name T112
Test name
Test status
Simulation time 505186287 ps
CPU time 1.98 seconds
Started Mar 03 12:32:05 PM PST 24
Finished Mar 03 12:32:08 PM PST 24
Peak memory 200800 kb
Host smart-683bdc4c-c3ea-432c-89ba-7b2f7cbca273
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338719853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1338719853
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2983817474
Short name T45
Test name
Test status
Simulation time 381985948 ps
CPU time 1.01 seconds
Started Mar 03 04:18:38 PM PST 24
Finished Mar 03 04:18:40 PM PST 24
Peak memory 200696 kb
Host smart-330cb5b8-fe06-4ba5-90d7-975995fc70ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983817474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2983817474
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2063793473
Short name T255
Test name
Test status
Simulation time 331976231121 ps
CPU time 226.23 seconds
Started Mar 03 04:20:39 PM PST 24
Finished Mar 03 04:24:25 PM PST 24
Peak memory 200908 kb
Host smart-d0e76537-7fd1-4969-80e3-8ea8a778301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063793473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2063793473
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.285634518
Short name T48
Test name
Test status
Simulation time 3774077522 ps
CPU time 7.05 seconds
Started Mar 03 04:15:15 PM PST 24
Finished Mar 03 04:15:23 PM PST 24
Peak memory 216052 kb
Host smart-6489678e-cd83-43cc-84fa-920f9216cdde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285634518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.285634518
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.4151892013
Short name T72
Test name
Test status
Simulation time 331019978813 ps
CPU time 588.69 seconds
Started Mar 03 04:23:20 PM PST 24
Finished Mar 03 04:33:09 PM PST 24
Peak memory 200948 kb
Host smart-91d170fa-eec7-4831-82fc-bbec086e7034
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151892013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.4151892013
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.4263592291
Short name T169
Test name
Test status
Simulation time 519964196708 ps
CPU time 1214.13 seconds
Started Mar 03 04:18:27 PM PST 24
Finished Mar 03 04:38:41 PM PST 24
Peak memory 200904 kb
Host smart-95eb09e2-3d8c-4b58-bb63-079425dc84cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263592291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.4263592291
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2207667463
Short name T265
Test name
Test status
Simulation time 147940862399 ps
CPU time 212.51 seconds
Started Mar 03 04:16:49 PM PST 24
Finished Mar 03 04:20:22 PM PST 24
Peak memory 209236 kb
Host smart-1d6435f4-4ca7-47d0-812a-d05057fbf819
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207667463 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2207667463
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3099720162
Short name T276
Test name
Test status
Simulation time 653918506547 ps
CPU time 1439.56 seconds
Started Mar 03 04:17:44 PM PST 24
Finished Mar 03 04:41:43 PM PST 24
Peak memory 200868 kb
Host smart-ce1d8da3-e49a-4939-9e70-6e6e9619de29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099720162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3099720162
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2854564892
Short name T4
Test name
Test status
Simulation time 490335836771 ps
CPU time 595.59 seconds
Started Mar 03 04:15:40 PM PST 24
Finished Mar 03 04:25:36 PM PST 24
Peak memory 200968 kb
Host smart-3e3e19dd-1a07-4791-81b0-5e9deabc8e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854564892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2854564892
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2436405087
Short name T247
Test name
Test status
Simulation time 327329677917 ps
CPU time 754.92 seconds
Started Mar 03 04:19:26 PM PST 24
Finished Mar 03 04:32:01 PM PST 24
Peak memory 200908 kb
Host smart-6552915c-3707-4f50-ac3b-5596a15794e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436405087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2436405087
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1377182691
Short name T108
Test name
Test status
Simulation time 331568492831 ps
CPU time 195.01 seconds
Started Mar 03 04:15:16 PM PST 24
Finished Mar 03 04:18:31 PM PST 24
Peak memory 200892 kb
Host smart-77d2f9cf-be97-4937-a862-f130f2b713a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377182691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1377182691
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3751877715
Short name T311
Test name
Test status
Simulation time 326670736631 ps
CPU time 263.5 seconds
Started Mar 03 04:15:30 PM PST 24
Finished Mar 03 04:19:54 PM PST 24
Peak memory 200904 kb
Host smart-c3d38525-8ff9-4110-a9f5-601cb061129b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751877715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3751877715
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1643775684
Short name T274
Test name
Test status
Simulation time 489657076192 ps
CPU time 287.33 seconds
Started Mar 03 04:17:20 PM PST 24
Finished Mar 03 04:22:08 PM PST 24
Peak memory 200960 kb
Host smart-3b4c4a2c-25b5-418d-802a-138eee8f5ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643775684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1643775684
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.4267430002
Short name T245
Test name
Test status
Simulation time 496112148175 ps
CPU time 259.97 seconds
Started Mar 03 04:21:08 PM PST 24
Finished Mar 03 04:25:28 PM PST 24
Peak memory 200904 kb
Host smart-b6ae385e-443d-4a49-9d82-a9834c4dcf1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267430002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.4267430002
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3693405470
Short name T294
Test name
Test status
Simulation time 327511718345 ps
CPU time 206.93 seconds
Started Mar 03 04:19:21 PM PST 24
Finished Mar 03 04:22:48 PM PST 24
Peak memory 200904 kb
Host smart-3af7a77f-f0be-479e-986e-5babaf4264ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693405470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3693405470
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2018938963
Short name T41
Test name
Test status
Simulation time 8846472678 ps
CPU time 6.65 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:11 PM PST 24
Peak memory 201068 kb
Host smart-d1ae5fb3-588b-4576-89ec-637997fd21db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018938963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2018938963
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1149569249
Short name T152
Test name
Test status
Simulation time 492582495306 ps
CPU time 235.4 seconds
Started Mar 03 04:19:26 PM PST 24
Finished Mar 03 04:23:21 PM PST 24
Peak memory 200916 kb
Host smart-dda94bf5-c792-494d-be40-7dafea56967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149569249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1149569249
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2197995509
Short name T202
Test name
Test status
Simulation time 524232411726 ps
CPU time 737.4 seconds
Started Mar 03 04:18:35 PM PST 24
Finished Mar 03 04:30:53 PM PST 24
Peak memory 216956 kb
Host smart-3d56141d-c4db-4170-8128-8e8e6bd4bbf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197995509 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2197995509
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.649190394
Short name T150
Test name
Test status
Simulation time 329863193962 ps
CPU time 151.9 seconds
Started Mar 03 04:20:03 PM PST 24
Finished Mar 03 04:22:35 PM PST 24
Peak memory 200896 kb
Host smart-251bb8f8-ee5b-4a1a-b24a-61aa86c22d62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=649190394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.649190394
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1040999129
Short name T134
Test name
Test status
Simulation time 140917116372 ps
CPU time 377.06 seconds
Started Mar 03 04:22:19 PM PST 24
Finished Mar 03 04:28:36 PM PST 24
Peak memory 209712 kb
Host smart-a41f2532-e9a9-49f7-b422-6a75feff671e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040999129 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1040999129
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.172827811
Short name T242
Test name
Test status
Simulation time 211346167867 ps
CPU time 138.26 seconds
Started Mar 03 04:18:06 PM PST 24
Finished Mar 03 04:20:25 PM PST 24
Peak memory 200880 kb
Host smart-c9525686-9611-4d7e-9b1e-f0c4e0f6f3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172827811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
172827811
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.356346664
Short name T147
Test name
Test status
Simulation time 326686993948 ps
CPU time 218.65 seconds
Started Mar 03 04:15:56 PM PST 24
Finished Mar 03 04:19:36 PM PST 24
Peak memory 200908 kb
Host smart-1f9ee191-7ca1-4432-a5f6-da31e27512c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356346664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.356346664
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2925983369
Short name T3
Test name
Test status
Simulation time 165951674471 ps
CPU time 379.02 seconds
Started Mar 03 04:21:32 PM PST 24
Finished Mar 03 04:27:52 PM PST 24
Peak memory 200936 kb
Host smart-347f2e06-453d-4c13-9069-f48656f84c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925983369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2925983369
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.74759888
Short name T240
Test name
Test status
Simulation time 497425105194 ps
CPU time 166.2 seconds
Started Mar 03 04:22:09 PM PST 24
Finished Mar 03 04:24:55 PM PST 24
Peak memory 200960 kb
Host smart-75a5681a-e474-438b-b681-5a242cfbc273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74759888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.74759888
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2652416104
Short name T284
Test name
Test status
Simulation time 322291121868 ps
CPU time 573.27 seconds
Started Mar 03 04:17:28 PM PST 24
Finished Mar 03 04:27:02 PM PST 24
Peak memory 200928 kb
Host smart-755fbf6b-99d2-4ecf-9ac7-043059ef3363
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652416104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2652416104
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.510098552
Short name T289
Test name
Test status
Simulation time 327264421072 ps
CPU time 180.39 seconds
Started Mar 03 04:16:46 PM PST 24
Finished Mar 03 04:19:47 PM PST 24
Peak memory 200976 kb
Host smart-21e432e2-d39e-4ebf-a04a-2fae515dbf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510098552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.510098552
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.220117708
Short name T256
Test name
Test status
Simulation time 501631569935 ps
CPU time 186 seconds
Started Mar 03 04:17:29 PM PST 24
Finished Mar 03 04:20:36 PM PST 24
Peak memory 200904 kb
Host smart-edfbc4cc-73a0-4982-abd7-8b0250bdfcad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220117708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_
wakeup.220117708
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1646910925
Short name T308
Test name
Test status
Simulation time 499745035403 ps
CPU time 135.19 seconds
Started Mar 03 04:18:36 PM PST 24
Finished Mar 03 04:20:51 PM PST 24
Peak memory 200956 kb
Host smart-9463c023-2c9d-4211-9470-b34860d3d895
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646910925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1646910925
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.672318272
Short name T258
Test name
Test status
Simulation time 325201578980 ps
CPU time 751.65 seconds
Started Mar 03 04:19:33 PM PST 24
Finished Mar 03 04:32:05 PM PST 24
Peak memory 200968 kb
Host smart-fc9ce040-d96a-4a45-a05d-ba4b0d1ac628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672318272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.672318272
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2020579360
Short name T277
Test name
Test status
Simulation time 325054148883 ps
CPU time 189.25 seconds
Started Mar 03 04:19:56 PM PST 24
Finished Mar 03 04:23:05 PM PST 24
Peak memory 200968 kb
Host smart-e894ff6a-d984-4d53-80bd-cc7588b29053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020579360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2020579360
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3809993497
Short name T65
Test name
Test status
Simulation time 139902666826 ps
CPU time 158.64 seconds
Started Mar 03 04:22:55 PM PST 24
Finished Mar 03 04:25:35 PM PST 24
Peak memory 209160 kb
Host smart-bf17cd5c-11a7-498d-835e-4abd311ad166
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809993497 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3809993497
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2736348119
Short name T135
Test name
Test status
Simulation time 1982839488 ps
CPU time 1.92 seconds
Started Mar 03 12:31:39 PM PST 24
Finished Mar 03 12:31:42 PM PST 24
Peak memory 200148 kb
Host smart-575ec7cc-d3a8-4847-b728-2c881161a72b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736348119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2736348119
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1213931025
Short name T304
Test name
Test status
Simulation time 484680865062 ps
CPU time 520.95 seconds
Started Mar 03 04:18:23 PM PST 24
Finished Mar 03 04:27:05 PM PST 24
Peak memory 200984 kb
Host smart-eb6a183b-11c8-4a6b-be10-ad829342ebff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213931025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1213931025
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3836015543
Short name T218
Test name
Test status
Simulation time 170819971044 ps
CPU time 422.09 seconds
Started Mar 03 04:22:03 PM PST 24
Finished Mar 03 04:29:06 PM PST 24
Peak memory 200928 kb
Host smart-69809342-c6ae-4f99-b71d-3fb5ec1cc5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836015543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3836015543
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2294844013
Short name T283
Test name
Test status
Simulation time 162393157701 ps
CPU time 109.87 seconds
Started Mar 03 04:17:32 PM PST 24
Finished Mar 03 04:19:22 PM PST 24
Peak memory 200960 kb
Host smart-de08f196-9836-4961-8172-2c706722a1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294844013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2294844013
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1929488100
Short name T297
Test name
Test status
Simulation time 215850585749 ps
CPU time 77.36 seconds
Started Mar 03 04:19:08 PM PST 24
Finished Mar 03 04:20:25 PM PST 24
Peak memory 201208 kb
Host smart-facf9f06-3c71-4641-b8a5-8b6085cb0d13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929488100 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1929488100
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.324756803
Short name T292
Test name
Test status
Simulation time 491177907706 ps
CPU time 158.21 seconds
Started Mar 03 04:19:14 PM PST 24
Finished Mar 03 04:21:52 PM PST 24
Peak memory 200944 kb
Host smart-7a82ec28-1b2f-4ccd-91d2-53534b081751
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324756803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.324756803
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3611795944
Short name T13
Test name
Test status
Simulation time 496818817643 ps
CPU time 858.95 seconds
Started Mar 03 04:19:40 PM PST 24
Finished Mar 03 04:34:00 PM PST 24
Peak memory 200884 kb
Host smart-33747b56-a421-49b0-b835-23929a62e8b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611795944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3611795944
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2641796826
Short name T241
Test name
Test status
Simulation time 327119668586 ps
CPU time 109.32 seconds
Started Mar 03 04:20:15 PM PST 24
Finished Mar 03 04:22:04 PM PST 24
Peak memory 200984 kb
Host smart-ee085aa2-b0e0-4e36-a46f-b2550dc4aeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641796826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2641796826
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1791086813
Short name T257
Test name
Test status
Simulation time 490759447596 ps
CPU time 1039.8 seconds
Started Mar 03 04:21:50 PM PST 24
Finished Mar 03 04:39:10 PM PST 24
Peak memory 200904 kb
Host smart-0f77f3d0-1e22-4386-a675-af7907f33392
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791086813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1791086813
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2670066973
Short name T77
Test name
Test status
Simulation time 126192166426 ps
CPU time 669.22 seconds
Started Mar 03 04:17:31 PM PST 24
Finished Mar 03 04:28:41 PM PST 24
Peak memory 201340 kb
Host smart-02a9a917-f35c-4c64-af85-182872291d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670066973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2670066973
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2579155844
Short name T122
Test name
Test status
Simulation time 19892506337 ps
CPU time 16.77 seconds
Started Mar 03 12:33:01 PM PST 24
Finished Mar 03 12:33:18 PM PST 24
Peak memory 201092 kb
Host smart-f161a02a-032d-4bdd-b051-2b9fe49f4001
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579155844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2579155844
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3628127237
Short name T246
Test name
Test status
Simulation time 327225834689 ps
CPU time 364.92 seconds
Started Mar 03 04:18:56 PM PST 24
Finished Mar 03 04:25:01 PM PST 24
Peak memory 200920 kb
Host smart-13d49194-f86b-417d-9741-7b15d06e5df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628127237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3628127237
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2086939639
Short name T237
Test name
Test status
Simulation time 329602648746 ps
CPU time 325.2 seconds
Started Mar 03 04:19:50 PM PST 24
Finished Mar 03 04:25:15 PM PST 24
Peak memory 200996 kb
Host smart-8e81947a-1f1d-406c-a5b4-5800120a585d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086939639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2086939639
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1665852655
Short name T313
Test name
Test status
Simulation time 323100173871 ps
CPU time 713.73 seconds
Started Mar 03 04:16:14 PM PST 24
Finished Mar 03 04:28:08 PM PST 24
Peak memory 200880 kb
Host smart-2eadfe31-2c47-4b3b-b8cf-866f52c9ab98
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665852655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1665852655
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2683416244
Short name T91
Test name
Test status
Simulation time 165208511828 ps
CPU time 189.39 seconds
Started Mar 03 04:22:43 PM PST 24
Finished Mar 03 04:25:53 PM PST 24
Peak memory 200956 kb
Host smart-1ff5f9b9-0546-4f93-9945-f389b0a6c049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683416244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2683416244
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.3973135427
Short name T206
Test name
Test status
Simulation time 53864384625 ps
CPU time 125.61 seconds
Started Mar 03 04:23:03 PM PST 24
Finished Mar 03 04:25:09 PM PST 24
Peak memory 209292 kb
Host smart-b19da8ac-2b2d-4ba5-96a8-8da8ece54bcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973135427 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.3973135427
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2518990094
Short name T337
Test name
Test status
Simulation time 8787831523 ps
CPU time 5.78 seconds
Started Mar 03 12:31:50 PM PST 24
Finished Mar 03 12:31:56 PM PST 24
Peak memory 200824 kb
Host smart-686e7e7a-47f8-418e-bbb9-68f2626dd853
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518990094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2518990094
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1404747237
Short name T179
Test name
Test status
Simulation time 164107586183 ps
CPU time 24.33 seconds
Started Mar 03 04:17:32 PM PST 24
Finished Mar 03 04:17:56 PM PST 24
Peak memory 200900 kb
Host smart-466cc396-92e8-4fcd-9408-8fc670cfe880
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404747237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1404747237
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1963287921
Short name T318
Test name
Test status
Simulation time 165949580551 ps
CPU time 31.68 seconds
Started Mar 03 04:17:55 PM PST 24
Finished Mar 03 04:18:26 PM PST 24
Peak memory 200912 kb
Host smart-3026b944-446c-4dc9-a258-50212d3bb8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963287921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1963287921
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2592496378
Short name T216
Test name
Test status
Simulation time 105971345047 ps
CPU time 531.3 seconds
Started Mar 03 04:17:56 PM PST 24
Finished Mar 03 04:26:48 PM PST 24
Peak memory 201396 kb
Host smart-3ec83f33-9711-439a-98d3-04bf15c55b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592496378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2592496378
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1355249773
Short name T151
Test name
Test status
Simulation time 489080835171 ps
CPU time 342.7 seconds
Started Mar 03 04:17:57 PM PST 24
Finished Mar 03 04:23:40 PM PST 24
Peak memory 201164 kb
Host smart-7c2a2361-d4c2-432d-b3fe-89f31adee408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355249773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1355249773
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.303505090
Short name T253
Test name
Test status
Simulation time 506074945188 ps
CPU time 313.14 seconds
Started Mar 03 04:19:38 PM PST 24
Finished Mar 03 04:24:51 PM PST 24
Peak memory 200980 kb
Host smart-1279cbc3-5045-422b-a608-6341b695d7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303505090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.303505090
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1258676375
Short name T305
Test name
Test status
Simulation time 497159223012 ps
CPU time 581.88 seconds
Started Mar 03 04:21:06 PM PST 24
Finished Mar 03 04:30:48 PM PST 24
Peak memory 200964 kb
Host smart-18544c05-6d1a-469f-b611-c5c9f15d0c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258676375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1258676375
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3019168692
Short name T22
Test name
Test status
Simulation time 73233074819 ps
CPU time 425.82 seconds
Started Mar 03 04:21:24 PM PST 24
Finished Mar 03 04:28:30 PM PST 24
Peak memory 201276 kb
Host smart-aff26007-8451-4449-b241-5be829e67c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019168692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3019168692
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.990485674
Short name T315
Test name
Test status
Simulation time 165100055160 ps
CPU time 93.72 seconds
Started Mar 03 04:22:09 PM PST 24
Finished Mar 03 04:23:43 PM PST 24
Peak memory 200976 kb
Host smart-cd8a23d2-0340-4d45-a352-743d56876b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990485674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.990485674
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.2775597663
Short name T288
Test name
Test status
Simulation time 360806285134 ps
CPU time 829.67 seconds
Started Mar 03 04:17:22 PM PST 24
Finished Mar 03 04:31:12 PM PST 24
Peak memory 200956 kb
Host smart-eec3aaa2-a0c4-42af-ae80-1883ce50ef5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775597663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
2775597663
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1139174940
Short name T215
Test name
Test status
Simulation time 238773134840 ps
CPU time 805.78 seconds
Started Mar 03 04:15:16 PM PST 24
Finished Mar 03 04:28:42 PM PST 24
Peak memory 209592 kb
Host smart-1e89a008-50cf-4bea-bfb3-fddb5da24053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139174940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1139174940
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2810727362
Short name T244
Test name
Test status
Simulation time 166516674445 ps
CPU time 215.89 seconds
Started Mar 03 04:18:01 PM PST 24
Finished Mar 03 04:21:37 PM PST 24
Peak memory 200916 kb
Host smart-5dec27fc-3f85-4378-afbe-e735373f0a89
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810727362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2810727362
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.991382424
Short name T29
Test name
Test status
Simulation time 72075801181 ps
CPU time 289.79 seconds
Started Mar 03 04:18:29 PM PST 24
Finished Mar 03 04:23:19 PM PST 24
Peak memory 201332 kb
Host smart-be45e5c2-7863-492f-8ba8-2b7a015bd4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991382424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.991382424
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3675252410
Short name T249
Test name
Test status
Simulation time 327401389464 ps
CPU time 232.34 seconds
Started Mar 03 04:15:51 PM PST 24
Finished Mar 03 04:19:45 PM PST 24
Peak memory 200880 kb
Host smart-b2f92fc4-0e17-433b-bd9c-964798d1409e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675252410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3675252410
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1839252314
Short name T27
Test name
Test status
Simulation time 132554447566 ps
CPU time 679.1 seconds
Started Mar 03 04:19:27 PM PST 24
Finished Mar 03 04:30:46 PM PST 24
Peak memory 201412 kb
Host smart-52858451-e96e-4eb5-b5e8-1adeba2c4f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839252314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1839252314
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3983080634
Short name T262
Test name
Test status
Simulation time 331435969657 ps
CPU time 769.85 seconds
Started Mar 03 04:19:31 PM PST 24
Finished Mar 03 04:32:21 PM PST 24
Peak memory 200860 kb
Host smart-78aa2c0a-bb40-41e0-9062-7da18a2c2c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983080634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3983080634
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3927042883
Short name T234
Test name
Test status
Simulation time 493748204916 ps
CPU time 569.01 seconds
Started Mar 03 04:20:28 PM PST 24
Finished Mar 03 04:29:57 PM PST 24
Peak memory 200972 kb
Host smart-ab73d5a7-b73d-495a-8253-3e00f5cd47ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927042883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3927042883
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.148348160
Short name T170
Test name
Test status
Simulation time 329925940170 ps
CPU time 126.79 seconds
Started Mar 03 04:16:03 PM PST 24
Finished Mar 03 04:18:10 PM PST 24
Peak memory 200832 kb
Host smart-b074ea1a-767d-42fc-846b-85522fa9bf9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148348160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.148348160
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2322646267
Short name T263
Test name
Test status
Simulation time 165962258430 ps
CPU time 180.45 seconds
Started Mar 03 04:15:58 PM PST 24
Finished Mar 03 04:18:59 PM PST 24
Peak memory 200944 kb
Host smart-12ec9fe1-a862-4aaa-982b-ea2861f44dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322646267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2322646267
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3025879827
Short name T12
Test name
Test status
Simulation time 227916591065 ps
CPU time 123.2 seconds
Started Mar 03 04:16:13 PM PST 24
Finished Mar 03 04:18:16 PM PST 24
Peak memory 209308 kb
Host smart-6400a0cb-a4eb-4d25-8999-38eb9c9aee47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025879827 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3025879827
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3369998928
Short name T214
Test name
Test status
Simulation time 76215843906 ps
CPU time 274.51 seconds
Started Mar 03 04:23:11 PM PST 24
Finished Mar 03 04:27:46 PM PST 24
Peak memory 201412 kb
Host smart-ee5c3659-4744-49f7-ad50-a1c69411666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369998928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3369998928
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3675563362
Short name T69
Test name
Test status
Simulation time 525872299910 ps
CPU time 428.06 seconds
Started Mar 03 04:23:11 PM PST 24
Finished Mar 03 04:30:20 PM PST 24
Peak memory 209728 kb
Host smart-32abfffb-803a-4a2a-a85d-20d3f9a63103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675563362 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3675563362
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1612721501
Short name T250
Test name
Test status
Simulation time 330644758166 ps
CPU time 177.54 seconds
Started Mar 03 04:17:20 PM PST 24
Finished Mar 03 04:20:18 PM PST 24
Peak memory 200876 kb
Host smart-2ae49f03-4091-412a-ad2b-e6ad50d74425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612721501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1612721501
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3331005513
Short name T910
Test name
Test status
Simulation time 590235406 ps
CPU time 3.06 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 200172 kb
Host smart-37cadf99-7234-43b0-8d4b-cd83dd0a627a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331005513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3331005513
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4013627013
Short name T128
Test name
Test status
Simulation time 911950565 ps
CPU time 2.47 seconds
Started Mar 03 12:32:57 PM PST 24
Finished Mar 03 12:32:59 PM PST 24
Peak memory 200104 kb
Host smart-60fa38c4-1a99-4cdb-b30c-563d8989d788
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013627013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.4013627013
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.665280588
Short name T891
Test name
Test status
Simulation time 465246293 ps
CPU time 1.45 seconds
Started Mar 03 12:31:46 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 200876 kb
Host smart-98024664-78d0-4e07-b0ad-7e0f61794515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665280588 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.665280588
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.1941547523
Short name T890
Test name
Test status
Simulation time 498624205 ps
CPU time 0.8 seconds
Started Mar 03 12:33:04 PM PST 24
Finished Mar 03 12:33:06 PM PST 24
Peak memory 200820 kb
Host smart-6eb64a70-03ee-4adb-8b30-86bc0cb53a32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941547523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.1941547523
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.132843085
Short name T797
Test name
Test status
Simulation time 461726744 ps
CPU time 0.89 seconds
Started Mar 03 12:33:06 PM PST 24
Finished Mar 03 12:33:07 PM PST 24
Peak memory 200680 kb
Host smart-e05164cf-2fbd-4f12-bdcd-e807ca806add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132843085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.132843085
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3005361636
Short name T812
Test name
Test status
Simulation time 2652972489 ps
CPU time 9.16 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:16 PM PST 24
Peak memory 200952 kb
Host smart-ed4c71ee-09ed-43aa-bba3-5ae66dbe9e98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005361636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3005361636
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1736626046
Short name T843
Test name
Test status
Simulation time 494847613 ps
CPU time 3.18 seconds
Started Mar 03 12:33:02 PM PST 24
Finished Mar 03 12:33:06 PM PST 24
Peak memory 210292 kb
Host smart-eb4c8171-f831-496c-98aa-42608a18e928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736626046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1736626046
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3007810434
Short name T118
Test name
Test status
Simulation time 799151028 ps
CPU time 3.18 seconds
Started Mar 03 12:31:34 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 200204 kb
Host smart-694af744-f0ff-416f-a060-9221a8f5cdbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007810434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3007810434
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.65976803
Short name T854
Test name
Test status
Simulation time 52210243307 ps
CPU time 113.37 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:33:56 PM PST 24
Peak memory 201096 kb
Host smart-4fbbad63-dc8a-4d4c-9fc0-2aa3dd32ba2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65976803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_ba
sh.65976803
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2008549298
Short name T829
Test name
Test status
Simulation time 1267208814 ps
CPU time 1.42 seconds
Started Mar 03 12:31:59 PM PST 24
Finished Mar 03 12:32:01 PM PST 24
Peak memory 200808 kb
Host smart-7e620765-e9ed-462d-b083-53c9aa3eab4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008549298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2008549298
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.164664188
Short name T901
Test name
Test status
Simulation time 572654369 ps
CPU time 2.15 seconds
Started Mar 03 12:31:31 PM PST 24
Finished Mar 03 12:31:49 PM PST 24
Peak memory 200940 kb
Host smart-5bd0bfd0-445b-45ce-828a-8f6bcfbc2ca5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164664188 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.164664188
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2134767688
Short name T851
Test name
Test status
Simulation time 298957862 ps
CPU time 1.37 seconds
Started Mar 03 12:31:36 PM PST 24
Finished Mar 03 12:31:38 PM PST 24
Peak memory 200568 kb
Host smart-f5e45b21-b828-4ea4-82df-07a801068646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134767688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2134767688
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2247772737
Short name T798
Test name
Test status
Simulation time 416319532 ps
CPU time 1.57 seconds
Started Mar 03 12:31:46 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 200624 kb
Host smart-3254f7a8-a86f-4233-9614-705b708d729b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247772737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2247772737
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3655669199
Short name T35
Test name
Test status
Simulation time 2328100450 ps
CPU time 8.67 seconds
Started Mar 03 12:31:50 PM PST 24
Finished Mar 03 12:31:59 PM PST 24
Peak memory 200932 kb
Host smart-db55a89d-5bda-401b-9c12-a8bc606f4260
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655669199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3655669199
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3495245997
Short name T140
Test name
Test status
Simulation time 8375661403 ps
CPU time 15.5 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:20 PM PST 24
Peak memory 201152 kb
Host smart-fa6be175-01ad-4596-926e-cd0ee41b0027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495245997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3495245997
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1930659334
Short name T832
Test name
Test status
Simulation time 1032314330 ps
CPU time 1.13 seconds
Started Mar 03 12:32:01 PM PST 24
Finished Mar 03 12:32:03 PM PST 24
Peak memory 200936 kb
Host smart-d3245669-87c8-404c-9e52-5dc7222cf33f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930659334 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1930659334
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.3529724083
Short name T857
Test name
Test status
Simulation time 480075743 ps
CPU time 1.66 seconds
Started Mar 03 12:31:46 PM PST 24
Finished Mar 03 12:31:53 PM PST 24
Peak memory 200620 kb
Host smart-58dee871-eda1-4c82-830d-f1e8188b9798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529724083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.3529724083
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.147225207
Short name T36
Test name
Test status
Simulation time 2281667089 ps
CPU time 6.19 seconds
Started Mar 03 12:31:58 PM PST 24
Finished Mar 03 12:32:04 PM PST 24
Peak memory 199748 kb
Host smart-65000f4c-c318-4ef8-8811-5016a22e23ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147225207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.147225207
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4246995392
Short name T894
Test name
Test status
Simulation time 3197754574 ps
CPU time 3.14 seconds
Started Mar 03 12:31:51 PM PST 24
Finished Mar 03 12:31:55 PM PST 24
Peak memory 200412 kb
Host smart-61168258-6acd-41ec-994f-aea779197a27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246995392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4246995392
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1629529421
Short name T869
Test name
Test status
Simulation time 7954477554 ps
CPU time 10.82 seconds
Started Mar 03 12:32:11 PM PST 24
Finished Mar 03 12:32:22 PM PST 24
Peak memory 201164 kb
Host smart-e1c355af-b07a-4491-92c2-0982246ca869
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629529421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1629529421
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3276503345
Short name T802
Test name
Test status
Simulation time 355286231 ps
CPU time 1.68 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 200812 kb
Host smart-c20d280a-bb1d-4ead-8eb9-c896fc8d212b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276503345 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3276503345
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.193166113
Short name T834
Test name
Test status
Simulation time 465502609 ps
CPU time 1.01 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 199608 kb
Host smart-b185b138-9596-4984-95f7-3d8da315c524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193166113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.193166113
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3254982797
Short name T845
Test name
Test status
Simulation time 305231222 ps
CPU time 1.35 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200344 kb
Host smart-7c2346d2-d703-4c67-ace9-63f1e3beacde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254982797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3254982797
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3918898357
Short name T853
Test name
Test status
Simulation time 2800207626 ps
CPU time 4.17 seconds
Started Mar 03 12:32:00 PM PST 24
Finished Mar 03 12:32:04 PM PST 24
Peak memory 200936 kb
Host smart-53e58e98-0feb-4273-a3c9-c9208f93b991
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918898357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3918898357
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.808348574
Short name T827
Test name
Test status
Simulation time 484729530 ps
CPU time 2.35 seconds
Started Mar 03 12:32:12 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 200892 kb
Host smart-1863070a-550a-4c12-92ed-54a340be7551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808348574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.808348574
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1808242735
Short name T838
Test name
Test status
Simulation time 4675228481 ps
CPU time 4.54 seconds
Started Mar 03 12:31:51 PM PST 24
Finished Mar 03 12:31:56 PM PST 24
Peak memory 201176 kb
Host smart-53acfb04-a1d4-4c96-9259-f915bfff51a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808242735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1808242735
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3813726962
Short name T874
Test name
Test status
Simulation time 465260201 ps
CPU time 1.78 seconds
Started Mar 03 12:31:41 PM PST 24
Finished Mar 03 12:31:43 PM PST 24
Peak memory 200700 kb
Host smart-8b5418ee-7605-4514-a8d0-5fd3bdeaeff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813726962 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3813726962
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.384992521
Short name T820
Test name
Test status
Simulation time 485617002 ps
CPU time 2.04 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200804 kb
Host smart-3c9bfe00-facc-4e68-a31b-09362ea12126
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384992521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.384992521
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.659566756
Short name T840
Test name
Test status
Simulation time 494173024 ps
CPU time 0.93 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:08 PM PST 24
Peak memory 199744 kb
Host smart-3f8b4002-6d44-4a05-9784-55062b3b2db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659566756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.659566756
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.695747296
Short name T889
Test name
Test status
Simulation time 4356705417 ps
CPU time 10.75 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:20 PM PST 24
Peak memory 201104 kb
Host smart-2a0966b4-03b0-4b5a-945e-ddcd2f4b3b5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695747296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.695747296
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4048548371
Short name T136
Test name
Test status
Simulation time 610027423 ps
CPU time 4.08 seconds
Started Mar 03 12:31:53 PM PST 24
Finished Mar 03 12:31:57 PM PST 24
Peak memory 216300 kb
Host smart-cec1ef67-042c-4732-93dd-9b50c5bf7b98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048548371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4048548371
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3274998969
Short name T903
Test name
Test status
Simulation time 4208929122 ps
CPU time 2.77 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:07 PM PST 24
Peak memory 201052 kb
Host smart-8716381b-2c4e-44f0-bb25-b42399389ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274998969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3274998969
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.729672401
Short name T813
Test name
Test status
Simulation time 505322089 ps
CPU time 2.07 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:16 PM PST 24
Peak memory 200872 kb
Host smart-c161e40b-3e10-43c5-86bc-37eaa2e0e37e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729672401 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.729672401
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2648049759
Short name T836
Test name
Test status
Simulation time 478415857 ps
CPU time 1.41 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200820 kb
Host smart-8cc3e7b1-cb3f-4af6-94f2-60de42006358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648049759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2648049759
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3335258474
Short name T791
Test name
Test status
Simulation time 347673926 ps
CPU time 0.75 seconds
Started Mar 03 12:32:04 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200788 kb
Host smart-84aeffd9-12c1-4407-9567-e10da1165b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335258474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3335258474
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.386835833
Short name T823
Test name
Test status
Simulation time 1724274392 ps
CPU time 6.39 seconds
Started Mar 03 12:32:40 PM PST 24
Finished Mar 03 12:32:46 PM PST 24
Peak memory 200884 kb
Host smart-de339452-cca8-4b83-b13d-bc405b3d56c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386835833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.386835833
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1918687096
Short name T897
Test name
Test status
Simulation time 456435006 ps
CPU time 2.47 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:07 PM PST 24
Peak memory 200852 kb
Host smart-1cc7fa9e-68fc-441d-8291-52e92a32fc27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918687096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1918687096
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.25705445
Short name T141
Test name
Test status
Simulation time 7989045494 ps
CPU time 6.74 seconds
Started Mar 03 12:32:04 PM PST 24
Finished Mar 03 12:32:11 PM PST 24
Peak memory 201072 kb
Host smart-7b76af59-0f75-4da2-a3ec-87bdfe14b5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25705445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_int
g_err.25705445
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.157537141
Short name T805
Test name
Test status
Simulation time 465464425 ps
CPU time 1.06 seconds
Started Mar 03 12:32:11 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 200924 kb
Host smart-bd58187a-433e-4590-9cc1-917540ad79d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157537141 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.157537141
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1789983123
Short name T879
Test name
Test status
Simulation time 359338000 ps
CPU time 1.04 seconds
Started Mar 03 12:32:07 PM PST 24
Finished Mar 03 12:32:08 PM PST 24
Peak memory 200816 kb
Host smart-a1d61b52-0b76-4a7b-ad54-5503efa11239
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789983123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1789983123
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3584208673
Short name T808
Test name
Test status
Simulation time 319605855 ps
CPU time 0.97 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 200804 kb
Host smart-31cd7c88-d744-4247-bc94-fcb2e0ddde65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584208673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3584208673
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1940899184
Short name T127
Test name
Test status
Simulation time 2315767594 ps
CPU time 3.29 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200952 kb
Host smart-e3b8a546-3283-4244-ac19-ae9d154ea720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940899184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1940899184
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.971452941
Short name T908
Test name
Test status
Simulation time 516400746 ps
CPU time 1.94 seconds
Started Mar 03 12:32:01 PM PST 24
Finished Mar 03 12:32:03 PM PST 24
Peak memory 201132 kb
Host smart-a91963d4-593b-4ee6-b75e-659561bf1451
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971452941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.971452941
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.79135894
Short name T71
Test name
Test status
Simulation time 431517570 ps
CPU time 1.05 seconds
Started Mar 03 12:32:04 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200960 kb
Host smart-628bb51d-8edd-4bd2-92f1-b115e08a0aaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79135894 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.79135894
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2119504821
Short name T814
Test name
Test status
Simulation time 334093213 ps
CPU time 1.77 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 200012 kb
Host smart-e4b1f866-3f65-4cbf-9b80-dce292550832
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119504821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2119504821
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2589838449
Short name T852
Test name
Test status
Simulation time 366751233 ps
CPU time 0.85 seconds
Started Mar 03 12:31:59 PM PST 24
Finished Mar 03 12:32:00 PM PST 24
Peak memory 200692 kb
Host smart-a899c690-825a-4d4c-9aea-4b1efa02f647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589838449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2589838449
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4251326259
Short name T819
Test name
Test status
Simulation time 4818299474 ps
CPU time 6.21 seconds
Started Mar 03 12:32:05 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 201116 kb
Host smart-cbfda429-1a54-4b63-9f5f-5483ec511971
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251326259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.4251326259
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3289949613
Short name T893
Test name
Test status
Simulation time 494315173 ps
CPU time 1.62 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 201052 kb
Host smart-450b7b52-0990-4fcc-b150-e0b2c3913a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289949613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3289949613
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.444617306
Short name T867
Test name
Test status
Simulation time 7945019587 ps
CPU time 20.7 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:28 PM PST 24
Peak memory 201168 kb
Host smart-4373233b-8d5f-44d1-ac40-904cfe30354d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444617306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.444617306
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.1908669095
Short name T863
Test name
Test status
Simulation time 572601639 ps
CPU time 2.26 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:09 PM PST 24
Peak memory 200936 kb
Host smart-289bb50a-a9de-4b0f-a085-5f7e9dcb938b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908669095 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.1908669095
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.982389956
Short name T907
Test name
Test status
Simulation time 472479873 ps
CPU time 0.99 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:07 PM PST 24
Peak memory 200824 kb
Host smart-93046afb-bb0d-4356-a82a-d712ea039338
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982389956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.982389956
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.294921093
Short name T801
Test name
Test status
Simulation time 340509893 ps
CPU time 1.48 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:11 PM PST 24
Peak memory 200776 kb
Host smart-99db77a7-dde5-4eb1-8cb2-4a12a176e59e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294921093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.294921093
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1031721392
Short name T898
Test name
Test status
Simulation time 5175919944 ps
CPU time 21.57 seconds
Started Mar 03 12:32:12 PM PST 24
Finished Mar 03 12:32:34 PM PST 24
Peak memory 201080 kb
Host smart-d16fe6a6-0534-4068-b13b-2653c60c2ae9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031721392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1031721392
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.24402031
Short name T866
Test name
Test status
Simulation time 435634281 ps
CPU time 3.16 seconds
Started Mar 03 12:32:05 PM PST 24
Finished Mar 03 12:32:09 PM PST 24
Peak memory 217400 kb
Host smart-1b1bade2-eccc-4676-b741-9aa511d38525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.24402031
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1757463773
Short name T139
Test name
Test status
Simulation time 4415421011 ps
CPU time 3.72 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:08 PM PST 24
Peak memory 201144 kb
Host smart-e5dd08e4-6517-4d69-b081-f948c9bc9861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757463773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1757463773
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2950152458
Short name T93
Test name
Test status
Simulation time 515053104 ps
CPU time 1.97 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:32:05 PM PST 24
Peak memory 200092 kb
Host smart-168e07ba-e3af-4dbd-a7a9-ee5d5421eff7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950152458 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2950152458
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.3754693853
Short name T120
Test name
Test status
Simulation time 488595308 ps
CPU time 1.26 seconds
Started Mar 03 12:32:01 PM PST 24
Finished Mar 03 12:32:02 PM PST 24
Peak memory 200788 kb
Host smart-d9a9fdcd-149c-46c3-8fff-1c3327f43224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754693853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.3754693853
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1179552185
Short name T796
Test name
Test status
Simulation time 438524967 ps
CPU time 1.55 seconds
Started Mar 03 12:32:11 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 200544 kb
Host smart-f60a00e2-271d-4ce6-b2de-f1fffefd4bc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179552185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1179552185
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3044715663
Short name T34
Test name
Test status
Simulation time 4191066395 ps
CPU time 7.79 seconds
Started Mar 03 12:32:12 PM PST 24
Finished Mar 03 12:32:20 PM PST 24
Peak memory 201124 kb
Host smart-238141b7-d257-48d3-91ad-0c3d55d416fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044715663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3044715663
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.852511569
Short name T864
Test name
Test status
Simulation time 437330016 ps
CPU time 3.23 seconds
Started Mar 03 12:31:56 PM PST 24
Finished Mar 03 12:32:00 PM PST 24
Peak memory 209552 kb
Host smart-1d74778b-a669-4849-b3f8-d7acddedd9ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852511569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.852511569
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2368804694
Short name T335
Test name
Test status
Simulation time 4160212518 ps
CPU time 3.7 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:14 PM PST 24
Peak memory 201088 kb
Host smart-0a59decd-daa5-4f0e-ad2f-b30dd715dde3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368804694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2368804694
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3677087519
Short name T807
Test name
Test status
Simulation time 662101858 ps
CPU time 1.36 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:08 PM PST 24
Peak memory 200924 kb
Host smart-1ec03072-3a51-4274-bf41-2179fcc33824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677087519 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3677087519
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.997672315
Short name T876
Test name
Test status
Simulation time 435061143 ps
CPU time 1.21 seconds
Started Mar 03 12:32:07 PM PST 24
Finished Mar 03 12:32:10 PM PST 24
Peak memory 200816 kb
Host smart-ac17be5f-2857-4a94-b437-b2d2a181f6dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997672315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.997672315
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2751160868
Short name T793
Test name
Test status
Simulation time 287945909 ps
CPU time 1.31 seconds
Started Mar 03 12:32:17 PM PST 24
Finished Mar 03 12:32:19 PM PST 24
Peak memory 200640 kb
Host smart-dac1e2f3-e42e-46bd-b8d1-aff7d18548b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751160868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2751160868
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3985501355
Short name T861
Test name
Test status
Simulation time 2834523234 ps
CPU time 1.57 seconds
Started Mar 03 12:32:12 PM PST 24
Finished Mar 03 12:32:14 PM PST 24
Peak memory 200952 kb
Host smart-b93573d1-d192-4647-93d5-1ca5758ae802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985501355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3985501355
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3076901409
Short name T856
Test name
Test status
Simulation time 551716529 ps
CPU time 3.56 seconds
Started Mar 03 12:32:15 PM PST 24
Finished Mar 03 12:32:19 PM PST 24
Peak memory 217048 kb
Host smart-3402e305-f14f-414d-ba66-f20cac16a1fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076901409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3076901409
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.652378367
Short name T855
Test name
Test status
Simulation time 4496686073 ps
CPU time 12.39 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:23 PM PST 24
Peak memory 201148 kb
Host smart-ea420b15-d7ee-41ce-b883-cdb8e236395d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652378367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.652378367
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1119101479
Short name T875
Test name
Test status
Simulation time 437210379 ps
CPU time 1.81 seconds
Started Mar 03 12:32:10 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 200948 kb
Host smart-c801d9d8-1076-4cf3-8e1b-445001871404
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119101479 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1119101479
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2368834280
Short name T114
Test name
Test status
Simulation time 432338804 ps
CPU time 1.76 seconds
Started Mar 03 12:32:28 PM PST 24
Finished Mar 03 12:32:30 PM PST 24
Peak memory 200796 kb
Host smart-5366ae1f-ad12-47b1-91a4-b74b4195789e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368834280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2368834280
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3890744758
Short name T883
Test name
Test status
Simulation time 451481864 ps
CPU time 0.81 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 200488 kb
Host smart-8c59ac03-dc64-4ac8-933b-08f3e871922a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890744758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3890744758
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3633439073
Short name T878
Test name
Test status
Simulation time 2519112088 ps
CPU time 3.42 seconds
Started Mar 03 12:32:22 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 200944 kb
Host smart-7fd3643b-00dd-4fbc-a4c0-92bd50bd0722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633439073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3633439073
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2223100991
Short name T137
Test name
Test status
Simulation time 604538143 ps
CPU time 3.69 seconds
Started Mar 03 12:32:30 PM PST 24
Finished Mar 03 12:32:33 PM PST 24
Peak memory 201120 kb
Host smart-953dd928-3f86-415c-a743-535a3c3ef18a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223100991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2223100991
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2752985617
Short name T131
Test name
Test status
Simulation time 8395097466 ps
CPU time 22.56 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:30 PM PST 24
Peak memory 201088 kb
Host smart-b7faa3be-a31d-4e26-aa79-48a99764c861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752985617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2752985617
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2584346668
Short name T868
Test name
Test status
Simulation time 838724172 ps
CPU time 4.6 seconds
Started Mar 03 12:31:50 PM PST 24
Finished Mar 03 12:31:55 PM PST 24
Peak memory 200988 kb
Host smart-de68612f-f2d0-4f53-9ca3-1668fb9a01ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584346668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2584346668
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2516092269
Short name T117
Test name
Test status
Simulation time 51832635247 ps
CPU time 32.47 seconds
Started Mar 03 12:31:38 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 199752 kb
Host smart-f5774d12-d865-4a8d-a5cf-25f7a2c4688f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516092269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2516092269
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3839868309
Short name T826
Test name
Test status
Simulation time 1331152671 ps
CPU time 3.77 seconds
Started Mar 03 12:31:57 PM PST 24
Finished Mar 03 12:32:01 PM PST 24
Peak memory 200616 kb
Host smart-6846e475-c3f4-415e-9fe9-eca9f5996386
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839868309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3839868309
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.964050653
Short name T806
Test name
Test status
Simulation time 404316355 ps
CPU time 1.72 seconds
Started Mar 03 12:31:52 PM PST 24
Finished Mar 03 12:31:53 PM PST 24
Peak memory 200956 kb
Host smart-8b130dad-4e5e-42e3-b41c-34bf2c4c5e73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964050653 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.964050653
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3839679576
Short name T115
Test name
Test status
Simulation time 411417290 ps
CPU time 1 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:07 PM PST 24
Peak memory 200672 kb
Host smart-d48c410d-fce9-4212-9540-890d817dfcc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839679576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3839679576
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2597920679
Short name T800
Test name
Test status
Simulation time 359811106 ps
CPU time 1.45 seconds
Started Mar 03 12:31:35 PM PST 24
Finished Mar 03 12:31:37 PM PST 24
Peak memory 201228 kb
Host smart-f3eda2ca-47b5-49bd-b680-7c53fb8d6bb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597920679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2597920679
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1967568953
Short name T126
Test name
Test status
Simulation time 4209005960 ps
CPU time 10.27 seconds
Started Mar 03 12:31:41 PM PST 24
Finished Mar 03 12:31:51 PM PST 24
Peak memory 201116 kb
Host smart-87f7d7d6-13b2-419d-9ca1-55aa7eb44129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967568953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1967568953
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.947153909
Short name T899
Test name
Test status
Simulation time 458520472 ps
CPU time 1.95 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 208436 kb
Host smart-886105dc-3a95-4224-bf65-de08032f4460
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947153909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.947153909
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1241482528
Short name T848
Test name
Test status
Simulation time 4692352142 ps
CPU time 2.71 seconds
Started Mar 03 12:31:44 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 201160 kb
Host smart-dce298f7-f0d4-4752-b397-9376d8a62567
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241482528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1241482528
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3723291686
Short name T900
Test name
Test status
Simulation time 294550018 ps
CPU time 1.24 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 200636 kb
Host smart-cca37737-6cbc-4e40-981b-9db2cf9073ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723291686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3723291686
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3453136313
Short name T895
Test name
Test status
Simulation time 498530780 ps
CPU time 1.16 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:08 PM PST 24
Peak memory 200636 kb
Host smart-f93e9c24-af22-4ff4-8928-7f076996e429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453136313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3453136313
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.365852347
Short name T830
Test name
Test status
Simulation time 455924525 ps
CPU time 1.65 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:09 PM PST 24
Peak memory 201228 kb
Host smart-18ed8cf9-9170-42db-a2da-fbe074307952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365852347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.365852347
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.169786805
Short name T810
Test name
Test status
Simulation time 495823686 ps
CPU time 1.69 seconds
Started Mar 03 12:32:21 PM PST 24
Finished Mar 03 12:32:23 PM PST 24
Peak memory 200816 kb
Host smart-6a17602b-163b-4cbb-b24d-e02a0e4deb3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169786805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.169786805
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1706372884
Short name T821
Test name
Test status
Simulation time 625891555 ps
CPU time 0.76 seconds
Started Mar 03 12:32:17 PM PST 24
Finished Mar 03 12:32:18 PM PST 24
Peak memory 200576 kb
Host smart-590cefe3-87f3-4339-bb40-cf49e889bf61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706372884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1706372884
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4228027338
Short name T792
Test name
Test status
Simulation time 336863429 ps
CPU time 1.35 seconds
Started Mar 03 12:32:40 PM PST 24
Finished Mar 03 12:32:42 PM PST 24
Peak memory 200644 kb
Host smart-b24a8570-32af-4fdd-be48-490200b263a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228027338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.4228027338
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2970108981
Short name T904
Test name
Test status
Simulation time 383568455 ps
CPU time 0.76 seconds
Started Mar 03 12:32:05 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200636 kb
Host smart-e1f25df4-2f6f-44c4-b8e6-378268c61c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970108981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2970108981
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1990158712
Short name T912
Test name
Test status
Simulation time 514492383 ps
CPU time 1.9 seconds
Started Mar 03 12:32:05 PM PST 24
Finished Mar 03 12:32:07 PM PST 24
Peak memory 200792 kb
Host smart-1937d9be-c062-4abd-883f-020d4de4e86c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990158712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1990158712
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2714548186
Short name T846
Test name
Test status
Simulation time 522298572 ps
CPU time 0.93 seconds
Started Mar 03 12:32:12 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 200812 kb
Host smart-18232c15-caef-45f1-b61f-63cd5b60df05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714548186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2714548186
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1341945398
Short name T850
Test name
Test status
Simulation time 333123618 ps
CPU time 1.36 seconds
Started Mar 03 12:32:15 PM PST 24
Finished Mar 03 12:32:16 PM PST 24
Peak memory 200652 kb
Host smart-480c4ad6-0262-4919-8523-f57cad2384c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341945398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1341945398
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.1469560846
Short name T909
Test name
Test status
Simulation time 792718189 ps
CPU time 1.91 seconds
Started Mar 03 12:31:38 PM PST 24
Finished Mar 03 12:31:41 PM PST 24
Peak memory 199596 kb
Host smart-6ab9b511-c75f-4d4f-ac48-7a379f2e2b9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469560846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.1469560846
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1680495282
Short name T119
Test name
Test status
Simulation time 1165408282 ps
CPU time 4.26 seconds
Started Mar 03 12:31:51 PM PST 24
Finished Mar 03 12:31:55 PM PST 24
Peak memory 200996 kb
Host smart-f9a26690-5e76-48f4-a2fa-d03fc3c869cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680495282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1680495282
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3294767382
Short name T803
Test name
Test status
Simulation time 910634985 ps
CPU time 2.58 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 200008 kb
Host smart-27d7e350-5f78-4404-a15b-960ea97fefbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294767382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3294767382
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.29291882
Short name T82
Test name
Test status
Simulation time 448890858 ps
CPU time 1.75 seconds
Started Mar 03 12:32:00 PM PST 24
Finished Mar 03 12:32:02 PM PST 24
Peak memory 200956 kb
Host smart-2dada8f4-0610-4ed2-98f9-8268c980350d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29291882 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.29291882
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2745633880
Short name T911
Test name
Test status
Simulation time 525076623 ps
CPU time 1.09 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:11 PM PST 24
Peak memory 200808 kb
Host smart-fabc4853-3e76-4f35-bf2a-c69cced26766
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745633880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2745633880
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.565151475
Short name T816
Test name
Test status
Simulation time 391278046 ps
CPU time 1.64 seconds
Started Mar 03 12:32:18 PM PST 24
Finished Mar 03 12:32:20 PM PST 24
Peak memory 200800 kb
Host smart-640c5f7b-b0ef-4fbb-a17a-06948f2bc6e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565151475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.565151475
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4073981676
Short name T828
Test name
Test status
Simulation time 4819952754 ps
CPU time 10.88 seconds
Started Mar 03 12:31:45 PM PST 24
Finished Mar 03 12:31:57 PM PST 24
Peak memory 201068 kb
Host smart-d71573f6-abaf-4232-94a5-e9eaefd251a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073981676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4073981676
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2469383422
Short name T138
Test name
Test status
Simulation time 527012497 ps
CPU time 3.25 seconds
Started Mar 03 12:31:57 PM PST 24
Finished Mar 03 12:32:01 PM PST 24
Peak memory 201136 kb
Host smart-64fc53ef-06c4-427a-a932-210f44b6c9db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469383422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2469383422
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2281822808
Short name T818
Test name
Test status
Simulation time 4310550484 ps
CPU time 10.61 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:14 PM PST 24
Peak memory 201100 kb
Host smart-8c88c6e8-61ac-4f8a-aa9b-05decdaeda8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281822808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2281822808
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.4112189978
Short name T817
Test name
Test status
Simulation time 474978854 ps
CPU time 1.65 seconds
Started Mar 03 12:32:18 PM PST 24
Finished Mar 03 12:32:20 PM PST 24
Peak memory 200692 kb
Host smart-4eb35638-ec70-4049-b069-56b680a635b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112189978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.4112189978
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.2866358800
Short name T835
Test name
Test status
Simulation time 470358687 ps
CPU time 1.64 seconds
Started Mar 03 12:32:24 PM PST 24
Finished Mar 03 12:32:26 PM PST 24
Peak memory 200812 kb
Host smart-10f69c12-da40-4a7a-8f65-7b351c61d5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866358800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.2866358800
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.821222149
Short name T881
Test name
Test status
Simulation time 343149924 ps
CPU time 0.86 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:09 PM PST 24
Peak memory 200648 kb
Host smart-8ed0ee2e-3416-4932-9f54-8e410564b8c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821222149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.821222149
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4095072276
Short name T837
Test name
Test status
Simulation time 445900838 ps
CPU time 1.09 seconds
Started Mar 03 12:32:11 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 200816 kb
Host smart-143855d1-9f64-4403-85b6-65ddf80fce04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095072276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4095072276
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3099166359
Short name T871
Test name
Test status
Simulation time 429770406 ps
CPU time 1.04 seconds
Started Mar 03 12:32:10 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 200812 kb
Host smart-545f194f-2ae0-455b-8f0c-f85c03efe577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099166359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3099166359
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3586115481
Short name T842
Test name
Test status
Simulation time 402601500 ps
CPU time 1.06 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 200604 kb
Host smart-58ddbf06-f9a5-4855-bcd5-d64ca1816a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586115481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3586115481
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3467528982
Short name T799
Test name
Test status
Simulation time 407825404 ps
CPU time 1.53 seconds
Started Mar 03 12:32:15 PM PST 24
Finished Mar 03 12:32:17 PM PST 24
Peak memory 200760 kb
Host smart-3beba2e3-2b70-47ef-ba2c-8d4990caed01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467528982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3467528982
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3314697728
Short name T804
Test name
Test status
Simulation time 377820643 ps
CPU time 1.46 seconds
Started Mar 03 12:32:11 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 200628 kb
Host smart-478ab4e7-a74f-43a6-ab85-60caea7d77cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314697728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3314697728
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1099314930
Short name T824
Test name
Test status
Simulation time 397688688 ps
CPU time 0.69 seconds
Started Mar 03 12:32:18 PM PST 24
Finished Mar 03 12:32:19 PM PST 24
Peak memory 200784 kb
Host smart-fc7ea5c2-685f-4355-9b27-ef2620b0d56e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099314930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1099314930
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1432995062
Short name T892
Test name
Test status
Simulation time 452188479 ps
CPU time 0.87 seconds
Started Mar 03 12:32:11 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 200628 kb
Host smart-97e759cc-362d-49ac-b9cd-eb4108b1e083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432995062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1432995062
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.942343216
Short name T886
Test name
Test status
Simulation time 1075474024 ps
CPU time 3.66 seconds
Started Mar 03 12:31:36 PM PST 24
Finished Mar 03 12:31:40 PM PST 24
Peak memory 200924 kb
Host smart-58324c16-47aa-4691-b5a1-b6bc12718713
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942343216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.942343216
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.4052511098
Short name T865
Test name
Test status
Simulation time 27428331505 ps
CPU time 47.12 seconds
Started Mar 03 12:31:54 PM PST 24
Finished Mar 03 12:32:41 PM PST 24
Peak memory 201004 kb
Host smart-fac51287-801e-485d-b198-75fcb95a1372
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052511098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.4052511098
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.2819088214
Short name T884
Test name
Test status
Simulation time 1257106727 ps
CPU time 3.85 seconds
Started Mar 03 12:31:35 PM PST 24
Finished Mar 03 12:31:39 PM PST 24
Peak memory 200008 kb
Host smart-8ae70bc5-3c66-4c81-ae20-d01c83a99786
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819088214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.2819088214
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.269509726
Short name T129
Test name
Test status
Simulation time 470074219 ps
CPU time 1.92 seconds
Started Mar 03 12:31:40 PM PST 24
Finished Mar 03 12:31:42 PM PST 24
Peak memory 200672 kb
Host smart-35314ef5-113f-45d2-9d4f-0c874e323621
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269509726 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.269509726
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3548095274
Short name T121
Test name
Test status
Simulation time 412003302 ps
CPU time 0.78 seconds
Started Mar 03 12:31:45 PM PST 24
Finished Mar 03 12:31:46 PM PST 24
Peak memory 200792 kb
Host smart-b6067b1b-7660-4324-bb2a-9474c2280bd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548095274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3548095274
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3566132226
Short name T809
Test name
Test status
Simulation time 338979143 ps
CPU time 0.8 seconds
Started Mar 03 12:31:38 PM PST 24
Finished Mar 03 12:31:40 PM PST 24
Peak memory 200016 kb
Host smart-69178485-2bee-4290-bc9b-329abdc5cd34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566132226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3566132226
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2508851414
Short name T125
Test name
Test status
Simulation time 2344000799 ps
CPU time 9.41 seconds
Started Mar 03 12:31:51 PM PST 24
Finished Mar 03 12:32:01 PM PST 24
Peak memory 200948 kb
Host smart-260f5e72-ca80-45b4-a590-3870c5375d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508851414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2508851414
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3985644090
Short name T130
Test name
Test status
Simulation time 747548318 ps
CPU time 2.09 seconds
Started Mar 03 12:32:00 PM PST 24
Finished Mar 03 12:32:02 PM PST 24
Peak memory 217396 kb
Host smart-72c3fad1-d4a8-4e70-8db8-509569f55676
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985644090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3985644090
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1653815141
Short name T42
Test name
Test status
Simulation time 5101413193 ps
CPU time 4.34 seconds
Started Mar 03 12:32:00 PM PST 24
Finished Mar 03 12:32:04 PM PST 24
Peak memory 201176 kb
Host smart-d9f81a42-14ec-49b6-b257-a4e4bdfd8874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653815141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1653815141
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1889014591
Short name T822
Test name
Test status
Simulation time 409667093 ps
CPU time 1.12 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 199468 kb
Host smart-37161635-a599-4180-8509-4f4250c59365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889014591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1889014591
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1715874123
Short name T885
Test name
Test status
Simulation time 342081951 ps
CPU time 0.81 seconds
Started Mar 03 12:32:10 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 200624 kb
Host smart-2cbce847-df05-4ccf-8a84-7cdc3c164811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715874123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1715874123
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3628412981
Short name T849
Test name
Test status
Simulation time 491927021 ps
CPU time 0.87 seconds
Started Mar 03 12:32:21 PM PST 24
Finished Mar 03 12:32:23 PM PST 24
Peak memory 200644 kb
Host smart-43628900-6e2b-4d4b-bf00-bf8ef88089a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628412981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3628412981
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4294560097
Short name T877
Test name
Test status
Simulation time 504670796 ps
CPU time 0.85 seconds
Started Mar 03 12:32:21 PM PST 24
Finished Mar 03 12:32:22 PM PST 24
Peak memory 200656 kb
Host smart-4f9fdb8d-665b-4f10-8bdf-0491c972e0a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294560097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4294560097
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3516115762
Short name T825
Test name
Test status
Simulation time 446277397 ps
CPU time 0.94 seconds
Started Mar 03 12:32:38 PM PST 24
Finished Mar 03 12:32:39 PM PST 24
Peak memory 200704 kb
Host smart-ac44d051-2fd2-4d41-9e51-a6037e51cecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516115762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3516115762
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.456228714
Short name T794
Test name
Test status
Simulation time 407137756 ps
CPU time 0.91 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 200676 kb
Host smart-b5d8ae90-47cb-457b-b80f-d8ab8cc5b42b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456228714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.456228714
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3924625918
Short name T906
Test name
Test status
Simulation time 339679822 ps
CPU time 1.38 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 200636 kb
Host smart-c42464ef-df4f-4cc1-ace8-17516f69b1b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924625918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3924625918
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2865398745
Short name T858
Test name
Test status
Simulation time 284067301 ps
CPU time 1.3 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 200612 kb
Host smart-0eddac62-8ef1-42d7-939a-b58c7571374f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865398745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2865398745
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.253716883
Short name T815
Test name
Test status
Simulation time 562142496 ps
CPU time 0.93 seconds
Started Mar 03 12:32:16 PM PST 24
Finished Mar 03 12:32:17 PM PST 24
Peak memory 200808 kb
Host smart-0df172ae-2f3c-40ff-9b67-542480a6357f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253716883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.253716883
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2209823682
Short name T870
Test name
Test status
Simulation time 521025412 ps
CPU time 1.25 seconds
Started Mar 03 12:32:19 PM PST 24
Finished Mar 03 12:32:20 PM PST 24
Peak memory 201168 kb
Host smart-27d2d53b-42cf-480b-8b8f-03fd79a57ddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209823682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2209823682
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.957506889
Short name T882
Test name
Test status
Simulation time 328878117 ps
CPU time 1.49 seconds
Started Mar 03 12:31:33 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 199980 kb
Host smart-838d9ba0-3805-4167-8ea2-d1803487ae1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957506889 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.957506889
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2619483542
Short name T116
Test name
Test status
Simulation time 387145375 ps
CPU time 1.54 seconds
Started Mar 03 12:32:04 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200804 kb
Host smart-4a200b35-e045-4f36-b45a-221faf8175e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619483542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2619483542
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3257890365
Short name T905
Test name
Test status
Simulation time 466062090 ps
CPU time 0.9 seconds
Started Mar 03 12:31:47 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 200656 kb
Host smart-8304bca9-5dcf-4cc5-bb0f-9b8b4deeef12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257890365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3257890365
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1809983121
Short name T888
Test name
Test status
Simulation time 4003530575 ps
CPU time 3.61 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:32:07 PM PST 24
Peak memory 200352 kb
Host smart-316a4c6c-02da-4e16-abb7-09312a3486bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809983121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1809983121
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.14425127
Short name T44
Test name
Test status
Simulation time 394051236 ps
CPU time 2.79 seconds
Started Mar 03 12:31:58 PM PST 24
Finished Mar 03 12:32:01 PM PST 24
Peak memory 208096 kb
Host smart-076ea0af-4363-435a-9103-9a4e1a04155d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14425127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.14425127
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4230718568
Short name T887
Test name
Test status
Simulation time 8342774959 ps
CPU time 21.37 seconds
Started Mar 03 12:31:38 PM PST 24
Finished Mar 03 12:32:00 PM PST 24
Peak memory 200328 kb
Host smart-06859b87-37df-4e2f-ba7d-3d0661b1f7c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230718568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4230718568
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.950987853
Short name T860
Test name
Test status
Simulation time 522032187 ps
CPU time 2.19 seconds
Started Mar 03 12:32:01 PM PST 24
Finished Mar 03 12:32:03 PM PST 24
Peak memory 200952 kb
Host smart-57c58778-6ff0-4b1b-ad26-4e5a7d89ce74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950987853 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.950987853
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.939627511
Short name T113
Test name
Test status
Simulation time 468102918 ps
CPU time 1.34 seconds
Started Mar 03 12:32:13 PM PST 24
Finished Mar 03 12:32:15 PM PST 24
Peak memory 200824 kb
Host smart-52e5f623-e556-4e17-8380-92abda77c5e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939627511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.939627511
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1356227625
Short name T811
Test name
Test status
Simulation time 412305295 ps
CPU time 1.58 seconds
Started Mar 03 12:31:43 PM PST 24
Finished Mar 03 12:31:46 PM PST 24
Peak memory 199800 kb
Host smart-3ce812c1-8334-41d3-bcbe-39486324fa49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356227625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1356227625
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3311061875
Short name T37
Test name
Test status
Simulation time 2492058623 ps
CPU time 2.9 seconds
Started Mar 03 12:32:04 PM PST 24
Finished Mar 03 12:32:08 PM PST 24
Peak memory 200936 kb
Host smart-8e5c32a0-a5ac-4d06-b806-77ef3dad027f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311061875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3311061875
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2342961353
Short name T839
Test name
Test status
Simulation time 578013570 ps
CPU time 1.85 seconds
Started Mar 03 12:31:32 PM PST 24
Finished Mar 03 12:31:35 PM PST 24
Peak memory 200368 kb
Host smart-18531386-428f-4e27-b35d-a7bdf6b99a52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342961353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2342961353
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.431806624
Short name T142
Test name
Test status
Simulation time 4600981516 ps
CPU time 4.32 seconds
Started Mar 03 12:31:59 PM PST 24
Finished Mar 03 12:32:03 PM PST 24
Peak memory 201124 kb
Host smart-30803060-54f8-444e-b94e-e696b0a334ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431806624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.431806624
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.71524866
Short name T872
Test name
Test status
Simulation time 501034927 ps
CPU time 1.11 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 200956 kb
Host smart-4ef9b8c4-a5ca-4bd8-8d73-469425af55e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71524866 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.71524866
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2534881912
Short name T862
Test name
Test status
Simulation time 392209250 ps
CPU time 1.57 seconds
Started Mar 03 12:32:09 PM PST 24
Finished Mar 03 12:32:13 PM PST 24
Peak memory 200824 kb
Host smart-17e6c18b-9cf7-4022-9920-6d25f7f26a77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534881912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2534881912
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2712214246
Short name T795
Test name
Test status
Simulation time 477025574 ps
CPU time 0.85 seconds
Started Mar 03 12:32:18 PM PST 24
Finished Mar 03 12:32:19 PM PST 24
Peak memory 200636 kb
Host smart-dd5bf40f-d3b3-4121-a9a4-cb669b6ea574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712214246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2712214246
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3629337493
Short name T847
Test name
Test status
Simulation time 2982030931 ps
CPU time 2.63 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:32:05 PM PST 24
Peak memory 200920 kb
Host smart-bf347187-d715-47b2-8de0-53881c647fa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629337493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3629337493
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3207104255
Short name T831
Test name
Test status
Simulation time 449136625 ps
CPU time 2.7 seconds
Started Mar 03 12:31:40 PM PST 24
Finished Mar 03 12:31:48 PM PST 24
Peak memory 200988 kb
Host smart-4d246be8-0a90-478e-a765-371b9f9431dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207104255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3207104255
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3755172996
Short name T43
Test name
Test status
Simulation time 7742377343 ps
CPU time 18.83 seconds
Started Mar 03 12:32:00 PM PST 24
Finished Mar 03 12:32:19 PM PST 24
Peak memory 201168 kb
Host smart-bd180802-f143-4f30-89be-18645296fc70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755172996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3755172996
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.4258330656
Short name T841
Test name
Test status
Simulation time 579341285 ps
CPU time 1.32 seconds
Started Mar 03 12:32:04 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 209188 kb
Host smart-b21b7df2-a743-4707-a1e2-80bd51dc74ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258330656 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.4258330656
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4187358387
Short name T124
Test name
Test status
Simulation time 345092475 ps
CPU time 1.19 seconds
Started Mar 03 12:32:12 PM PST 24
Finished Mar 03 12:32:14 PM PST 24
Peak memory 200572 kb
Host smart-9a5767f8-aaaf-46a5-bb28-582a4f547b59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187358387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4187358387
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.3164581750
Short name T880
Test name
Test status
Simulation time 478250975 ps
CPU time 1.46 seconds
Started Mar 03 12:32:05 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200628 kb
Host smart-ed11b8f5-914a-4a4d-89e3-ecbc75788411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164581750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.3164581750
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2629416726
Short name T833
Test name
Test status
Simulation time 2333180913 ps
CPU time 2.56 seconds
Started Mar 03 12:31:57 PM PST 24
Finished Mar 03 12:31:59 PM PST 24
Peak memory 201352 kb
Host smart-9bc328e0-873f-499c-b95c-e0981fb25c14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629416726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2629416726
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1204253385
Short name T902
Test name
Test status
Simulation time 365919994 ps
CPU time 3.18 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 209340 kb
Host smart-9e8fd683-a1eb-4826-8cd9-5bffb9709b90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204253385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1204253385
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.3672817282
Short name T859
Test name
Test status
Simulation time 4551173688 ps
CPU time 4.35 seconds
Started Mar 03 12:31:55 PM PST 24
Finished Mar 03 12:32:00 PM PST 24
Peak memory 200360 kb
Host smart-6f477542-d0ec-412a-ac35-659c30a3c8a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672817282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.3672817282
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.752510205
Short name T844
Test name
Test status
Simulation time 535594597 ps
CPU time 1.64 seconds
Started Mar 03 12:32:04 PM PST 24
Finished Mar 03 12:32:07 PM PST 24
Peak memory 200956 kb
Host smart-e2aff702-e270-40e1-87cc-f9ef4888df67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752510205 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.752510205
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1876885557
Short name T123
Test name
Test status
Simulation time 318890162 ps
CPU time 1.47 seconds
Started Mar 03 12:32:08 PM PST 24
Finished Mar 03 12:32:12 PM PST 24
Peak memory 200820 kb
Host smart-f7964f01-112d-456d-a1db-3ada44e2a839
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876885557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1876885557
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1303374974
Short name T873
Test name
Test status
Simulation time 422818593 ps
CPU time 0.99 seconds
Started Mar 03 12:32:02 PM PST 24
Finished Mar 03 12:32:04 PM PST 24
Peak memory 200800 kb
Host smart-184dff86-9b71-4993-be91-c803c0b17908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303374974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1303374974
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.621337658
Short name T896
Test name
Test status
Simulation time 2278884462 ps
CPU time 2.18 seconds
Started Mar 03 12:32:03 PM PST 24
Finished Mar 03 12:32:06 PM PST 24
Peak memory 200592 kb
Host smart-d43e7751-e565-43cb-816e-ffb0e4ce708f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621337658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.621337658
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1554755037
Short name T336
Test name
Test status
Simulation time 8103726577 ps
CPU time 12.81 seconds
Started Mar 03 12:32:06 PM PST 24
Finished Mar 03 12:32:25 PM PST 24
Peak memory 200600 kb
Host smart-4b94cd5e-0ccb-4a39-a8e1-8fb4de289338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554755037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1554755037
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.963594272
Short name T709
Test name
Test status
Simulation time 408644565 ps
CPU time 1.62 seconds
Started Mar 03 04:15:15 PM PST 24
Finished Mar 03 04:15:17 PM PST 24
Peak memory 200680 kb
Host smart-43916760-e60f-45ea-abdd-374573f0a47b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963594272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.963594272
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2340174908
Short name T182
Test name
Test status
Simulation time 331718281295 ps
CPU time 122.93 seconds
Started Mar 03 04:15:15 PM PST 24
Finished Mar 03 04:17:18 PM PST 24
Peak memory 200948 kb
Host smart-fa01f8f9-89c4-45e6-9796-6c3b1509922d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340174908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2340174908
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2788044202
Short name T496
Test name
Test status
Simulation time 160543002521 ps
CPU time 90.13 seconds
Started Mar 03 04:15:09 PM PST 24
Finished Mar 03 04:16:39 PM PST 24
Peak memory 200896 kb
Host smart-80801dce-4219-4b99-86a0-1dd8466c78bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788044202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2788044202
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3994573558
Short name T459
Test name
Test status
Simulation time 327403362326 ps
CPU time 696.84 seconds
Started Mar 03 04:15:16 PM PST 24
Finished Mar 03 04:26:53 PM PST 24
Peak memory 200896 kb
Host smart-704543e1-83b0-4711-b324-b56d0331be64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994573558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3994573558
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.1683080027
Short name T410
Test name
Test status
Simulation time 165078079450 ps
CPU time 359.83 seconds
Started Mar 03 04:15:08 PM PST 24
Finished Mar 03 04:21:08 PM PST 24
Peak memory 200952 kb
Host smart-7cc9d2a8-74f2-4e95-b664-7c19820b38b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683080027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.1683080027
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2115390507
Short name T646
Test name
Test status
Simulation time 166016416032 ps
CPU time 214.85 seconds
Started Mar 03 04:15:10 PM PST 24
Finished Mar 03 04:18:45 PM PST 24
Peak memory 200896 kb
Host smart-813637f3-fa97-4230-9786-b1f46de21230
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115390507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2115390507
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2788268910
Short name T774
Test name
Test status
Simulation time 164347615736 ps
CPU time 200.83 seconds
Started Mar 03 04:15:16 PM PST 24
Finished Mar 03 04:18:37 PM PST 24
Peak memory 200972 kb
Host smart-6f4d556b-33ee-4d62-8614-43739525b03c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788268910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2788268910
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3623966747
Short name T556
Test name
Test status
Simulation time 480765984178 ps
CPU time 214.31 seconds
Started Mar 03 04:15:14 PM PST 24
Finished Mar 03 04:18:49 PM PST 24
Peak memory 200904 kb
Host smart-4ba7c6e9-3ede-4592-8485-130e9f28cb32
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623966747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3623966747
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2638408315
Short name T340
Test name
Test status
Simulation time 111893008516 ps
CPU time 440.95 seconds
Started Mar 03 04:15:15 PM PST 24
Finished Mar 03 04:22:36 PM PST 24
Peak memory 201328 kb
Host smart-b0bf0089-1152-4527-a99e-08e2c38c6ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638408315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2638408315
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.319198696
Short name T756
Test name
Test status
Simulation time 34361288583 ps
CPU time 21.81 seconds
Started Mar 03 04:15:16 PM PST 24
Finished Mar 03 04:15:38 PM PST 24
Peak memory 200760 kb
Host smart-847c2039-6f14-45ef-b664-23827566c451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319198696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.319198696
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.271177130
Short name T713
Test name
Test status
Simulation time 3820625986 ps
CPU time 2.15 seconds
Started Mar 03 04:15:15 PM PST 24
Finished Mar 03 04:15:17 PM PST 24
Peak memory 200752 kb
Host smart-d4d0b872-2c3c-4751-b8ef-46a7a85b81e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271177130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.271177130
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1290836572
Short name T366
Test name
Test status
Simulation time 6009351038 ps
CPU time 13.19 seconds
Started Mar 03 04:15:09 PM PST 24
Finished Mar 03 04:15:22 PM PST 24
Peak memory 200708 kb
Host smart-16efeea4-cefa-4875-a077-559fe73e482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290836572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1290836572
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1320497241
Short name T739
Test name
Test status
Simulation time 78212979646 ps
CPU time 125.02 seconds
Started Mar 03 04:15:15 PM PST 24
Finished Mar 03 04:17:20 PM PST 24
Peak memory 209720 kb
Host smart-16617b0a-6c99-4886-aa39-eb3c141a4e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320497241 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1320497241
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3790835697
Short name T588
Test name
Test status
Simulation time 428460754 ps
CPU time 0.96 seconds
Started Mar 03 04:15:33 PM PST 24
Finished Mar 03 04:15:35 PM PST 24
Peak memory 200696 kb
Host smart-7dcde0d6-9f59-4517-9449-97950f29b67b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790835697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3790835697
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.671400560
Short name T312
Test name
Test status
Simulation time 486892666252 ps
CPU time 122.07 seconds
Started Mar 03 04:15:28 PM PST 24
Finished Mar 03 04:17:31 PM PST 24
Peak memory 200928 kb
Host smart-820166c4-bb58-4559-877c-46f8c85e18af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671400560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.671400560
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2183109576
Short name T326
Test name
Test status
Simulation time 164560248705 ps
CPU time 118.11 seconds
Started Mar 03 04:15:22 PM PST 24
Finished Mar 03 04:17:20 PM PST 24
Peak memory 200932 kb
Host smart-30518628-0593-4295-9217-f144658bfb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183109576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2183109576
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.4049629503
Short name T166
Test name
Test status
Simulation time 327156667875 ps
CPU time 170.88 seconds
Started Mar 03 04:15:21 PM PST 24
Finished Mar 03 04:18:12 PM PST 24
Peak memory 200952 kb
Host smart-ab323652-c175-45a4-97a1-9070fe35c453
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049629503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.4049629503
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3688945965
Short name T436
Test name
Test status
Simulation time 326619674013 ps
CPU time 199.85 seconds
Started Mar 03 04:15:21 PM PST 24
Finished Mar 03 04:18:41 PM PST 24
Peak memory 200964 kb
Host smart-200e773c-6108-4402-acfd-ae6eb6cfccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688945965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3688945965
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3904810994
Short name T723
Test name
Test status
Simulation time 158250093169 ps
CPU time 97.68 seconds
Started Mar 03 04:15:22 PM PST 24
Finished Mar 03 04:17:00 PM PST 24
Peak memory 200968 kb
Host smart-a2a2d2de-23b5-4895-9528-5bf16aeab38d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904810994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3904810994
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2677445627
Short name T20
Test name
Test status
Simulation time 165715374665 ps
CPU time 368.34 seconds
Started Mar 03 04:15:21 PM PST 24
Finished Mar 03 04:21:30 PM PST 24
Peak memory 200968 kb
Host smart-e23b685c-e823-4b97-afc0-59f1d514e083
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677445627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2677445627
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.21061917
Short name T403
Test name
Test status
Simulation time 329631474289 ps
CPU time 789.05 seconds
Started Mar 03 04:15:22 PM PST 24
Finished Mar 03 04:28:31 PM PST 24
Peak memory 201100 kb
Host smart-91a6d118-94e9-463b-b4bf-ac54636b40b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21061917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ad
c_ctrl_filters_wakeup_fixed.21061917
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1422869212
Short name T533
Test name
Test status
Simulation time 104438728359 ps
CPU time 371.06 seconds
Started Mar 03 04:15:28 PM PST 24
Finished Mar 03 04:21:39 PM PST 24
Peak memory 201284 kb
Host smart-89ca4a17-b0f8-4b95-87b6-0f123a6b6d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422869212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1422869212
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.244617368
Short name T559
Test name
Test status
Simulation time 21699334277 ps
CPU time 14.47 seconds
Started Mar 03 04:15:29 PM PST 24
Finished Mar 03 04:15:44 PM PST 24
Peak memory 200760 kb
Host smart-b3455c16-3690-40db-9b90-92ae788691b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244617368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.244617368
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3100756871
Short name T777
Test name
Test status
Simulation time 2773326876 ps
CPU time 7.46 seconds
Started Mar 03 04:15:27 PM PST 24
Finished Mar 03 04:15:35 PM PST 24
Peak memory 200764 kb
Host smart-4628d7fe-99c4-45db-9392-a42a9fdc9373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100756871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3100756871
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2393734977
Short name T51
Test name
Test status
Simulation time 7794020901 ps
CPU time 18.66 seconds
Started Mar 03 04:15:34 PM PST 24
Finished Mar 03 04:15:53 PM PST 24
Peak memory 217252 kb
Host smart-00c92d2d-ccfc-4b7d-8153-46729ea10ca6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393734977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2393734977
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.498928863
Short name T514
Test name
Test status
Simulation time 5611764239 ps
CPU time 14.5 seconds
Started Mar 03 04:15:22 PM PST 24
Finished Mar 03 04:15:36 PM PST 24
Peak memory 200760 kb
Host smart-65727aa5-8b52-4d25-94f0-43911cfb1296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498928863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.498928863
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3487007834
Short name T591
Test name
Test status
Simulation time 441134870009 ps
CPU time 1403.94 seconds
Started Mar 03 04:15:34 PM PST 24
Finished Mar 03 04:38:58 PM PST 24
Peak memory 201276 kb
Host smart-5b73e259-c7f2-4eb7-9e7d-683297ae7523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487007834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3487007834
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2433693083
Short name T92
Test name
Test status
Simulation time 49570389678 ps
CPU time 115.7 seconds
Started Mar 03 04:15:33 PM PST 24
Finished Mar 03 04:17:29 PM PST 24
Peak memory 201028 kb
Host smart-0c9c4642-0c9c-4923-bf5e-308b93ca4f76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433693083 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2433693083
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1761589225
Short name T107
Test name
Test status
Simulation time 535171136 ps
CPU time 0.88 seconds
Started Mar 03 04:17:35 PM PST 24
Finished Mar 03 04:17:36 PM PST 24
Peak memory 200688 kb
Host smart-c135c630-496d-4c99-ac15-6aaae135e26f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761589225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1761589225
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.4229576269
Short name T762
Test name
Test status
Simulation time 318921139700 ps
CPU time 727.24 seconds
Started Mar 03 04:17:31 PM PST 24
Finished Mar 03 04:29:39 PM PST 24
Peak memory 200960 kb
Host smart-9be39446-101b-4102-a192-a39fba7999e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229576269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.4229576269
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.797207071
Short name T280
Test name
Test status
Simulation time 332979233582 ps
CPU time 804.27 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:30:56 PM PST 24
Peak memory 200960 kb
Host smart-e864a481-c90d-4bef-904c-e6da700ab3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797207071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.797207071
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.909331858
Short name T520
Test name
Test status
Simulation time 330979268589 ps
CPU time 191.67 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:20:43 PM PST 24
Peak memory 200828 kb
Host smart-eec9e30a-fd63-492c-a9da-70e126289bb4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=909331858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.909331858
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3212810199
Short name T748
Test name
Test status
Simulation time 164163135667 ps
CPU time 155.73 seconds
Started Mar 03 04:17:31 PM PST 24
Finished Mar 03 04:20:08 PM PST 24
Peak memory 200840 kb
Host smart-86d03c52-5d75-4f75-901e-3427d8985a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212810199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3212810199
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1614009286
Short name T354
Test name
Test status
Simulation time 331349517641 ps
CPU time 697.05 seconds
Started Mar 03 04:17:32 PM PST 24
Finished Mar 03 04:29:10 PM PST 24
Peak memory 200824 kb
Host smart-a8057aa7-dc09-411a-8aba-05340b3771f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614009286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1614009286
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3578063618
Short name T432
Test name
Test status
Simulation time 95717246456 ps
CPU time 369.72 seconds
Started Mar 03 04:17:36 PM PST 24
Finished Mar 03 04:23:46 PM PST 24
Peak memory 201328 kb
Host smart-74a40e82-b367-45e4-ae81-3c0aabbea946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578063618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3578063618
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2327540199
Short name T699
Test name
Test status
Simulation time 33702374607 ps
CPU time 14.16 seconds
Started Mar 03 04:17:36 PM PST 24
Finished Mar 03 04:17:50 PM PST 24
Peak memory 200684 kb
Host smart-3a4c3a1d-3dc9-4dd2-8d7a-09fbcc8f7eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327540199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2327540199
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.4270972055
Short name T689
Test name
Test status
Simulation time 5288425734 ps
CPU time 1.45 seconds
Started Mar 03 04:17:29 PM PST 24
Finished Mar 03 04:17:31 PM PST 24
Peak memory 200744 kb
Host smart-b1e53cf2-25b8-4214-8b7d-efd6f9acd767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270972055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4270972055
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2310402227
Short name T710
Test name
Test status
Simulation time 5908813700 ps
CPU time 4.17 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:17:35 PM PST 24
Peak memory 200756 kb
Host smart-07d98383-66e9-4774-b55c-a7e81879a2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310402227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2310402227
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1849603078
Short name T47
Test name
Test status
Simulation time 337027181000 ps
CPU time 202.2 seconds
Started Mar 03 04:17:37 PM PST 24
Finished Mar 03 04:21:00 PM PST 24
Peak memory 201076 kb
Host smart-dbfc5f0d-4ca8-4f74-a8a5-7965d09f9be5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849603078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1849603078
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.4042027481
Short name T98
Test name
Test status
Simulation time 32695986767 ps
CPU time 76.84 seconds
Started Mar 03 04:17:35 PM PST 24
Finished Mar 03 04:18:52 PM PST 24
Peak memory 209724 kb
Host smart-84969efb-4563-4997-b5ba-9450cfd09ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042027481 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.4042027481
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4098551677
Short name T666
Test name
Test status
Simulation time 440287464 ps
CPU time 0.91 seconds
Started Mar 03 04:17:49 PM PST 24
Finished Mar 03 04:17:50 PM PST 24
Peak memory 200692 kb
Host smart-fc4c6083-22fb-49f6-b404-189b51b0d02c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098551677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4098551677
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2212955951
Short name T607
Test name
Test status
Simulation time 160180688445 ps
CPU time 78.32 seconds
Started Mar 03 04:17:39 PM PST 24
Finished Mar 03 04:18:57 PM PST 24
Peak memory 200980 kb
Host smart-60f1f367-8f19-4fb5-945e-9126f0f91e39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212955951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2212955951
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3955040375
Short name T612
Test name
Test status
Simulation time 503535716811 ps
CPU time 505.73 seconds
Started Mar 03 04:17:39 PM PST 24
Finished Mar 03 04:26:05 PM PST 24
Peak memory 200924 kb
Host smart-4268227c-3afa-430e-8faa-e0971c15e28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955040375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3955040375
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2621561208
Short name T468
Test name
Test status
Simulation time 167259190216 ps
CPU time 185.3 seconds
Started Mar 03 04:17:41 PM PST 24
Finished Mar 03 04:20:46 PM PST 24
Peak memory 200892 kb
Host smart-b0b42da2-dde7-43f1-b949-3b5bd01b8410
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621561208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2621561208
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.113994825
Short name T316
Test name
Test status
Simulation time 496802057022 ps
CPU time 428.4 seconds
Started Mar 03 04:17:36 PM PST 24
Finished Mar 03 04:24:45 PM PST 24
Peak memory 200908 kb
Host smart-075d6461-f7b4-4eec-8828-fc2d3cfb3158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113994825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.113994825
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2909063792
Short name T622
Test name
Test status
Simulation time 166175070130 ps
CPU time 102.06 seconds
Started Mar 03 04:17:39 PM PST 24
Finished Mar 03 04:19:22 PM PST 24
Peak memory 200908 kb
Host smart-095a195a-bdb4-4a20-9d72-3cf726ed1c29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909063792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2909063792
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1832142306
Short name T325
Test name
Test status
Simulation time 492771959124 ps
CPU time 413.82 seconds
Started Mar 03 04:17:39 PM PST 24
Finished Mar 03 04:24:33 PM PST 24
Peak memory 200904 kb
Host smart-9291267e-ac90-412c-8830-4fd59fe54304
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832142306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1832142306
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.266292826
Short name T724
Test name
Test status
Simulation time 328888868885 ps
CPU time 324.04 seconds
Started Mar 03 04:17:41 PM PST 24
Finished Mar 03 04:23:05 PM PST 24
Peak memory 200896 kb
Host smart-a62ab2c7-c263-4bb1-8e2e-4f9bcfa1ec06
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266292826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.266292826
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4159391234
Short name T665
Test name
Test status
Simulation time 99855737179 ps
CPU time 381.63 seconds
Started Mar 03 04:17:44 PM PST 24
Finished Mar 03 04:24:06 PM PST 24
Peak memory 201404 kb
Host smart-9694e325-4b78-4737-9a29-4a7aeacba3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159391234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4159391234
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2479059437
Short name T389
Test name
Test status
Simulation time 29726476762 ps
CPU time 16.91 seconds
Started Mar 03 04:17:49 PM PST 24
Finished Mar 03 04:18:06 PM PST 24
Peak memory 200748 kb
Host smart-a4fd9d23-8ed0-4c6a-9660-a823aeaf3c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479059437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2479059437
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.626295024
Short name T531
Test name
Test status
Simulation time 4228714563 ps
CPU time 10.42 seconds
Started Mar 03 04:17:45 PM PST 24
Finished Mar 03 04:17:56 PM PST 24
Peak memory 200708 kb
Host smart-12c4a67c-1699-48e9-bd1a-bb234fc2b311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626295024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.626295024
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2521046607
Short name T488
Test name
Test status
Simulation time 5886697942 ps
CPU time 7.82 seconds
Started Mar 03 04:17:36 PM PST 24
Finished Mar 03 04:17:44 PM PST 24
Peak memory 200756 kb
Host smart-3a2cde87-b6a6-447a-92bc-ab552e4a820c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521046607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2521046607
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2660481522
Short name T455
Test name
Test status
Simulation time 357078777 ps
CPU time 0.85 seconds
Started Mar 03 04:17:56 PM PST 24
Finished Mar 03 04:17:56 PM PST 24
Peak memory 200700 kb
Host smart-dc98a342-e7cd-4855-b204-d933a4718613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660481522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2660481522
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2351405344
Short name T17
Test name
Test status
Simulation time 333901514219 ps
CPU time 213.08 seconds
Started Mar 03 04:17:51 PM PST 24
Finished Mar 03 04:21:24 PM PST 24
Peak memory 200888 kb
Host smart-e6b8240b-b54a-465f-8f41-cc4d3de19d59
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351405344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2351405344
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2108890273
Short name T701
Test name
Test status
Simulation time 162983168619 ps
CPU time 100.06 seconds
Started Mar 03 04:17:55 PM PST 24
Finished Mar 03 04:19:35 PM PST 24
Peak memory 200976 kb
Host smart-6f2a1859-8c38-49b3-b515-871ad25671bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108890273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2108890273
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2319839581
Short name T381
Test name
Test status
Simulation time 329576727191 ps
CPU time 218.5 seconds
Started Mar 03 04:17:52 PM PST 24
Finished Mar 03 04:21:31 PM PST 24
Peak memory 200900 kb
Host smart-7dbbfdd0-c73b-4c7c-b0a7-067e9266130b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319839581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2319839581
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1188388388
Short name T285
Test name
Test status
Simulation time 327615163225 ps
CPU time 186.61 seconds
Started Mar 03 04:17:50 PM PST 24
Finished Mar 03 04:20:56 PM PST 24
Peak memory 200912 kb
Host smart-860bb33f-b1c4-4751-a972-02c3a498ee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188388388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1188388388
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.384693430
Short name T509
Test name
Test status
Simulation time 162265143166 ps
CPU time 100.33 seconds
Started Mar 03 04:17:51 PM PST 24
Finished Mar 03 04:19:32 PM PST 24
Peak memory 200884 kb
Host smart-fb0b224c-8e43-4fd2-816b-43c77e92ced9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=384693430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.384693430
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1427704668
Short name T677
Test name
Test status
Simulation time 168630174608 ps
CPU time 411.57 seconds
Started Mar 03 04:17:55 PM PST 24
Finished Mar 03 04:24:46 PM PST 24
Peak memory 200912 kb
Host smart-c4f34174-6bdb-4a0b-babb-7908ce4fd372
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427704668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1427704668
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1973579299
Short name T590
Test name
Test status
Simulation time 484982848117 ps
CPU time 738.33 seconds
Started Mar 03 04:17:54 PM PST 24
Finished Mar 03 04:30:13 PM PST 24
Peak memory 200908 kb
Host smart-53228dc5-382f-4d2b-9df8-74172f64adfb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973579299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1973579299
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1645837723
Short name T367
Test name
Test status
Simulation time 40207013190 ps
CPU time 24.96 seconds
Started Mar 03 04:17:55 PM PST 24
Finished Mar 03 04:18:21 PM PST 24
Peak memory 200760 kb
Host smart-58aa3cd3-e67c-4908-8ba6-50f1b10d02ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645837723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1645837723
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2051220957
Short name T707
Test name
Test status
Simulation time 3828791401 ps
CPU time 2.75 seconds
Started Mar 03 04:17:56 PM PST 24
Finished Mar 03 04:17:58 PM PST 24
Peak memory 200740 kb
Host smart-ab6a14aa-103d-4932-ab7a-b9f82cb93683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051220957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2051220957
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.503632057
Short name T379
Test name
Test status
Simulation time 6181360777 ps
CPU time 8.17 seconds
Started Mar 03 04:17:52 PM PST 24
Finished Mar 03 04:18:00 PM PST 24
Peak memory 200756 kb
Host smart-38632083-e592-41a1-b34e-092188690b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503632057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.503632057
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1778465867
Short name T173
Test name
Test status
Simulation time 495197606849 ps
CPU time 1115.58 seconds
Started Mar 03 04:17:57 PM PST 24
Finished Mar 03 04:36:33 PM PST 24
Peak memory 200964 kb
Host smart-e718a121-820a-427c-afc4-468a5178f4af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778465867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1778465867
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.199847415
Short name T60
Test name
Test status
Simulation time 144715103777 ps
CPU time 153.16 seconds
Started Mar 03 04:17:55 PM PST 24
Finished Mar 03 04:20:29 PM PST 24
Peak memory 209632 kb
Host smart-69f71110-05e2-4dac-911c-4c24ef1a4283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199847415 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.199847415
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1468124295
Short name T79
Test name
Test status
Simulation time 353286863 ps
CPU time 1.49 seconds
Started Mar 03 04:18:07 PM PST 24
Finished Mar 03 04:18:09 PM PST 24
Peak memory 200692 kb
Host smart-6a861a6e-cd15-4d9f-9f24-9a0d35c87295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468124295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1468124295
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.777689155
Short name T573
Test name
Test status
Simulation time 161268678307 ps
CPU time 24.21 seconds
Started Mar 03 04:18:00 PM PST 24
Finished Mar 03 04:18:24 PM PST 24
Peak memory 200884 kb
Host smart-4cf6af41-50e4-409c-aa7d-9f046c0ddfa0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777689155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.777689155
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2771281624
Short name T254
Test name
Test status
Simulation time 495804326727 ps
CPU time 1028.4 seconds
Started Mar 03 04:18:09 PM PST 24
Finished Mar 03 04:35:17 PM PST 24
Peak memory 200908 kb
Host smart-9ae7f4d7-abcb-42cb-a2fe-a3bf4a5b616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771281624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2771281624
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.729453430
Short name T323
Test name
Test status
Simulation time 159584362057 ps
CPU time 339.95 seconds
Started Mar 03 04:18:00 PM PST 24
Finished Mar 03 04:23:40 PM PST 24
Peak memory 200960 kb
Host smart-8fd51667-eb56-43b7-afda-31c88db78f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729453430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.729453430
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.21098931
Short name T547
Test name
Test status
Simulation time 163131558213 ps
CPU time 412.97 seconds
Started Mar 03 04:18:02 PM PST 24
Finished Mar 03 04:24:56 PM PST 24
Peak memory 200892 kb
Host smart-b36913fc-0177-4c7a-984a-38048ebaa4a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=21098931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt
_fixed.21098931
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3626648473
Short name T578
Test name
Test status
Simulation time 330585030322 ps
CPU time 411.71 seconds
Started Mar 03 04:17:57 PM PST 24
Finished Mar 03 04:24:49 PM PST 24
Peak memory 200908 kb
Host smart-04b11cfd-388e-4622-ad61-929800cdacb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626648473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3626648473
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.70285990
Short name T575
Test name
Test status
Simulation time 335201820199 ps
CPU time 415.39 seconds
Started Mar 03 04:17:58 PM PST 24
Finished Mar 03 04:24:54 PM PST 24
Peak memory 200872 kb
Host smart-b468061c-2411-41cb-aaaf-a4c96135a28a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70285990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.a
dc_ctrl_filters_wakeup_fixed.70285990
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1833590648
Short name T638
Test name
Test status
Simulation time 134125225634 ps
CPU time 460.79 seconds
Started Mar 03 04:18:07 PM PST 24
Finished Mar 03 04:25:48 PM PST 24
Peak memory 201392 kb
Host smart-56d26dee-6703-47d6-a44b-2ba06f907e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833590648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1833590648
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.389568202
Short name T358
Test name
Test status
Simulation time 30821433419 ps
CPU time 36.82 seconds
Started Mar 03 04:18:07 PM PST 24
Finished Mar 03 04:18:44 PM PST 24
Peak memory 200736 kb
Host smart-c29182cb-fbc7-49c1-8fe6-6072b2e75870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389568202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.389568202
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.658315866
Short name T473
Test name
Test status
Simulation time 2983487995 ps
CPU time 6.01 seconds
Started Mar 03 04:18:07 PM PST 24
Finished Mar 03 04:18:14 PM PST 24
Peak memory 200716 kb
Host smart-0acf4bc6-5e84-43aa-81c9-873c78c73887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658315866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.658315866
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.958431365
Short name T751
Test name
Test status
Simulation time 5992695146 ps
CPU time 4.14 seconds
Started Mar 03 04:17:58 PM PST 24
Finished Mar 03 04:18:03 PM PST 24
Peak memory 200760 kb
Host smart-748ecb9b-0c7c-48a6-a560-cdbb489df246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958431365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.958431365
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3735903377
Short name T365
Test name
Test status
Simulation time 452270991 ps
CPU time 1.46 seconds
Started Mar 03 04:18:17 PM PST 24
Finished Mar 03 04:18:19 PM PST 24
Peak memory 200592 kb
Host smart-047b8042-e62a-4d64-9675-733b8d74e993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735903377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3735903377
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.784125203
Short name T334
Test name
Test status
Simulation time 493980792198 ps
CPU time 195.65 seconds
Started Mar 03 04:18:11 PM PST 24
Finished Mar 03 04:21:27 PM PST 24
Peak memory 200880 kb
Host smart-93dd457b-89ca-4d24-8b70-2518883df4a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784125203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.784125203
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.85922170
Short name T194
Test name
Test status
Simulation time 337180365300 ps
CPU time 146.74 seconds
Started Mar 03 04:18:13 PM PST 24
Finished Mar 03 04:20:40 PM PST 24
Peak memory 200972 kb
Host smart-1172535c-e208-484f-bbbb-f55b2b9f316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85922170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.85922170
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1862389589
Short name T553
Test name
Test status
Simulation time 162329597095 ps
CPU time 180.41 seconds
Started Mar 03 04:18:12 PM PST 24
Finished Mar 03 04:21:13 PM PST 24
Peak memory 200968 kb
Host smart-92ba874f-8b3d-40d3-b630-d595abdff3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862389589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1862389589
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2463318584
Short name T201
Test name
Test status
Simulation time 164414348803 ps
CPU time 92.47 seconds
Started Mar 03 04:18:12 PM PST 24
Finished Mar 03 04:19:45 PM PST 24
Peak memory 200872 kb
Host smart-f82f1c51-4b18-451a-919d-75a179182eff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463318584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2463318584
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3906999960
Short name T171
Test name
Test status
Simulation time 162354444918 ps
CPU time 186.19 seconds
Started Mar 03 04:18:11 PM PST 24
Finished Mar 03 04:21:17 PM PST 24
Peak memory 200836 kb
Host smart-f1718a41-9fca-4ce8-81f1-624e831a5476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906999960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3906999960
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3209898645
Short name T384
Test name
Test status
Simulation time 491627488446 ps
CPU time 131.48 seconds
Started Mar 03 04:18:13 PM PST 24
Finished Mar 03 04:20:25 PM PST 24
Peak memory 200892 kb
Host smart-5b55a8bd-1d20-47f9-8d80-8cb5fdf9a340
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209898645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3209898645
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3549821590
Short name T154
Test name
Test status
Simulation time 334160950712 ps
CPU time 763.37 seconds
Started Mar 03 04:18:14 PM PST 24
Finished Mar 03 04:30:58 PM PST 24
Peak memory 200964 kb
Host smart-956f5b21-cf6e-47af-bd1f-3f773e8212aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549821590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3549821590
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.883943492
Short name T281
Test name
Test status
Simulation time 163536441753 ps
CPU time 189.8 seconds
Started Mar 03 04:18:12 PM PST 24
Finished Mar 03 04:21:23 PM PST 24
Peak memory 200896 kb
Host smart-83497b2f-8d22-4309-972e-7523652fc6b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883943492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.883943492
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1757411272
Short name T572
Test name
Test status
Simulation time 82541288197 ps
CPU time 350.1 seconds
Started Mar 03 04:18:17 PM PST 24
Finished Mar 03 04:24:08 PM PST 24
Peak memory 201400 kb
Host smart-6c15e671-353b-458e-bb1c-c8c0d2037c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757411272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1757411272
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3541969819
Short name T737
Test name
Test status
Simulation time 44650819150 ps
CPU time 10.47 seconds
Started Mar 03 04:18:18 PM PST 24
Finished Mar 03 04:18:29 PM PST 24
Peak memory 200724 kb
Host smart-cfe77c7a-311d-42ec-97ce-ee5f47865c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541969819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3541969819
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3900758200
Short name T611
Test name
Test status
Simulation time 5110193732 ps
CPU time 12.51 seconds
Started Mar 03 04:18:12 PM PST 24
Finished Mar 03 04:18:25 PM PST 24
Peak memory 200956 kb
Host smart-ee782518-f462-4752-9950-438a782e5642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900758200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3900758200
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1835454307
Short name T401
Test name
Test status
Simulation time 6014477901 ps
CPU time 4.4 seconds
Started Mar 03 04:18:07 PM PST 24
Finished Mar 03 04:18:11 PM PST 24
Peak memory 200760 kb
Host smart-661a9098-94d7-4b41-943f-652686e0be83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835454307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1835454307
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.206999091
Short name T70
Test name
Test status
Simulation time 61063599719 ps
CPU time 151.51 seconds
Started Mar 03 04:18:18 PM PST 24
Finished Mar 03 04:20:50 PM PST 24
Peak memory 209240 kb
Host smart-2826d9cb-a1b5-475f-bae9-19cbdf0e3201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206999091 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.206999091
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3560536640
Short name T679
Test name
Test status
Simulation time 514404008 ps
CPU time 1.84 seconds
Started Mar 03 04:18:30 PM PST 24
Finished Mar 03 04:18:33 PM PST 24
Peak memory 200688 kb
Host smart-129abefb-242a-4a35-ab0a-4344cbfa9d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560536640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3560536640
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2389351321
Short name T228
Test name
Test status
Simulation time 483256027826 ps
CPU time 722.51 seconds
Started Mar 03 04:18:23 PM PST 24
Finished Mar 03 04:30:26 PM PST 24
Peak memory 200884 kb
Host smart-9ab641bc-fab7-4be2-8290-efb328607944
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389351321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2389351321
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.4190446220
Short name T167
Test name
Test status
Simulation time 332130799095 ps
CPU time 131.97 seconds
Started Mar 03 04:18:24 PM PST 24
Finished Mar 03 04:20:36 PM PST 24
Peak memory 200980 kb
Host smart-f22535e0-2e11-4616-b5cc-1e52319e95ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190446220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.4190446220
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3275183550
Short name T702
Test name
Test status
Simulation time 487167352033 ps
CPU time 1158.04 seconds
Started Mar 03 04:18:27 PM PST 24
Finished Mar 03 04:37:45 PM PST 24
Peak memory 200888 kb
Host smart-9b1bb3a4-01b1-47c8-b073-b8aed23f4904
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275183550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3275183550
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.731149506
Short name T784
Test name
Test status
Simulation time 495531445809 ps
CPU time 148.1 seconds
Started Mar 03 04:18:23 PM PST 24
Finished Mar 03 04:20:52 PM PST 24
Peak memory 200976 kb
Host smart-48609fc1-9502-4625-b206-9b43b9f3916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731149506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.731149506
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.3420540339
Short name T407
Test name
Test status
Simulation time 482750830343 ps
CPU time 1193.79 seconds
Started Mar 03 04:18:23 PM PST 24
Finished Mar 03 04:38:18 PM PST 24
Peak memory 200896 kb
Host smart-121b7aa5-6a66-4f52-92d4-52390b6571a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420540339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.3420540339
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1493464259
Short name T697
Test name
Test status
Simulation time 160940200496 ps
CPU time 361.11 seconds
Started Mar 03 04:18:24 PM PST 24
Finished Mar 03 04:24:26 PM PST 24
Peak memory 200876 kb
Host smart-0a153165-7d37-4f04-ad47-3647bd4dbcf2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493464259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1493464259
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1778311016
Short name T787
Test name
Test status
Simulation time 39653837582 ps
CPU time 94.36 seconds
Started Mar 03 04:18:32 PM PST 24
Finished Mar 03 04:20:07 PM PST 24
Peak memory 200752 kb
Host smart-df7fe9bd-0371-4033-b207-76739db8d20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778311016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1778311016
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3533883768
Short name T536
Test name
Test status
Simulation time 3702665965 ps
CPU time 9.54 seconds
Started Mar 03 04:18:27 PM PST 24
Finished Mar 03 04:18:37 PM PST 24
Peak memory 200764 kb
Host smart-d2c60f91-88cd-4a3c-a7f7-c0994048e2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533883768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3533883768
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1330626018
Short name T428
Test name
Test status
Simulation time 5758116000 ps
CPU time 2.58 seconds
Started Mar 03 04:18:16 PM PST 24
Finished Mar 03 04:18:19 PM PST 24
Peak memory 200760 kb
Host smart-700cc49a-9b1f-4aff-8beb-38d99f4cee24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330626018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1330626018
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.3402904253
Short name T56
Test name
Test status
Simulation time 204590614055 ps
CPU time 323.24 seconds
Started Mar 03 04:18:34 PM PST 24
Finished Mar 03 04:23:58 PM PST 24
Peak memory 200944 kb
Host smart-b949c76c-4a6e-4975-a34b-eebcb841ab56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402904253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.3402904253
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1442352283
Short name T776
Test name
Test status
Simulation time 165206593685 ps
CPU time 113.58 seconds
Started Mar 03 04:18:35 PM PST 24
Finished Mar 03 04:20:28 PM PST 24
Peak memory 200904 kb
Host smart-78af23c9-f159-49e9-adcb-78db0d04663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442352283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1442352283
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2136725707
Short name T279
Test name
Test status
Simulation time 341200605931 ps
CPU time 781.99 seconds
Started Mar 03 04:18:35 PM PST 24
Finished Mar 03 04:31:38 PM PST 24
Peak memory 200916 kb
Host smart-1789a6b5-ba2f-4e1c-976a-ac81356e928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136725707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2136725707
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1553361409
Short name T786
Test name
Test status
Simulation time 166675834091 ps
CPU time 210.39 seconds
Started Mar 03 04:18:31 PM PST 24
Finished Mar 03 04:22:01 PM PST 24
Peak memory 200904 kb
Host smart-d5af7689-21c6-4741-95d1-32992bed77cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553361409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1553361409
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1406793727
Short name T178
Test name
Test status
Simulation time 330275909532 ps
CPU time 203.66 seconds
Started Mar 03 04:18:36 PM PST 24
Finished Mar 03 04:22:00 PM PST 24
Peak memory 200972 kb
Host smart-ea300ecb-dddb-40b7-ab39-760626732d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406793727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1406793727
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3620516182
Short name T715
Test name
Test status
Simulation time 483139133396 ps
CPU time 990.48 seconds
Started Mar 03 04:18:30 PM PST 24
Finished Mar 03 04:35:01 PM PST 24
Peak memory 200968 kb
Host smart-72833c51-21b1-4ab0-ad3b-398c1fca207e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620516182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3620516182
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1988158609
Short name T310
Test name
Test status
Simulation time 327676104740 ps
CPU time 759.45 seconds
Started Mar 03 04:18:35 PM PST 24
Finished Mar 03 04:31:15 PM PST 24
Peak memory 200900 kb
Host smart-f988b48a-114e-49a6-b0c8-a28b28e9d762
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988158609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1988158609
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3008181038
Short name T5
Test name
Test status
Simulation time 493225985881 ps
CPU time 525.6 seconds
Started Mar 03 04:18:36 PM PST 24
Finished Mar 03 04:27:22 PM PST 24
Peak memory 200960 kb
Host smart-18886d4a-b1ee-4b1e-9bc5-152ba0736642
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008181038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3008181038
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2284080535
Short name T657
Test name
Test status
Simulation time 133840641103 ps
CPU time 488.18 seconds
Started Mar 03 04:18:35 PM PST 24
Finished Mar 03 04:26:44 PM PST 24
Peak memory 201332 kb
Host smart-eda21418-3ab8-44cb-8d2c-d2b1a2c42558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284080535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2284080535
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2069585729
Short name T539
Test name
Test status
Simulation time 38795734904 ps
CPU time 79.94 seconds
Started Mar 03 04:18:36 PM PST 24
Finished Mar 03 04:19:56 PM PST 24
Peak memory 200736 kb
Host smart-f64d2bf4-f617-4063-b7ac-a35193df4e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069585729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2069585729
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3514373595
Short name T404
Test name
Test status
Simulation time 5256647251 ps
CPU time 13.86 seconds
Started Mar 03 04:18:38 PM PST 24
Finished Mar 03 04:18:53 PM PST 24
Peak memory 200768 kb
Host smart-f597bc3c-de46-4ed9-a2ed-9bdad7866f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514373595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3514373595
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3023355418
Short name T485
Test name
Test status
Simulation time 5756808576 ps
CPU time 7.6 seconds
Started Mar 03 04:18:34 PM PST 24
Finished Mar 03 04:18:42 PM PST 24
Peak memory 200712 kb
Host smart-b76a1aa9-5498-4669-8d17-9a89a5581df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023355418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3023355418
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3103691751
Short name T217
Test name
Test status
Simulation time 322765843611 ps
CPU time 569.34 seconds
Started Mar 03 04:18:35 PM PST 24
Finished Mar 03 04:28:05 PM PST 24
Peak memory 211852 kb
Host smart-1f01ba9d-ad3e-4f7f-966e-40dde1e2e28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103691751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3103691751
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.769987009
Short name T346
Test name
Test status
Simulation time 403301727 ps
CPU time 1.07 seconds
Started Mar 03 04:18:47 PM PST 24
Finished Mar 03 04:18:49 PM PST 24
Peak memory 200676 kb
Host smart-75ddd996-2cbe-4891-aeed-6f25bed00e00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769987009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.769987009
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3153522351
Short name T268
Test name
Test status
Simulation time 166105916458 ps
CPU time 101.59 seconds
Started Mar 03 04:18:47 PM PST 24
Finished Mar 03 04:20:29 PM PST 24
Peak memory 200928 kb
Host smart-d3908df9-2154-4be6-b364-6290e6ef1c5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153522351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3153522351
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2393601586
Short name T729
Test name
Test status
Simulation time 329452495403 ps
CPU time 734.16 seconds
Started Mar 03 04:18:45 PM PST 24
Finished Mar 03 04:31:01 PM PST 24
Peak memory 200968 kb
Host smart-e54f6df5-a84e-43fd-9481-d7b219c4d567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393601586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2393601586
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3228762494
Short name T486
Test name
Test status
Simulation time 331506956116 ps
CPU time 814.5 seconds
Started Mar 03 04:18:44 PM PST 24
Finished Mar 03 04:32:20 PM PST 24
Peak memory 200940 kb
Host smart-7f4dee7a-4e6a-46a3-a985-833d923a4a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228762494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3228762494
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.774817907
Short name T495
Test name
Test status
Simulation time 169495890198 ps
CPU time 27.18 seconds
Started Mar 03 04:18:41 PM PST 24
Finished Mar 03 04:19:09 PM PST 24
Peak memory 200908 kb
Host smart-ccc58e3f-5e82-4e7a-9032-91e705809ebf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=774817907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.774817907
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.188929971
Short name T434
Test name
Test status
Simulation time 487824231043 ps
CPU time 339.66 seconds
Started Mar 03 04:18:44 PM PST 24
Finished Mar 03 04:24:24 PM PST 24
Peak memory 200944 kb
Host smart-35b4045e-daa5-45a5-8d88-496d0ea89e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188929971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.188929971
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2632661718
Short name T453
Test name
Test status
Simulation time 329682144751 ps
CPU time 236.02 seconds
Started Mar 03 04:18:41 PM PST 24
Finished Mar 03 04:22:37 PM PST 24
Peak memory 200904 kb
Host smart-058754dd-5300-45ea-99dc-d534d30654db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632661718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2632661718
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2487049628
Short name T542
Test name
Test status
Simulation time 320774616248 ps
CPU time 365.36 seconds
Started Mar 03 04:18:44 PM PST 24
Finished Mar 03 04:24:51 PM PST 24
Peak memory 200908 kb
Host smart-9db266ea-91ed-4338-acae-e951ee48fa5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487049628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2487049628
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.273412350
Short name T726
Test name
Test status
Simulation time 161772915334 ps
CPU time 183.32 seconds
Started Mar 03 04:18:46 PM PST 24
Finished Mar 03 04:21:51 PM PST 24
Peak memory 200900 kb
Host smart-2eaa88b5-0167-4fd5-b48b-613f514481a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273412350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.273412350
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.52288010
Short name T598
Test name
Test status
Simulation time 106529430006 ps
CPU time 404.37 seconds
Started Mar 03 04:18:47 PM PST 24
Finished Mar 03 04:25:32 PM PST 24
Peak memory 201312 kb
Host smart-4eb60843-548b-4bff-a215-cb29b8fc4c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52288010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.52288010
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3774788191
Short name T530
Test name
Test status
Simulation time 43083663282 ps
CPU time 92.24 seconds
Started Mar 03 04:18:47 PM PST 24
Finished Mar 03 04:20:20 PM PST 24
Peak memory 200760 kb
Host smart-acca1910-3f3c-465f-90df-d3c256e64a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774788191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3774788191
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1898908921
Short name T738
Test name
Test status
Simulation time 5375058881 ps
CPU time 14.07 seconds
Started Mar 03 04:18:50 PM PST 24
Finished Mar 03 04:19:06 PM PST 24
Peak memory 200792 kb
Host smart-d465bacf-9c4f-40e6-a774-46ec180e5171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898908921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1898908921
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2266229064
Short name T347
Test name
Test status
Simulation time 5599557609 ps
CPU time 13.88 seconds
Started Mar 03 04:18:40 PM PST 24
Finished Mar 03 04:18:54 PM PST 24
Peak memory 200760 kb
Host smart-faaa3d94-02e8-4219-8de5-6c12a1199939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266229064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2266229064
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3724509863
Short name T415
Test name
Test status
Simulation time 41222267305 ps
CPU time 94.73 seconds
Started Mar 03 04:18:47 PM PST 24
Finished Mar 03 04:20:23 PM PST 24
Peak memory 200764 kb
Host smart-a8351eb1-449c-4e9f-9d55-2b82348c860b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724509863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3724509863
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3766669179
Short name T656
Test name
Test status
Simulation time 117248329445 ps
CPU time 227.43 seconds
Started Mar 03 04:18:46 PM PST 24
Finished Mar 03 04:22:35 PM PST 24
Peak memory 209604 kb
Host smart-b991c04c-3771-48db-9791-257ea257cc7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766669179 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3766669179
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3736641180
Short name T382
Test name
Test status
Simulation time 549753161 ps
CPU time 0.75 seconds
Started Mar 03 04:18:56 PM PST 24
Finished Mar 03 04:18:57 PM PST 24
Peak memory 200628 kb
Host smart-c4f442ea-31b4-47bb-8755-86ebd119e4bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736641180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3736641180
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.137182730
Short name T460
Test name
Test status
Simulation time 163953173896 ps
CPU time 8.37 seconds
Started Mar 03 04:18:53 PM PST 24
Finished Mar 03 04:19:02 PM PST 24
Peak memory 200880 kb
Host smart-d41cc090-a6d4-4120-b143-9a932fa7f6fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137182730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.137182730
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2655316329
Short name T227
Test name
Test status
Simulation time 325160032602 ps
CPU time 363.12 seconds
Started Mar 03 04:18:56 PM PST 24
Finished Mar 03 04:25:00 PM PST 24
Peak memory 200904 kb
Host smart-4dd2bfe1-53c7-4197-8b61-e4b9d9919bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655316329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2655316329
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1240164571
Short name T681
Test name
Test status
Simulation time 329421860702 ps
CPU time 212.18 seconds
Started Mar 03 04:18:45 PM PST 24
Finished Mar 03 04:22:19 PM PST 24
Peak memory 200964 kb
Host smart-6731281e-cafa-4040-a596-f2b53eab60df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240164571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1240164571
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.655582845
Short name T480
Test name
Test status
Simulation time 501824451613 ps
CPU time 292.7 seconds
Started Mar 03 04:18:50 PM PST 24
Finished Mar 03 04:23:44 PM PST 24
Peak memory 200976 kb
Host smart-34e3df9f-c84c-49b1-be24-6ea2351453d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=655582845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.655582845
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.371454054
Short name T275
Test name
Test status
Simulation time 329203666383 ps
CPU time 370.03 seconds
Started Mar 03 04:18:46 PM PST 24
Finished Mar 03 04:24:58 PM PST 24
Peak memory 200900 kb
Host smart-e6c8a942-7ed9-4593-8e9c-961bb8c7ae28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371454054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.371454054
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.234562644
Short name T456
Test name
Test status
Simulation time 488247173454 ps
CPU time 230.28 seconds
Started Mar 03 04:18:46 PM PST 24
Finished Mar 03 04:22:38 PM PST 24
Peak memory 200892 kb
Host smart-39b5b77e-a462-4e79-82a7-cccb466e2e18
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=234562644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.234562644
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.138794438
Short name T162
Test name
Test status
Simulation time 338041365449 ps
CPU time 767.24 seconds
Started Mar 03 04:18:51 PM PST 24
Finished Mar 03 04:31:39 PM PST 24
Peak memory 200836 kb
Host smart-a66da2c3-cd5c-4df6-9ec1-b5906bd23a4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138794438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.138794438
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2408708393
Short name T373
Test name
Test status
Simulation time 326198689528 ps
CPU time 385.39 seconds
Started Mar 03 04:18:51 PM PST 24
Finished Mar 03 04:25:18 PM PST 24
Peak memory 200900 kb
Host smart-023d206f-b084-4921-a48e-b83c7decac29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408708393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2408708393
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2997231090
Short name T620
Test name
Test status
Simulation time 126612451418 ps
CPU time 676.69 seconds
Started Mar 03 04:18:57 PM PST 24
Finished Mar 03 04:30:14 PM PST 24
Peak memory 201308 kb
Host smart-84867199-9280-481d-a9a3-4cbec23c7f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997231090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2997231090
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1770389527
Short name T685
Test name
Test status
Simulation time 27426175134 ps
CPU time 14.97 seconds
Started Mar 03 04:18:56 PM PST 24
Finished Mar 03 04:19:11 PM PST 24
Peak memory 200760 kb
Host smart-d53d545e-b731-4899-84a2-ce359d3ae92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770389527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1770389527
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3730007252
Short name T669
Test name
Test status
Simulation time 5014921603 ps
CPU time 3.45 seconds
Started Mar 03 04:18:56 PM PST 24
Finished Mar 03 04:19:00 PM PST 24
Peak memory 200768 kb
Host smart-1b2ec746-4d16-4e6c-97d1-1438fc5bf1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730007252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3730007252
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.778128103
Short name T740
Test name
Test status
Simulation time 5793803443 ps
CPU time 3.77 seconds
Started Mar 03 04:18:44 PM PST 24
Finished Mar 03 04:18:49 PM PST 24
Peak memory 200712 kb
Host smart-38b3b107-c8c2-4b64-a1c4-f2500dd47c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778128103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.778128103
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2864649861
Short name T293
Test name
Test status
Simulation time 289523199487 ps
CPU time 404.85 seconds
Started Mar 03 04:18:56 PM PST 24
Finished Mar 03 04:25:41 PM PST 24
Peak memory 201288 kb
Host smart-eeeae8c7-ed3f-475d-b953-cd870dd246ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864649861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2864649861
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2289345459
Short name T754
Test name
Test status
Simulation time 39108337337 ps
CPU time 89.59 seconds
Started Mar 03 04:18:57 PM PST 24
Finished Mar 03 04:20:27 PM PST 24
Peak memory 209716 kb
Host smart-9d6028c8-fd93-4183-ae36-475093666077
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289345459 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2289345459
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.527866190
Short name T360
Test name
Test status
Simulation time 505234013 ps
CPU time 0.95 seconds
Started Mar 03 04:19:08 PM PST 24
Finished Mar 03 04:19:09 PM PST 24
Peak memory 200700 kb
Host smart-fd4855a7-1600-4ae4-aecd-d99f7455ffcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527866190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.527866190
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.257141058
Short name T282
Test name
Test status
Simulation time 490750134004 ps
CPU time 604.93 seconds
Started Mar 03 04:19:03 PM PST 24
Finished Mar 03 04:29:08 PM PST 24
Peak memory 200960 kb
Host smart-644e318e-001b-4544-b06b-32b7bfa16dd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257141058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.257141058
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.960362309
Short name T270
Test name
Test status
Simulation time 333852410139 ps
CPU time 757.01 seconds
Started Mar 03 04:19:02 PM PST 24
Finished Mar 03 04:31:39 PM PST 24
Peak memory 200964 kb
Host smart-02949f88-83ab-451d-827a-6fe777c234c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960362309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.960362309
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2777985333
Short name T450
Test name
Test status
Simulation time 324424434860 ps
CPU time 800.3 seconds
Started Mar 03 04:18:57 PM PST 24
Finished Mar 03 04:32:17 PM PST 24
Peak memory 200896 kb
Host smart-ddcaf889-212d-4d1d-943b-f97e0799e8fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777985333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2777985333
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.989952742
Short name T675
Test name
Test status
Simulation time 165432144548 ps
CPU time 104.73 seconds
Started Mar 03 04:18:57 PM PST 24
Finished Mar 03 04:20:42 PM PST 24
Peak memory 200904 kb
Host smart-40d86996-50db-4527-83d6-269abec91618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989952742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.989952742
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1596639694
Short name T461
Test name
Test status
Simulation time 160487872756 ps
CPU time 164.94 seconds
Started Mar 03 04:18:58 PM PST 24
Finished Mar 03 04:21:43 PM PST 24
Peak memory 200944 kb
Host smart-9772b9df-1423-417b-8066-22a19e709568
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596639694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1596639694
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2205511096
Short name T303
Test name
Test status
Simulation time 162376382136 ps
CPU time 386.72 seconds
Started Mar 03 04:19:03 PM PST 24
Finished Mar 03 04:25:30 PM PST 24
Peak memory 200964 kb
Host smart-8f1146c2-e34a-430e-ab71-6987432e2ece
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205511096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2205511096
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.265646694
Short name T561
Test name
Test status
Simulation time 162346486074 ps
CPU time 311.26 seconds
Started Mar 03 04:19:02 PM PST 24
Finished Mar 03 04:24:13 PM PST 24
Peak memory 200896 kb
Host smart-358534d6-d1d5-46ab-b2eb-e3acc65392f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265646694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.265646694
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2928546517
Short name T24
Test name
Test status
Simulation time 58903229047 ps
CPU time 244.58 seconds
Started Mar 03 04:19:03 PM PST 24
Finished Mar 03 04:23:08 PM PST 24
Peak memory 201340 kb
Host smart-f974a244-c906-430a-bdda-5c70d6e2adf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928546517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2928546517
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3406767737
Short name T635
Test name
Test status
Simulation time 37346252147 ps
CPU time 87.29 seconds
Started Mar 03 04:19:02 PM PST 24
Finished Mar 03 04:20:29 PM PST 24
Peak memory 200752 kb
Host smart-6c15e1cf-4977-4941-b9d2-0605c656a6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406767737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3406767737
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.525189988
Short name T423
Test name
Test status
Simulation time 5354301611 ps
CPU time 5.58 seconds
Started Mar 03 04:19:03 PM PST 24
Finished Mar 03 04:19:09 PM PST 24
Peak memory 200772 kb
Host smart-c81adf20-4243-4c51-b7e4-7cd94afee644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525189988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.525189988
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3036040758
Short name T745
Test name
Test status
Simulation time 5751528627 ps
CPU time 14.21 seconds
Started Mar 03 04:18:56 PM PST 24
Finished Mar 03 04:19:11 PM PST 24
Peak memory 200724 kb
Host smart-ab654105-af9f-4f8b-9be7-ad0e57c16d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036040758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3036040758
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.279834416
Short name T331
Test name
Test status
Simulation time 323855659149 ps
CPU time 415.34 seconds
Started Mar 03 04:19:08 PM PST 24
Finished Mar 03 04:26:04 PM PST 24
Peak memory 200904 kb
Host smart-fce9222f-9ef2-44c0-af01-0eb1bc862320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279834416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
279834416
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1739699138
Short name T371
Test name
Test status
Simulation time 378201330 ps
CPU time 0.78 seconds
Started Mar 03 04:15:56 PM PST 24
Finished Mar 03 04:15:57 PM PST 24
Peak memory 200688 kb
Host smart-a8dbc77a-9429-415a-8303-1b79a4debbde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739699138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1739699138
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.4286002871
Short name T674
Test name
Test status
Simulation time 326720888315 ps
CPU time 196.86 seconds
Started Mar 03 04:15:45 PM PST 24
Finished Mar 03 04:19:02 PM PST 24
Peak memory 200944 kb
Host smart-cbdd8622-f527-4558-8f27-24db79d12f0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286002871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.4286002871
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1073027330
Short name T427
Test name
Test status
Simulation time 165903113432 ps
CPU time 404.54 seconds
Started Mar 03 04:15:39 PM PST 24
Finished Mar 03 04:22:24 PM PST 24
Peak memory 200880 kb
Host smart-37e626f7-a9e8-46e9-883f-b9cea678444c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073027330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1073027330
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2728328170
Short name T667
Test name
Test status
Simulation time 160990265894 ps
CPU time 27.79 seconds
Started Mar 03 04:15:33 PM PST 24
Finished Mar 03 04:16:01 PM PST 24
Peak memory 200824 kb
Host smart-d1cb1187-ed50-4e53-b7d9-ae264adc4f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728328170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2728328170
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3545589361
Short name T478
Test name
Test status
Simulation time 322933190756 ps
CPU time 745.62 seconds
Started Mar 03 04:15:33 PM PST 24
Finished Mar 03 04:27:59 PM PST 24
Peak memory 200892 kb
Host smart-fa9221a7-7377-4e5a-9dd5-262964457282
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545589361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3545589361
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2768831332
Short name T705
Test name
Test status
Simulation time 333889388785 ps
CPU time 733.91 seconds
Started Mar 03 04:15:38 PM PST 24
Finished Mar 03 04:27:52 PM PST 24
Peak memory 200904 kb
Host smart-965dfd0c-0169-45ea-9016-93cf42e773db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768831332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2768831332
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.929407865
Short name T400
Test name
Test status
Simulation time 495767475370 ps
CPU time 1071.88 seconds
Started Mar 03 04:15:45 PM PST 24
Finished Mar 03 04:33:37 PM PST 24
Peak memory 200904 kb
Host smart-544e667f-8af4-4d2b-bd12-1e5e3658c846
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929407865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.929407865
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1897234912
Short name T516
Test name
Test status
Simulation time 80448886304 ps
CPU time 471.08 seconds
Started Mar 03 04:15:53 PM PST 24
Finished Mar 03 04:23:44 PM PST 24
Peak memory 201392 kb
Host smart-8e37ec96-1bd4-4e57-bad8-bd258e454fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897234912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1897234912
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2802842687
Short name T26
Test name
Test status
Simulation time 47354713143 ps
CPU time 110.38 seconds
Started Mar 03 04:15:53 PM PST 24
Finished Mar 03 04:17:44 PM PST 24
Peak memory 200764 kb
Host smart-dc18d7fe-0fd2-44f1-a611-d6ad43791ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802842687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2802842687
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.4140199091
Short name T608
Test name
Test status
Simulation time 4049950027 ps
CPU time 10.48 seconds
Started Mar 03 04:15:51 PM PST 24
Finished Mar 03 04:16:02 PM PST 24
Peak memory 200736 kb
Host smart-04be555b-2c29-4944-9bca-912142072ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140199091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4140199091
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2831311963
Short name T50
Test name
Test status
Simulation time 4072912708 ps
CPU time 10.44 seconds
Started Mar 03 04:15:56 PM PST 24
Finished Mar 03 04:16:07 PM PST 24
Peak memory 216096 kb
Host smart-1c112dd5-702d-4cfc-b2b8-18bb7463808e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831311963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2831311963
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.647138032
Short name T680
Test name
Test status
Simulation time 5823404276 ps
CPU time 4.4 seconds
Started Mar 03 04:15:33 PM PST 24
Finished Mar 03 04:15:38 PM PST 24
Peak memory 200760 kb
Host smart-f1013ef3-8066-4aa0-bac7-5c88f4ecf357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647138032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.647138032
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2383408506
Short name T102
Test name
Test status
Simulation time 44459220959 ps
CPU time 101.27 seconds
Started Mar 03 04:15:52 PM PST 24
Finished Mar 03 04:17:34 PM PST 24
Peak memory 201088 kb
Host smart-82f72036-1e1f-458f-a498-5e408e79c9be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383408506 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2383408506
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2319538095
Short name T673
Test name
Test status
Simulation time 302619985 ps
CPU time 1.35 seconds
Started Mar 03 04:19:24 PM PST 24
Finished Mar 03 04:19:25 PM PST 24
Peak memory 200704 kb
Host smart-57ea382e-43c7-4bbe-ac0d-ce302b2a940e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319538095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2319538095
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1322252098
Short name T222
Test name
Test status
Simulation time 164004394130 ps
CPU time 342.8 seconds
Started Mar 03 04:19:13 PM PST 24
Finished Mar 03 04:24:56 PM PST 24
Peak memory 200844 kb
Host smart-16d533d9-cbe4-4032-b2f6-d8edc9a7dd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322252098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1322252098
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.697775950
Short name T172
Test name
Test status
Simulation time 495543552828 ps
CPU time 1164.66 seconds
Started Mar 03 04:19:08 PM PST 24
Finished Mar 03 04:38:32 PM PST 24
Peak memory 200912 kb
Host smart-33ea7a72-387e-40f5-9c34-76f27f8fd075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697775950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.697775950
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2501041046
Short name T594
Test name
Test status
Simulation time 167698492058 ps
CPU time 409.7 seconds
Started Mar 03 04:19:08 PM PST 24
Finished Mar 03 04:25:58 PM PST 24
Peak memory 200864 kb
Host smart-cabfd7ae-8024-47da-a92b-96c8ed2bbe1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501041046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2501041046
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3254024548
Short name T721
Test name
Test status
Simulation time 491756333587 ps
CPU time 346.28 seconds
Started Mar 03 04:19:08 PM PST 24
Finished Mar 03 04:24:54 PM PST 24
Peak memory 200836 kb
Host smart-3a04c731-822a-413e-8d3b-5ebefa1cad78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254024548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3254024548
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2418010201
Short name T99
Test name
Test status
Simulation time 492401729683 ps
CPU time 360.23 seconds
Started Mar 03 04:19:06 PM PST 24
Finished Mar 03 04:25:06 PM PST 24
Peak memory 200956 kb
Host smart-2653af43-e113-4323-9de2-697bbef595c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418010201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2418010201
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1560252980
Short name T198
Test name
Test status
Simulation time 485705920900 ps
CPU time 183.14 seconds
Started Mar 03 04:19:14 PM PST 24
Finished Mar 03 04:22:17 PM PST 24
Peak memory 200908 kb
Host smart-9a4fea72-2761-4b6e-a2da-b7a81a6f0fa0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560252980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1560252980
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1861450621
Short name T413
Test name
Test status
Simulation time 316699246865 ps
CPU time 182.79 seconds
Started Mar 03 04:19:12 PM PST 24
Finished Mar 03 04:22:15 PM PST 24
Peak memory 200892 kb
Host smart-96424e1d-f479-460f-9990-28eb84126253
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861450621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1861450621
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.643250371
Short name T772
Test name
Test status
Simulation time 74589867726 ps
CPU time 327.04 seconds
Started Mar 03 04:19:14 PM PST 24
Finished Mar 03 04:24:42 PM PST 24
Peak memory 201284 kb
Host smart-b8cfe034-3839-45ce-948e-825911ccfe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643250371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.643250371
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1381117103
Short name T165
Test name
Test status
Simulation time 26667487974 ps
CPU time 5.1 seconds
Started Mar 03 04:19:12 PM PST 24
Finished Mar 03 04:19:18 PM PST 24
Peak memory 200752 kb
Host smart-bc964b9b-e2b4-48c2-b382-382dab6e95db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381117103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1381117103
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3963312372
Short name T482
Test name
Test status
Simulation time 3312102265 ps
CPU time 1.13 seconds
Started Mar 03 04:19:15 PM PST 24
Finished Mar 03 04:19:16 PM PST 24
Peak memory 200660 kb
Host smart-93f9723d-bd60-4dd9-86ea-535c181a749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963312372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3963312372
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.4109179879
Short name T452
Test name
Test status
Simulation time 5715740181 ps
CPU time 8.45 seconds
Started Mar 03 04:19:10 PM PST 24
Finished Mar 03 04:19:18 PM PST 24
Peak memory 200700 kb
Host smart-d101fbe5-95d7-420f-b05f-0e8f0412d94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109179879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.4109179879
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.504354877
Short name T466
Test name
Test status
Simulation time 4096460583 ps
CPU time 9.77 seconds
Started Mar 03 04:19:13 PM PST 24
Finished Mar 03 04:19:23 PM PST 24
Peak memory 200764 kb
Host smart-d12a034b-6f22-47c8-b6b4-3b456ff330f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504354877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
504354877
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2276803602
Short name T176
Test name
Test status
Simulation time 399124322670 ps
CPU time 91.3 seconds
Started Mar 03 04:19:13 PM PST 24
Finished Mar 03 04:20:45 PM PST 24
Peak memory 209652 kb
Host smart-e89b57d7-c947-492e-a73f-d8d0ec42e7b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276803602 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2276803602
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.810216126
Short name T782
Test name
Test status
Simulation time 458400249 ps
CPU time 0.79 seconds
Started Mar 03 04:19:26 PM PST 24
Finished Mar 03 04:19:27 PM PST 24
Peak memory 200692 kb
Host smart-f7a690ae-6b92-430f-8395-7fee3195c316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810216126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.810216126
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.4153550611
Short name T550
Test name
Test status
Simulation time 323341133080 ps
CPU time 192.87 seconds
Started Mar 03 04:19:21 PM PST 24
Finished Mar 03 04:22:34 PM PST 24
Peak memory 200996 kb
Host smart-9ae338e3-9baa-41e2-b9fe-0268b785082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153550611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.4153550611
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1500453637
Short name T648
Test name
Test status
Simulation time 168280813064 ps
CPU time 116.54 seconds
Started Mar 03 04:19:22 PM PST 24
Finished Mar 03 04:21:19 PM PST 24
Peak memory 200904 kb
Host smart-9e4d7084-f913-433e-b35f-f08d5f4137af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500453637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1500453637
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3312028196
Short name T291
Test name
Test status
Simulation time 327449837480 ps
CPU time 192.26 seconds
Started Mar 03 04:19:22 PM PST 24
Finished Mar 03 04:22:34 PM PST 24
Peak memory 200920 kb
Host smart-2ba16762-7592-4dc6-aa2e-9924e582e52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312028196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3312028196
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2606242103
Short name T525
Test name
Test status
Simulation time 329176866343 ps
CPU time 772.02 seconds
Started Mar 03 04:19:21 PM PST 24
Finished Mar 03 04:32:13 PM PST 24
Peak memory 200896 kb
Host smart-8af9d829-11cf-4e52-9da4-b31b89d0aaf6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606242103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2606242103
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.499516175
Short name T462
Test name
Test status
Simulation time 162362112184 ps
CPU time 51.95 seconds
Started Mar 03 04:19:21 PM PST 24
Finished Mar 03 04:20:13 PM PST 24
Peak memory 200884 kb
Host smart-48e4349a-5c46-41fa-be17-ac2d7fdab84d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499516175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.499516175
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2261247192
Short name T742
Test name
Test status
Simulation time 33291950704 ps
CPU time 79.41 seconds
Started Mar 03 04:19:26 PM PST 24
Finished Mar 03 04:20:46 PM PST 24
Peak memory 200720 kb
Host smart-19c3fb8e-ea4c-4cb2-af97-e88e19b96b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261247192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2261247192
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1927462513
Short name T499
Test name
Test status
Simulation time 3539677734 ps
CPU time 1.8 seconds
Started Mar 03 04:19:27 PM PST 24
Finished Mar 03 04:19:29 PM PST 24
Peak memory 200768 kb
Host smart-032e8783-f2ef-470d-a9bb-4f36de006b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927462513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1927462513
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.3153034478
Short name T712
Test name
Test status
Simulation time 5538729145 ps
CPU time 7.01 seconds
Started Mar 03 04:19:23 PM PST 24
Finished Mar 03 04:19:30 PM PST 24
Peak memory 200712 kb
Host smart-87d4f449-913d-4000-8036-65492b8b66c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153034478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.3153034478
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.528401507
Short name T565
Test name
Test status
Simulation time 6761986467 ps
CPU time 4.71 seconds
Started Mar 03 04:19:25 PM PST 24
Finished Mar 03 04:19:30 PM PST 24
Peak memory 200740 kb
Host smart-556527c9-2189-4f05-9866-962b68c92615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528401507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
528401507
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1577384464
Short name T483
Test name
Test status
Simulation time 531579140 ps
CPU time 1.71 seconds
Started Mar 03 04:19:34 PM PST 24
Finished Mar 03 04:19:36 PM PST 24
Peak memory 200684 kb
Host smart-3243707f-4175-407a-b487-304d42698584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577384464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1577384464
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.399916881
Short name T286
Test name
Test status
Simulation time 163358013984 ps
CPU time 97.71 seconds
Started Mar 03 04:19:25 PM PST 24
Finished Mar 03 04:21:03 PM PST 24
Peak memory 200852 kb
Host smart-83d90328-1853-4240-ae67-831ed2aac335
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399916881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.399916881
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.555161638
Short name T643
Test name
Test status
Simulation time 329901216904 ps
CPU time 382.65 seconds
Started Mar 03 04:19:26 PM PST 24
Finished Mar 03 04:25:49 PM PST 24
Peak memory 200956 kb
Host smart-ba1dde70-51a7-4314-bb06-06d8a48e21c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555161638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.555161638
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1349676714
Short name T83
Test name
Test status
Simulation time 319292750603 ps
CPU time 712.87 seconds
Started Mar 03 04:19:28 PM PST 24
Finished Mar 03 04:31:21 PM PST 24
Peak memory 200960 kb
Host smart-b47955f5-14da-4380-96ae-63e071531d5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349676714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1349676714
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.579486553
Short name T628
Test name
Test status
Simulation time 476801245940 ps
CPU time 287.08 seconds
Started Mar 03 04:19:26 PM PST 24
Finished Mar 03 04:24:13 PM PST 24
Peak memory 200908 kb
Host smart-33957711-5bce-43b5-b9e0-6619b6a6a0c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=579486553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.579486553
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.791157406
Short name T243
Test name
Test status
Simulation time 327612412234 ps
CPU time 219.81 seconds
Started Mar 03 04:19:27 PM PST 24
Finished Mar 03 04:23:07 PM PST 24
Peak memory 200972 kb
Host smart-dfeffd93-20fd-470a-98ec-eb1156860c97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791157406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.791157406
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2044715561
Short name T624
Test name
Test status
Simulation time 322704500622 ps
CPU time 125.66 seconds
Started Mar 03 04:19:26 PM PST 24
Finished Mar 03 04:21:31 PM PST 24
Peak memory 200904 kb
Host smart-d5ae04ba-5eb4-42c4-86da-dfc265156045
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044715561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2044715561
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2845685781
Short name T211
Test name
Test status
Simulation time 67044943085 ps
CPU time 385.36 seconds
Started Mar 03 04:19:31 PM PST 24
Finished Mar 03 04:25:57 PM PST 24
Peak memory 201284 kb
Host smart-eea1a541-e2e3-42b4-a996-9c44057784f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845685781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2845685781
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3117286351
Short name T562
Test name
Test status
Simulation time 42994042718 ps
CPU time 54.87 seconds
Started Mar 03 04:19:26 PM PST 24
Finished Mar 03 04:20:21 PM PST 24
Peak memory 200964 kb
Host smart-fe199bcc-c43b-45ad-adab-f6a08c560ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117286351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3117286351
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1173133938
Short name T32
Test name
Test status
Simulation time 3871387760 ps
CPU time 3.28 seconds
Started Mar 03 04:19:27 PM PST 24
Finished Mar 03 04:19:30 PM PST 24
Peak memory 200752 kb
Host smart-c5c5d8d5-b17f-4ec2-9f7a-dee416fe9a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173133938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1173133938
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1810099288
Short name T143
Test name
Test status
Simulation time 6147987213 ps
CPU time 4.51 seconds
Started Mar 03 04:19:28 PM PST 24
Finished Mar 03 04:19:32 PM PST 24
Peak memory 200736 kb
Host smart-1268c566-6f2f-40f9-80fd-8fbcf8818224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810099288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1810099288
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.4029132529
Short name T321
Test name
Test status
Simulation time 190250430846 ps
CPU time 208.24 seconds
Started Mar 03 04:19:32 PM PST 24
Finished Mar 03 04:23:01 PM PST 24
Peak memory 200960 kb
Host smart-ae2b6b46-3d65-475b-b312-861846dd03bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029132529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.4029132529
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.537874048
Short name T767
Test name
Test status
Simulation time 268687148736 ps
CPU time 165.06 seconds
Started Mar 03 04:19:34 PM PST 24
Finished Mar 03 04:22:19 PM PST 24
Peak memory 201060 kb
Host smart-897d36a6-05f8-4b8a-b9ae-d17977ec84aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537874048 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.537874048
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.4073561676
Short name T357
Test name
Test status
Simulation time 515242976 ps
CPU time 0.7 seconds
Started Mar 03 04:19:45 PM PST 24
Finished Mar 03 04:19:47 PM PST 24
Peak memory 200676 kb
Host smart-fcfcf837-8593-4d06-bdf4-2f8bab9fdf3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073561676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.4073561676
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1323301457
Short name T464
Test name
Test status
Simulation time 497654145873 ps
CPU time 390 seconds
Started Mar 03 04:19:45 PM PST 24
Finished Mar 03 04:26:16 PM PST 24
Peak memory 200956 kb
Host smart-0e61cc1e-f4d5-438e-86c7-adda356fc707
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323301457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1323301457
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1555503960
Short name T535
Test name
Test status
Simulation time 327349072379 ps
CPU time 736.25 seconds
Started Mar 03 04:19:34 PM PST 24
Finished Mar 03 04:31:50 PM PST 24
Peak memory 200960 kb
Host smart-4dcefeae-6131-4ece-a48c-b2fd51a20730
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555503960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1555503960
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1679276812
Short name T563
Test name
Test status
Simulation time 320155609639 ps
CPU time 194.68 seconds
Started Mar 03 04:19:45 PM PST 24
Finished Mar 03 04:23:00 PM PST 24
Peak memory 200908 kb
Host smart-0f9d9762-d698-4ccb-9c3b-30ebd3cdccbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679276812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1679276812
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1868459416
Short name T519
Test name
Test status
Simulation time 325353377949 ps
CPU time 175.77 seconds
Started Mar 03 04:19:45 PM PST 24
Finished Mar 03 04:22:42 PM PST 24
Peak memory 200900 kb
Host smart-2a0a3d75-594d-4284-aa5d-5b4c23c3f240
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868459416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1868459416
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1516174970
Short name T576
Test name
Test status
Simulation time 127773102289 ps
CPU time 442.99 seconds
Started Mar 03 04:19:38 PM PST 24
Finished Mar 03 04:27:02 PM PST 24
Peak memory 201396 kb
Host smart-2c519d1e-c0f7-44d7-b316-a48451618737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516174970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1516174970
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1510577797
Short name T388
Test name
Test status
Simulation time 24660890356 ps
CPU time 5.08 seconds
Started Mar 03 04:19:38 PM PST 24
Finished Mar 03 04:19:45 PM PST 24
Peak memory 200768 kb
Host smart-0b436e5a-337d-468e-a36c-ec67fe3dbeed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510577797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1510577797
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1589046820
Short name T109
Test name
Test status
Simulation time 4082493839 ps
CPU time 9.43 seconds
Started Mar 03 04:19:38 PM PST 24
Finished Mar 03 04:19:48 PM PST 24
Peak memory 200716 kb
Host smart-e8acc627-5072-4ef2-9099-7c1ae6c2c7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589046820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1589046820
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1407471969
Short name T652
Test name
Test status
Simulation time 5735069969 ps
CPU time 4.16 seconds
Started Mar 03 04:19:34 PM PST 24
Finished Mar 03 04:19:38 PM PST 24
Peak memory 200764 kb
Host smart-3c858d9d-e68e-4420-9157-9f8d0d2b821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407471969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1407471969
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1783435326
Short name T324
Test name
Test status
Simulation time 371580938650 ps
CPU time 725.21 seconds
Started Mar 03 04:19:38 PM PST 24
Finished Mar 03 04:31:44 PM PST 24
Peak memory 209540 kb
Host smart-4c912f43-4cc7-45f6-bc0f-fb9a7432879e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783435326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1783435326
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1188271644
Short name T558
Test name
Test status
Simulation time 268939399497 ps
CPU time 533.11 seconds
Started Mar 03 04:19:36 PM PST 24
Finished Mar 03 04:28:30 PM PST 24
Peak memory 209656 kb
Host smart-46f810c2-473c-48b5-b30b-3e21c9ac6549
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188271644 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1188271644
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.2632792314
Short name T397
Test name
Test status
Simulation time 459389146 ps
CPU time 0.93 seconds
Started Mar 03 04:19:49 PM PST 24
Finished Mar 03 04:19:50 PM PST 24
Peak memory 200620 kb
Host smart-701186b1-0b47-4364-879a-0fc1aab24dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632792314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.2632792314
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.915854834
Short name T763
Test name
Test status
Simulation time 498554255042 ps
CPU time 276.02 seconds
Started Mar 03 04:19:51 PM PST 24
Finished Mar 03 04:24:27 PM PST 24
Peak memory 200888 kb
Host smart-6315e5c2-08ce-49d3-8619-18a40c57f1f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915854834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.915854834
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3166369247
Short name T538
Test name
Test status
Simulation time 482412533816 ps
CPU time 120.19 seconds
Started Mar 03 04:19:51 PM PST 24
Finished Mar 03 04:21:51 PM PST 24
Peak memory 201176 kb
Host smart-82b9a069-4909-4217-9817-704542adc6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166369247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3166369247
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3841277498
Short name T146
Test name
Test status
Simulation time 484366122858 ps
CPU time 257.57 seconds
Started Mar 03 04:19:45 PM PST 24
Finished Mar 03 04:24:03 PM PST 24
Peak memory 200972 kb
Host smart-c4008f86-7696-4d1a-9297-e778310ec7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841277498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3841277498
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.795039924
Short name T788
Test name
Test status
Simulation time 494653322443 ps
CPU time 1031.33 seconds
Started Mar 03 04:19:45 PM PST 24
Finished Mar 03 04:36:56 PM PST 24
Peak memory 200868 kb
Host smart-ab2edb11-2848-4656-a7b8-4f076d3bce57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=795039924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.795039924
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2872452027
Short name T223
Test name
Test status
Simulation time 325431679709 ps
CPU time 363.22 seconds
Started Mar 03 04:19:44 PM PST 24
Finished Mar 03 04:25:48 PM PST 24
Peak memory 200920 kb
Host smart-a14e019b-4c09-4759-9fce-54623760d24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872452027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2872452027
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.630300976
Short name T422
Test name
Test status
Simulation time 164171493988 ps
CPU time 100.02 seconds
Started Mar 03 04:19:45 PM PST 24
Finished Mar 03 04:21:26 PM PST 24
Peak memory 200896 kb
Host smart-b2d1eb81-641d-418a-956e-7a25c466d713
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=630300976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.630300976
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1609394993
Short name T260
Test name
Test status
Simulation time 184525758139 ps
CPU time 232.11 seconds
Started Mar 03 04:19:44 PM PST 24
Finished Mar 03 04:23:37 PM PST 24
Peak memory 200836 kb
Host smart-9b36f72f-921f-4862-8c4c-109e754cfe49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609394993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1609394993
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.744625368
Short name T493
Test name
Test status
Simulation time 168393258079 ps
CPU time 38.1 seconds
Started Mar 03 04:19:45 PM PST 24
Finished Mar 03 04:20:24 PM PST 24
Peak memory 200908 kb
Host smart-a2888702-665f-45a1-a059-e6cf0de23c4b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744625368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.744625368
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1286865909
Short name T601
Test name
Test status
Simulation time 86518780748 ps
CPU time 454.08 seconds
Started Mar 03 04:19:49 PM PST 24
Finished Mar 03 04:27:23 PM PST 24
Peak memory 201332 kb
Host smart-bab5db14-3bba-4238-b7f3-29ad260bad5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286865909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1286865909
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1833723188
Short name T517
Test name
Test status
Simulation time 29245139577 ps
CPU time 21.71 seconds
Started Mar 03 04:19:51 PM PST 24
Finished Mar 03 04:20:13 PM PST 24
Peak memory 200960 kb
Host smart-beaa4098-9fda-4dc2-940d-a09c83a721f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833723188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1833723188
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1138164226
Short name T640
Test name
Test status
Simulation time 3867121308 ps
CPU time 5.08 seconds
Started Mar 03 04:19:51 PM PST 24
Finished Mar 03 04:19:56 PM PST 24
Peak memory 200660 kb
Host smart-d1233474-2404-4603-8201-a2cc4b6ec819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138164226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1138164226
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3105068203
Short name T584
Test name
Test status
Simulation time 5647557227 ps
CPU time 3.74 seconds
Started Mar 03 04:19:45 PM PST 24
Finished Mar 03 04:19:49 PM PST 24
Peak memory 200760 kb
Host smart-97039c42-42cb-4dc1-a8f8-3ffa265f7f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105068203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3105068203
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.172226697
Short name T208
Test name
Test status
Simulation time 76684262119 ps
CPU time 83.71 seconds
Started Mar 03 04:19:48 PM PST 24
Finished Mar 03 04:21:12 PM PST 24
Peak memory 209724 kb
Host smart-8d5cd467-555f-475d-a45a-d61a71300f6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172226697 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.172226697
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3810428634
Short name T443
Test name
Test status
Simulation time 515449782 ps
CPU time 1.56 seconds
Started Mar 03 04:20:01 PM PST 24
Finished Mar 03 04:20:03 PM PST 24
Peak memory 200688 kb
Host smart-ef541249-d08b-4a17-83eb-3b1ff6a300eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810428634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3810428634
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2092826782
Short name T301
Test name
Test status
Simulation time 162128325065 ps
CPU time 95.22 seconds
Started Mar 03 04:19:55 PM PST 24
Finished Mar 03 04:21:30 PM PST 24
Peak memory 200952 kb
Host smart-dc986e57-bfd6-4657-87b5-551906236571
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092826782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2092826782
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3325526018
Short name T110
Test name
Test status
Simulation time 164337867551 ps
CPU time 59.12 seconds
Started Mar 03 04:19:55 PM PST 24
Finished Mar 03 04:20:54 PM PST 24
Peak memory 200880 kb
Host smart-01f5eca1-42e8-43e3-8baa-7b3423b32d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325526018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3325526018
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3691483979
Short name T441
Test name
Test status
Simulation time 494734102377 ps
CPU time 1129.43 seconds
Started Mar 03 04:19:57 PM PST 24
Finished Mar 03 04:38:46 PM PST 24
Peak memory 200956 kb
Host smart-a3eda0de-1179-4d48-b511-eab8ce8fa3ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691483979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3691483979
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.594392926
Short name T506
Test name
Test status
Simulation time 169327164293 ps
CPU time 176.41 seconds
Started Mar 03 04:19:49 PM PST 24
Finished Mar 03 04:22:46 PM PST 24
Peak memory 200964 kb
Host smart-712e5ec2-3cc7-49d8-8b59-9e41623b9b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594392926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.594392926
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2165588382
Short name T521
Test name
Test status
Simulation time 323258227579 ps
CPU time 694.32 seconds
Started Mar 03 04:19:56 PM PST 24
Finished Mar 03 04:31:31 PM PST 24
Peak memory 200840 kb
Host smart-714dd84c-e779-409e-b10c-ba4a38c5493c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165588382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2165588382
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2638538022
Short name T621
Test name
Test status
Simulation time 341390216374 ps
CPU time 395.67 seconds
Started Mar 03 04:19:56 PM PST 24
Finished Mar 03 04:26:32 PM PST 24
Peak memory 200900 kb
Host smart-40a20a1a-277a-4f9d-9cca-0c9aef759e06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638538022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2638538022
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1522283601
Short name T783
Test name
Test status
Simulation time 325671658901 ps
CPU time 718.42 seconds
Started Mar 03 04:19:58 PM PST 24
Finished Mar 03 04:31:57 PM PST 24
Peak memory 200792 kb
Host smart-804427de-459a-4ed4-b2b6-a8fa9b1974b0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522283601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1522283601
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2765692382
Short name T341
Test name
Test status
Simulation time 148653131928 ps
CPU time 599.67 seconds
Started Mar 03 04:19:58 PM PST 24
Finished Mar 03 04:29:58 PM PST 24
Peak memory 201396 kb
Host smart-c264fcd2-5d5b-474b-9b40-564591775812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765692382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2765692382
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2976511378
Short name T647
Test name
Test status
Simulation time 23769278288 ps
CPU time 50.78 seconds
Started Mar 03 04:19:59 PM PST 24
Finished Mar 03 04:20:49 PM PST 24
Peak memory 200756 kb
Host smart-c507880b-eba4-458b-9031-dbd7a2b592db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976511378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2976511378
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1407432813
Short name T448
Test name
Test status
Simulation time 5176078799 ps
CPU time 3.68 seconds
Started Mar 03 04:19:56 PM PST 24
Finished Mar 03 04:19:59 PM PST 24
Peak memory 200756 kb
Host smart-93e9c851-4a82-4b2f-bbfa-80f20febd305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407432813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1407432813
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2104261412
Short name T778
Test name
Test status
Simulation time 5707205464 ps
CPU time 7.28 seconds
Started Mar 03 04:19:50 PM PST 24
Finished Mar 03 04:19:57 PM PST 24
Peak memory 200724 kb
Host smart-64eba623-24bc-4a22-a337-5223e31a57e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104261412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2104261412
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.599988639
Short name T744
Test name
Test status
Simulation time 40616041291 ps
CPU time 37.29 seconds
Started Mar 03 04:20:02 PM PST 24
Finished Mar 03 04:20:39 PM PST 24
Peak memory 200756 kb
Host smart-434c353c-18c1-4474-8751-b56a9022e8ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599988639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
599988639
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3542314534
Short name T692
Test name
Test status
Simulation time 281234233125 ps
CPU time 174.16 seconds
Started Mar 03 04:20:05 PM PST 24
Finished Mar 03 04:23:01 PM PST 24
Peak memory 209672 kb
Host smart-dde9466c-b8bb-4192-b167-52979e96268f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542314534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3542314534
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1940356505
Short name T511
Test name
Test status
Simulation time 389340293 ps
CPU time 1.09 seconds
Started Mar 03 04:20:06 PM PST 24
Finished Mar 03 04:20:10 PM PST 24
Peak memory 200664 kb
Host smart-7bda3679-120c-4693-9ae3-28ac69a5bd29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940356505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1940356505
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3191135557
Short name T196
Test name
Test status
Simulation time 334907758160 ps
CPU time 164.33 seconds
Started Mar 03 04:20:14 PM PST 24
Finished Mar 03 04:22:58 PM PST 24
Peak memory 200868 kb
Host smart-7337a06c-4316-4c80-96cb-41f1482918c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191135557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3191135557
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3267886631
Short name T663
Test name
Test status
Simulation time 169726665374 ps
CPU time 394.93 seconds
Started Mar 03 04:20:07 PM PST 24
Finished Mar 03 04:26:43 PM PST 24
Peak memory 200972 kb
Host smart-b69f5fdb-cc7e-4d3d-9418-3e9f48674ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267886631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3267886631
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3554816290
Short name T278
Test name
Test status
Simulation time 330933757021 ps
CPU time 211.98 seconds
Started Mar 03 04:20:01 PM PST 24
Finished Mar 03 04:23:33 PM PST 24
Peak memory 200916 kb
Host smart-4640bd0f-2543-4bed-887a-610c4cd0b312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554816290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3554816290
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2826454750
Short name T497
Test name
Test status
Simulation time 160499466063 ps
CPU time 377.53 seconds
Started Mar 03 04:20:01 PM PST 24
Finished Mar 03 04:26:18 PM PST 24
Peak memory 200912 kb
Host smart-c7a3f654-94a8-4365-9b48-7ee2c33e4483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826454750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2826454750
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2711703553
Short name T191
Test name
Test status
Simulation time 163340926344 ps
CPU time 85.48 seconds
Started Mar 03 04:20:05 PM PST 24
Finished Mar 03 04:21:31 PM PST 24
Peak memory 200908 kb
Host smart-723c5373-9155-4420-9c7e-feb31ccd5d76
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711703553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2711703553
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1748988702
Short name T749
Test name
Test status
Simulation time 328809053157 ps
CPU time 765.95 seconds
Started Mar 03 04:20:01 PM PST 24
Finished Mar 03 04:32:47 PM PST 24
Peak memory 200912 kb
Host smart-114b5c2f-f786-4e6b-a290-053161c4b6e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748988702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1748988702
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2814672161
Short name T532
Test name
Test status
Simulation time 163497033572 ps
CPU time 50.33 seconds
Started Mar 03 04:20:01 PM PST 24
Finished Mar 03 04:20:51 PM PST 24
Peak memory 200900 kb
Host smart-703411aa-2578-4cde-9253-ca5d8d41f012
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814672161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2814672161
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2069443283
Short name T477
Test name
Test status
Simulation time 130747229657 ps
CPU time 707.69 seconds
Started Mar 03 04:20:07 PM PST 24
Finished Mar 03 04:31:56 PM PST 24
Peak memory 201280 kb
Host smart-8f1a9bca-d8d8-45ef-9783-7546d346f7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069443283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2069443283
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2299960633
Short name T650
Test name
Test status
Simulation time 42385740371 ps
CPU time 87.27 seconds
Started Mar 03 04:20:07 PM PST 24
Finished Mar 03 04:21:35 PM PST 24
Peak memory 200752 kb
Host smart-8766c814-9d89-49e4-966a-a50c1fedadfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299960633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2299960633
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.545532577
Short name T444
Test name
Test status
Simulation time 3794223040 ps
CPU time 2.79 seconds
Started Mar 03 04:20:07 PM PST 24
Finished Mar 03 04:20:11 PM PST 24
Peak memory 200772 kb
Host smart-869551e2-8e58-4008-bc69-6a8b1b7a041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545532577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.545532577
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1717244675
Short name T706
Test name
Test status
Simulation time 5788201387 ps
CPU time 7.39 seconds
Started Mar 03 04:20:05 PM PST 24
Finished Mar 03 04:20:14 PM PST 24
Peak memory 200768 kb
Host smart-0bbab308-f34d-4e86-a24f-5e8fb57548f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717244675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1717244675
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3857644843
Short name T233
Test name
Test status
Simulation time 579692285427 ps
CPU time 581.32 seconds
Started Mar 03 04:20:08 PM PST 24
Finished Mar 03 04:29:50 PM PST 24
Peak memory 209540 kb
Host smart-847c945b-77c0-45b9-8bf1-1677fc42551a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857644843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3857644843
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3442902268
Short name T81
Test name
Test status
Simulation time 203763437586 ps
CPU time 110.92 seconds
Started Mar 03 04:20:08 PM PST 24
Finished Mar 03 04:21:59 PM PST 24
Peak memory 217240 kb
Host smart-c274b982-b0b8-40c0-9899-d7931a650efd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442902268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3442902268
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3032766741
Short name T362
Test name
Test status
Simulation time 409393741 ps
CPU time 0.95 seconds
Started Mar 03 04:20:12 PM PST 24
Finished Mar 03 04:20:13 PM PST 24
Peak memory 200672 kb
Host smart-75f11093-6bb8-4600-9272-a6acb56ffb33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032766741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3032766741
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2722785040
Short name T595
Test name
Test status
Simulation time 327850817794 ps
CPU time 729.24 seconds
Started Mar 03 04:20:21 PM PST 24
Finished Mar 03 04:32:30 PM PST 24
Peak memory 200884 kb
Host smart-0778afa2-f9a2-4241-bcb4-731f72213c50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722785040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2722785040
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3342740689
Short name T570
Test name
Test status
Simulation time 168471039497 ps
CPU time 371.25 seconds
Started Mar 03 04:20:13 PM PST 24
Finished Mar 03 04:26:25 PM PST 24
Peak memory 200968 kb
Host smart-374219ca-491e-4a0d-a68e-1df24df79da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342740689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3342740689
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3143482239
Short name T53
Test name
Test status
Simulation time 492620020075 ps
CPU time 561.79 seconds
Started Mar 03 04:20:21 PM PST 24
Finished Mar 03 04:29:43 PM PST 24
Peak memory 200960 kb
Host smart-eefa3bd7-fb63-4493-9bb2-d56e191f5213
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143482239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3143482239
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1347634601
Short name T609
Test name
Test status
Simulation time 489413065385 ps
CPU time 1145.39 seconds
Started Mar 03 04:20:13 PM PST 24
Finished Mar 03 04:39:19 PM PST 24
Peak memory 200904 kb
Host smart-753c260f-9e89-4e7b-8cc6-fbbc96e1b563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347634601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1347634601
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4086007780
Short name T527
Test name
Test status
Simulation time 162033187999 ps
CPU time 255.17 seconds
Started Mar 03 04:20:13 PM PST 24
Finished Mar 03 04:24:29 PM PST 24
Peak memory 200896 kb
Host smart-efb634d3-98d4-4128-80c2-90c738a19352
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086007780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4086007780
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2066188838
Short name T761
Test name
Test status
Simulation time 162141174021 ps
CPU time 114.93 seconds
Started Mar 03 04:20:13 PM PST 24
Finished Mar 03 04:22:08 PM PST 24
Peak memory 200892 kb
Host smart-00327d9e-1f96-4fbd-845a-e54e0b41e0fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066188838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2066188838
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1424753350
Short name T393
Test name
Test status
Simulation time 493910434972 ps
CPU time 595.49 seconds
Started Mar 03 04:20:21 PM PST 24
Finished Mar 03 04:30:16 PM PST 24
Peak memory 200904 kb
Host smart-fedd13e6-83a5-4d42-8e01-aee4763aca74
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424753350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1424753350
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1811671035
Short name T33
Test name
Test status
Simulation time 87785185831 ps
CPU time 313.33 seconds
Started Mar 03 04:20:13 PM PST 24
Finished Mar 03 04:25:27 PM PST 24
Peak memory 201340 kb
Host smart-049376cc-f25b-449f-b041-eb84c47ee774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811671035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1811671035
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2059436646
Short name T458
Test name
Test status
Simulation time 45754806065 ps
CPU time 9.39 seconds
Started Mar 03 04:20:20 PM PST 24
Finished Mar 03 04:20:30 PM PST 24
Peak memory 200756 kb
Host smart-eb4c696f-296f-4750-b082-bac653e8be55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059436646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2059436646
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1750030463
Short name T704
Test name
Test status
Simulation time 4151669683 ps
CPU time 3.12 seconds
Started Mar 03 04:20:20 PM PST 24
Finished Mar 03 04:20:23 PM PST 24
Peak memory 200768 kb
Host smart-a025f9ab-5add-42fc-9695-0d4d859e7eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750030463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1750030463
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2208393410
Short name T359
Test name
Test status
Simulation time 5807824502 ps
CPU time 6.46 seconds
Started Mar 03 04:20:07 PM PST 24
Finished Mar 03 04:20:14 PM PST 24
Peak memory 200756 kb
Host smart-02ae4b0f-99a4-46c6-b46a-af2197c5ced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208393410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2208393410
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.120597207
Short name T164
Test name
Test status
Simulation time 42114757577 ps
CPU time 128.85 seconds
Started Mar 03 04:20:13 PM PST 24
Finished Mar 03 04:22:22 PM PST 24
Peak memory 209652 kb
Host smart-f97e3ac9-ec75-41b8-881d-c9b40814ab26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120597207 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.120597207
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.2647897318
Short name T637
Test name
Test status
Simulation time 526473860 ps
CPU time 1.26 seconds
Started Mar 03 04:20:26 PM PST 24
Finished Mar 03 04:20:27 PM PST 24
Peak memory 200708 kb
Host smart-2af76642-0796-4e0e-a701-f4105cc7ceb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647897318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.2647897318
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3944252110
Short name T770
Test name
Test status
Simulation time 497960527285 ps
CPU time 291.57 seconds
Started Mar 03 04:20:18 PM PST 24
Finished Mar 03 04:25:10 PM PST 24
Peak memory 200884 kb
Host smart-fb19e57a-4240-4255-b7c2-5134b45928ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944252110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3944252110
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1893726791
Short name T197
Test name
Test status
Simulation time 493788971652 ps
CPU time 310.72 seconds
Started Mar 03 04:20:18 PM PST 24
Finished Mar 03 04:25:29 PM PST 24
Peak memory 200908 kb
Host smart-b6c7df9c-af4f-4c3c-a196-64fe16c67242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893726791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1893726791
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1495680534
Short name T661
Test name
Test status
Simulation time 490462740497 ps
CPU time 655.57 seconds
Started Mar 03 04:20:19 PM PST 24
Finished Mar 03 04:31:14 PM PST 24
Peak memory 200892 kb
Host smart-6b471587-74da-4639-b27b-3e2aa3a2d20c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495680534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1495680534
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.951272958
Short name T180
Test name
Test status
Simulation time 326301430451 ps
CPU time 106.38 seconds
Started Mar 03 04:20:20 PM PST 24
Finished Mar 03 04:22:06 PM PST 24
Peak memory 200840 kb
Host smart-b0dc45af-63e2-4d9b-a814-ebf8edb53a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951272958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.951272958
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3188780148
Short name T630
Test name
Test status
Simulation time 326781946252 ps
CPU time 233.33 seconds
Started Mar 03 04:20:18 PM PST 24
Finished Mar 03 04:24:11 PM PST 24
Peak memory 200900 kb
Host smart-63347582-45a9-4b87-b31a-7f20b355502a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188780148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3188780148
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1088657571
Short name T717
Test name
Test status
Simulation time 324677987262 ps
CPU time 143.46 seconds
Started Mar 03 04:20:18 PM PST 24
Finished Mar 03 04:22:42 PM PST 24
Peak memory 200832 kb
Host smart-0b673cde-4f35-4593-bc7a-7169fcb5e897
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088657571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1088657571
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.172674876
Short name T599
Test name
Test status
Simulation time 499491041499 ps
CPU time 82.42 seconds
Started Mar 03 04:20:19 PM PST 24
Finished Mar 03 04:21:41 PM PST 24
Peak memory 200932 kb
Host smart-65a5ff96-3bd0-4be2-8904-6f8abaf92d51
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172674876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.172674876
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1756856847
Short name T209
Test name
Test status
Simulation time 129018056954 ps
CPU time 729.66 seconds
Started Mar 03 04:20:17 PM PST 24
Finished Mar 03 04:32:27 PM PST 24
Peak memory 201396 kb
Host smart-ab93f426-b256-4853-bae6-2fbb58d4a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756856847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1756856847
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3827169210
Short name T587
Test name
Test status
Simulation time 27269065500 ps
CPU time 8.88 seconds
Started Mar 03 04:20:18 PM PST 24
Finished Mar 03 04:20:27 PM PST 24
Peak memory 200764 kb
Host smart-2697863b-218e-4a3c-85bd-3418db3db070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827169210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3827169210
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.2473540391
Short name T504
Test name
Test status
Simulation time 3777674035 ps
CPU time 9.9 seconds
Started Mar 03 04:20:18 PM PST 24
Finished Mar 03 04:20:29 PM PST 24
Peak memory 200768 kb
Host smart-684dce4e-303b-4c09-a8e9-697a909bcaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473540391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.2473540391
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1139910593
Short name T454
Test name
Test status
Simulation time 5646888928 ps
CPU time 13.98 seconds
Started Mar 03 04:20:15 PM PST 24
Finished Mar 03 04:20:29 PM PST 24
Peak memory 200768 kb
Host smart-e8775d7e-c45a-44bf-b256-7401caf8f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139910593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1139910593
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.569714918
Short name T104
Test name
Test status
Simulation time 5313925303 ps
CPU time 7.02 seconds
Started Mar 03 04:20:25 PM PST 24
Finished Mar 03 04:20:32 PM PST 24
Peak memory 200740 kb
Host smart-ceb3dd15-dc97-4cab-af3a-34b5987aa82d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569714918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
569714918
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2351035511
Short name T207
Test name
Test status
Simulation time 1350462960637 ps
CPU time 279.08 seconds
Started Mar 03 04:20:20 PM PST 24
Finished Mar 03 04:24:59 PM PST 24
Peak memory 217392 kb
Host smart-3ba9879e-727f-4cad-9644-a71785c3ce9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351035511 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2351035511
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3446942506
Short name T641
Test name
Test status
Simulation time 453647385 ps
CPU time 1.63 seconds
Started Mar 03 04:20:34 PM PST 24
Finished Mar 03 04:20:36 PM PST 24
Peak memory 200660 kb
Host smart-dbea941f-23c4-46a3-b813-78c2177561d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446942506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3446942506
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1323971669
Short name T722
Test name
Test status
Simulation time 162540995565 ps
CPU time 178.89 seconds
Started Mar 03 04:20:29 PM PST 24
Finished Mar 03 04:23:28 PM PST 24
Peak memory 200920 kb
Host smart-6568cbc2-1090-4af9-9b79-feff078c7686
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323971669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1323971669
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.682941715
Short name T185
Test name
Test status
Simulation time 330649227946 ps
CPU time 91.12 seconds
Started Mar 03 04:20:25 PM PST 24
Finished Mar 03 04:21:56 PM PST 24
Peak memory 200848 kb
Host smart-68c843e0-412f-4f7d-94ec-9c5c3ccac9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682941715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.682941715
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3781160041
Short name T417
Test name
Test status
Simulation time 167221680001 ps
CPU time 185.42 seconds
Started Mar 03 04:20:26 PM PST 24
Finished Mar 03 04:23:32 PM PST 24
Peak memory 200904 kb
Host smart-1c4cd3a9-4756-4f07-ac42-85ddff48d7e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781160041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3781160041
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.284533977
Short name T398
Test name
Test status
Simulation time 165029024013 ps
CPU time 101.89 seconds
Started Mar 03 04:20:25 PM PST 24
Finished Mar 03 04:22:07 PM PST 24
Peak memory 200900 kb
Host smart-96cac10f-c6f3-4bde-9be0-5f8653dacf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284533977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.284533977
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1103056048
Short name T439
Test name
Test status
Simulation time 494940905343 ps
CPU time 1124.65 seconds
Started Mar 03 04:20:25 PM PST 24
Finished Mar 03 04:39:10 PM PST 24
Peak memory 200896 kb
Host smart-367a0f14-7463-4138-9bc7-e1c7666e3c22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103056048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1103056048
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1842950233
Short name T479
Test name
Test status
Simulation time 329896079174 ps
CPU time 690.12 seconds
Started Mar 03 04:20:28 PM PST 24
Finished Mar 03 04:31:58 PM PST 24
Peak memory 200908 kb
Host smart-7cd35d68-f291-4088-b3a0-f607e03e5a18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842950233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1842950233
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4028492381
Short name T688
Test name
Test status
Simulation time 172022446706 ps
CPU time 358.07 seconds
Started Mar 03 04:20:29 PM PST 24
Finished Mar 03 04:26:27 PM PST 24
Peak memory 200976 kb
Host smart-a454cae9-2b9c-4870-983e-701fa2c80437
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028492381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.4028492381
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4237611362
Short name T338
Test name
Test status
Simulation time 82512825971 ps
CPU time 450.67 seconds
Started Mar 03 04:20:30 PM PST 24
Finished Mar 03 04:28:01 PM PST 24
Peak memory 201404 kb
Host smart-2130cf9a-30b1-4b74-bfd6-9ff54aaa1e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237611362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4237611362
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2681514571
Short name T409
Test name
Test status
Simulation time 46742261541 ps
CPU time 100.38 seconds
Started Mar 03 04:20:30 PM PST 24
Finished Mar 03 04:22:10 PM PST 24
Peak memory 200764 kb
Host smart-6dd70f88-cf30-4854-8880-192433e4c925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681514571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2681514571
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.4051961570
Short name T560
Test name
Test status
Simulation time 3544283412 ps
CPU time 4.56 seconds
Started Mar 03 04:20:29 PM PST 24
Finished Mar 03 04:20:34 PM PST 24
Peak memory 200708 kb
Host smart-97a3c81d-e558-4649-9739-030a46ad8b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051961570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.4051961570
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2999806815
Short name T529
Test name
Test status
Simulation time 5560161903 ps
CPU time 5.53 seconds
Started Mar 03 04:20:24 PM PST 24
Finished Mar 03 04:20:29 PM PST 24
Peak memory 200636 kb
Host smart-859c368e-f24e-4de4-a04d-b838986247a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999806815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2999806815
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3013646102
Short name T472
Test name
Test status
Simulation time 520144498126 ps
CPU time 858.04 seconds
Started Mar 03 04:20:36 PM PST 24
Finished Mar 03 04:34:54 PM PST 24
Peak memory 211420 kb
Host smart-06e14c50-ebd3-4bd1-a77b-346a2eaed666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013646102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3013646102
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2342752106
Short name T205
Test name
Test status
Simulation time 232732371789 ps
CPU time 361.88 seconds
Started Mar 03 04:20:36 PM PST 24
Finished Mar 03 04:26:38 PM PST 24
Peak memory 209716 kb
Host smart-7eecbe05-25be-42bf-bf8c-4c1dd77a44f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342752106 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2342752106
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.99893896
Short name T498
Test name
Test status
Simulation time 497136744 ps
CPU time 1.95 seconds
Started Mar 03 04:16:09 PM PST 24
Finished Mar 03 04:16:11 PM PST 24
Peak memory 200704 kb
Host smart-4b83d8a1-bf0f-4df1-a8f6-e2b03fe4ee11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99893896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.99893896
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1374070977
Short name T264
Test name
Test status
Simulation time 323421115781 ps
CPU time 200.27 seconds
Started Mar 03 04:16:03 PM PST 24
Finished Mar 03 04:19:23 PM PST 24
Peak memory 200900 kb
Host smart-bf49a7bc-1ac1-4de3-b539-e5abfacfb5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374070977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1374070977
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3997394749
Short name T78
Test name
Test status
Simulation time 491217522578 ps
CPU time 1163.2 seconds
Started Mar 03 04:15:57 PM PST 24
Finished Mar 03 04:35:20 PM PST 24
Peak memory 200904 kb
Host smart-16ea903b-957c-4a87-a3a8-0fc68bc8d79c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997394749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3997394749
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3619263948
Short name T163
Test name
Test status
Simulation time 330133064543 ps
CPU time 686.01 seconds
Started Mar 03 04:15:56 PM PST 24
Finished Mar 03 04:27:23 PM PST 24
Peak memory 200904 kb
Host smart-4b6f7924-50c6-4d6b-b6ab-75e6b596ef10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619263948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3619263948
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.4133360096
Short name T513
Test name
Test status
Simulation time 330113882339 ps
CPU time 397.35 seconds
Started Mar 03 04:15:56 PM PST 24
Finished Mar 03 04:22:34 PM PST 24
Peak memory 200876 kb
Host smart-433750c5-f666-4ce9-b0cb-db63c133b9ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133360096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.4133360096
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3304809962
Short name T703
Test name
Test status
Simulation time 324246813633 ps
CPU time 691.98 seconds
Started Mar 03 04:16:05 PM PST 24
Finished Mar 03 04:27:37 PM PST 24
Peak memory 200828 kb
Host smart-00b9b3bd-eafd-4bfe-a3bc-8c080d87db51
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304809962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3304809962
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.289133713
Short name T25
Test name
Test status
Simulation time 101639175442 ps
CPU time 363.47 seconds
Started Mar 03 04:16:08 PM PST 24
Finished Mar 03 04:22:12 PM PST 24
Peak memory 201392 kb
Host smart-5515088c-7c7a-446e-b1f1-e8c99aa00bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289133713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.289133713
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3293948041
Short name T672
Test name
Test status
Simulation time 28297050776 ps
CPU time 32.24 seconds
Started Mar 03 04:16:08 PM PST 24
Finished Mar 03 04:16:40 PM PST 24
Peak memory 200744 kb
Host smart-d15de856-9299-4a30-93b8-b44b0fbc479b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293948041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3293948041
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1729888325
Short name T773
Test name
Test status
Simulation time 2804629928 ps
CPU time 2.42 seconds
Started Mar 03 04:16:03 PM PST 24
Finished Mar 03 04:16:06 PM PST 24
Peak memory 200772 kb
Host smart-12302a34-d84c-4069-a4f9-958766798dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729888325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1729888325
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1785787164
Short name T52
Test name
Test status
Simulation time 8488421696 ps
CPU time 5.37 seconds
Started Mar 03 04:16:07 PM PST 24
Finished Mar 03 04:16:12 PM PST 24
Peak memory 217208 kb
Host smart-ce618850-b6af-410f-8fa6-9653f6a54367
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785787164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1785787164
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2421015502
Short name T654
Test name
Test status
Simulation time 5964199445 ps
CPU time 14.75 seconds
Started Mar 03 04:15:56 PM PST 24
Finished Mar 03 04:16:11 PM PST 24
Peak memory 200752 kb
Host smart-6befde0e-e60e-41c3-961e-7f08c3d1c7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421015502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2421015502
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3024398268
Short name T632
Test name
Test status
Simulation time 603866659217 ps
CPU time 778.59 seconds
Started Mar 03 04:16:08 PM PST 24
Finished Mar 03 04:29:07 PM PST 24
Peak memory 209604 kb
Host smart-a0ed11b3-aa28-4db6-ae32-bc796960d059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024398268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3024398268
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1858779636
Short name T64
Test name
Test status
Simulation time 84873314025 ps
CPU time 88.44 seconds
Started Mar 03 04:16:09 PM PST 24
Finished Mar 03 04:17:38 PM PST 24
Peak memory 209720 kb
Host smart-c884547e-100b-44dc-9bf6-c8c3ef248167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858779636 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1858779636
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3321176629
Short name T395
Test name
Test status
Simulation time 517353047 ps
CPU time 1.74 seconds
Started Mar 03 04:20:46 PM PST 24
Finished Mar 03 04:20:47 PM PST 24
Peak memory 200584 kb
Host smart-1c261445-e822-4a78-90ac-80b19f579280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321176629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3321176629
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.740989810
Short name T580
Test name
Test status
Simulation time 494986407543 ps
CPU time 566.03 seconds
Started Mar 03 04:20:39 PM PST 24
Finished Mar 03 04:30:05 PM PST 24
Peak memory 200888 kb
Host smart-706edfd6-59c2-449f-9ae9-a023f1a610d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740989810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.740989810
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1661387104
Short name T631
Test name
Test status
Simulation time 165483119711 ps
CPU time 370.59 seconds
Started Mar 03 04:20:37 PM PST 24
Finished Mar 03 04:26:48 PM PST 24
Peak memory 200972 kb
Host smart-9c42019c-a419-41a7-aec1-d41c0a94a1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661387104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1661387104
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2453066674
Short name T708
Test name
Test status
Simulation time 162803787577 ps
CPU time 387.92 seconds
Started Mar 03 04:20:41 PM PST 24
Finished Mar 03 04:27:09 PM PST 24
Peak memory 200936 kb
Host smart-6a1d4845-dfc6-41f9-8b6f-e96305e2067e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453066674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2453066674
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3941578838
Short name T156
Test name
Test status
Simulation time 324204972015 ps
CPU time 346.97 seconds
Started Mar 03 04:20:36 PM PST 24
Finished Mar 03 04:26:23 PM PST 24
Peak memory 200912 kb
Host smart-55c5c888-5636-4c6b-b198-38a94489846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941578838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3941578838
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1198419628
Short name T714
Test name
Test status
Simulation time 325300408287 ps
CPU time 94.01 seconds
Started Mar 03 04:20:36 PM PST 24
Finished Mar 03 04:22:10 PM PST 24
Peak memory 200884 kb
Host smart-ca1e141a-e3a1-4743-8a4c-a64d7956e293
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198419628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1198419628
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.818283921
Short name T94
Test name
Test status
Simulation time 159927694442 ps
CPU time 100.46 seconds
Started Mar 03 04:20:42 PM PST 24
Finished Mar 03 04:22:22 PM PST 24
Peak memory 200868 kb
Host smart-35295d1e-5a4c-472d-8750-1843c549ccd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818283921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.818283921
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2471638431
Short name T780
Test name
Test status
Simulation time 495727193329 ps
CPU time 354.92 seconds
Started Mar 03 04:20:40 PM PST 24
Finished Mar 03 04:26:35 PM PST 24
Peak memory 200900 kb
Host smart-f62e1828-8206-4ec8-9e4d-e08815c7f14e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471638431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2471638431
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1263322898
Short name T522
Test name
Test status
Simulation time 89585816269 ps
CPU time 352.19 seconds
Started Mar 03 04:20:45 PM PST 24
Finished Mar 03 04:26:37 PM PST 24
Peak memory 201324 kb
Host smart-6a749de6-e859-41ea-b646-b758b8edfe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263322898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1263322898
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.753008018
Short name T566
Test name
Test status
Simulation time 39302954585 ps
CPU time 40.8 seconds
Started Mar 03 04:20:47 PM PST 24
Finished Mar 03 04:21:28 PM PST 24
Peak memory 200736 kb
Host smart-8b3d27a4-fb72-46ff-8487-63306c1c6704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753008018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.753008018
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3691563915
Short name T412
Test name
Test status
Simulation time 3615469674 ps
CPU time 1.78 seconds
Started Mar 03 04:20:46 PM PST 24
Finished Mar 03 04:20:47 PM PST 24
Peak memory 200768 kb
Host smart-915e0ffc-ea73-40f7-be4d-d70ddc9a3a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691563915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3691563915
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.435653579
Short name T518
Test name
Test status
Simulation time 5931728430 ps
CPU time 10.44 seconds
Started Mar 03 04:20:36 PM PST 24
Finished Mar 03 04:20:47 PM PST 24
Peak memory 200648 kb
Host smart-d739fc44-65c9-4aba-aabe-ee6a74244d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435653579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.435653579
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2235051268
Short name T204
Test name
Test status
Simulation time 27077871784 ps
CPU time 49.92 seconds
Started Mar 03 04:20:47 PM PST 24
Finished Mar 03 04:21:37 PM PST 24
Peak memory 209712 kb
Host smart-0df2a2f0-6e31-47f4-b2eb-56fa69738c42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235051268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2235051268
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3923453887
Short name T372
Test name
Test status
Simulation time 547843607 ps
CPU time 0.98 seconds
Started Mar 03 04:20:56 PM PST 24
Finished Mar 03 04:20:57 PM PST 24
Peak memory 200668 kb
Host smart-ff83b60a-d87e-4618-af6c-259bb859c21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923453887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3923453887
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.944420723
Short name T644
Test name
Test status
Simulation time 489755438472 ps
CPU time 796.32 seconds
Started Mar 03 04:20:50 PM PST 24
Finished Mar 03 04:34:07 PM PST 24
Peak memory 200932 kb
Host smart-c6537c49-ac10-469e-a655-0f73a8cbb421
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944420723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.944420723
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.727051229
Short name T175
Test name
Test status
Simulation time 481801905730 ps
CPU time 1114.96 seconds
Started Mar 03 04:20:51 PM PST 24
Finished Mar 03 04:39:26 PM PST 24
Peak memory 201172 kb
Host smart-05237e07-ab62-411a-a595-67191751104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727051229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.727051229
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2664000174
Short name T651
Test name
Test status
Simulation time 168364046762 ps
CPU time 193.36 seconds
Started Mar 03 04:20:51 PM PST 24
Finished Mar 03 04:24:04 PM PST 24
Peak memory 200912 kb
Host smart-72d86397-08a4-4374-b5c0-1e31b89f6858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664000174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2664000174
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2780314004
Short name T734
Test name
Test status
Simulation time 496594833564 ps
CPU time 180.74 seconds
Started Mar 03 04:20:51 PM PST 24
Finished Mar 03 04:23:51 PM PST 24
Peak memory 200912 kb
Host smart-bdc95f8e-de17-43f4-8f48-516a31ac2e88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780314004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2780314004
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1330143798
Short name T7
Test name
Test status
Simulation time 162467875105 ps
CPU time 49.6 seconds
Started Mar 03 04:20:52 PM PST 24
Finished Mar 03 04:21:42 PM PST 24
Peak memory 200896 kb
Host smart-2a09cb5c-a79c-46ca-a1d0-a273833755ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330143798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1330143798
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2510304871
Short name T11
Test name
Test status
Simulation time 162988357971 ps
CPU time 384.77 seconds
Started Mar 03 04:20:52 PM PST 24
Finished Mar 03 04:27:17 PM PST 24
Peak memory 200892 kb
Host smart-83aeb14a-87e5-41cc-b95e-f3852b489e34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510304871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2510304871
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.1429709837
Short name T653
Test name
Test status
Simulation time 329186352095 ps
CPU time 82.05 seconds
Started Mar 03 04:20:51 PM PST 24
Finished Mar 03 04:22:13 PM PST 24
Peak memory 200912 kb
Host smart-2011ae66-b3fc-4feb-a9e7-397a9e573c25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429709837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.1429709837
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3644733746
Short name T760
Test name
Test status
Simulation time 328953597005 ps
CPU time 711.73 seconds
Started Mar 03 04:20:52 PM PST 24
Finished Mar 03 04:32:44 PM PST 24
Peak memory 200896 kb
Host smart-17b65059-d991-4174-9001-d4ff997ad278
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644733746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3644733746
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2769151798
Short name T727
Test name
Test status
Simulation time 121998039484 ps
CPU time 449.9 seconds
Started Mar 03 04:20:57 PM PST 24
Finished Mar 03 04:28:27 PM PST 24
Peak memory 201420 kb
Host smart-dc568a2f-b2dc-4e01-93cf-ebfb60fedcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769151798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2769151798
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4045298672
Short name T437
Test name
Test status
Simulation time 49999419489 ps
CPU time 29.44 seconds
Started Mar 03 04:20:55 PM PST 24
Finished Mar 03 04:21:25 PM PST 24
Peak memory 200752 kb
Host smart-bf0a4fa4-e693-4efe-849e-b13f9a944b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045298672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4045298672
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.514265785
Short name T549
Test name
Test status
Simulation time 2850646572 ps
CPU time 2.25 seconds
Started Mar 03 04:20:56 PM PST 24
Finished Mar 03 04:20:59 PM PST 24
Peak memory 200700 kb
Host smart-11837ae3-56f2-4f91-88a3-edb519bcad8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514265785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.514265785
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3707065482
Short name T105
Test name
Test status
Simulation time 6116574614 ps
CPU time 14.25 seconds
Started Mar 03 04:20:45 PM PST 24
Finished Mar 03 04:21:00 PM PST 24
Peak memory 200736 kb
Host smart-44b4ed70-d376-4ceb-9fd3-24b0769685e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707065482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3707065482
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3950139167
Short name T259
Test name
Test status
Simulation time 171587047784 ps
CPU time 391.36 seconds
Started Mar 03 04:20:55 PM PST 24
Finished Mar 03 04:27:27 PM PST 24
Peak memory 200964 kb
Host smart-5bcd0773-018d-4918-a568-23a38fbdf5ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950139167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3950139167
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3496010423
Short name T103
Test name
Test status
Simulation time 173681794079 ps
CPU time 142.93 seconds
Started Mar 03 04:20:58 PM PST 24
Finished Mar 03 04:23:21 PM PST 24
Peak memory 209356 kb
Host smart-fcf022b5-8c6e-4b09-a45e-e07433cf06e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496010423 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3496010423
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2711197566
Short name T586
Test name
Test status
Simulation time 507873020 ps
CPU time 1.8 seconds
Started Mar 03 04:21:04 PM PST 24
Finished Mar 03 04:21:06 PM PST 24
Peak memory 200908 kb
Host smart-bbb7180e-662c-45a0-a69c-a89d4859d69e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711197566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2711197566
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4289596029
Short name T236
Test name
Test status
Simulation time 174286465174 ps
CPU time 42.53 seconds
Started Mar 03 04:21:03 PM PST 24
Finished Mar 03 04:21:46 PM PST 24
Peak memory 200884 kb
Host smart-844e06ff-9824-4738-86e5-f33e976dd881
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289596029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4289596029
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.552057717
Short name T329
Test name
Test status
Simulation time 322383544377 ps
CPU time 339.65 seconds
Started Mar 03 04:21:02 PM PST 24
Finished Mar 03 04:26:43 PM PST 24
Peak memory 200972 kb
Host smart-1c892b20-28a9-486f-889a-24dcf57366cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552057717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.552057717
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3608630995
Short name T603
Test name
Test status
Simulation time 495262575933 ps
CPU time 321.18 seconds
Started Mar 03 04:21:06 PM PST 24
Finished Mar 03 04:26:27 PM PST 24
Peak memory 200876 kb
Host smart-363b0268-0a80-4518-ab57-1150b7266aab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608630995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3608630995
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1289867997
Short name T272
Test name
Test status
Simulation time 169383827927 ps
CPU time 177.61 seconds
Started Mar 03 04:20:56 PM PST 24
Finished Mar 03 04:23:54 PM PST 24
Peak memory 200972 kb
Host smart-75b16de5-250b-4066-982d-d34272999d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289867997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1289867997
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.385254042
Short name T503
Test name
Test status
Simulation time 492126926184 ps
CPU time 1158.64 seconds
Started Mar 03 04:20:56 PM PST 24
Finished Mar 03 04:40:15 PM PST 24
Peak memory 200888 kb
Host smart-5a570515-b844-48f3-876c-5407d83e2fd4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=385254042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.385254042
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1757020817
Short name T746
Test name
Test status
Simulation time 349189222250 ps
CPU time 191.2 seconds
Started Mar 03 04:21:04 PM PST 24
Finished Mar 03 04:24:16 PM PST 24
Peak memory 200896 kb
Host smart-d8de075a-092b-4f28-8d9a-98dcbf23177d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757020817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1757020817
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4209696943
Short name T383
Test name
Test status
Simulation time 168166450139 ps
CPU time 355.19 seconds
Started Mar 03 04:21:03 PM PST 24
Finished Mar 03 04:26:59 PM PST 24
Peak memory 200896 kb
Host smart-beef3cfd-b3dc-440d-af14-330f9a4b3a1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209696943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4209696943
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3945638516
Short name T188
Test name
Test status
Simulation time 92266742807 ps
CPU time 355.89 seconds
Started Mar 03 04:21:04 PM PST 24
Finished Mar 03 04:27:00 PM PST 24
Peak memory 201392 kb
Host smart-4f9071f5-4e25-40fa-8772-c88cbd09e613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945638516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3945638516
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.779348011
Short name T80
Test name
Test status
Simulation time 29242798593 ps
CPU time 37.1 seconds
Started Mar 03 04:21:04 PM PST 24
Finished Mar 03 04:21:41 PM PST 24
Peak memory 200768 kb
Host smart-29b7c70f-5d05-4311-bcc7-38eb41b18fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779348011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.779348011
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3302376246
Short name T353
Test name
Test status
Simulation time 4880257663 ps
CPU time 1.84 seconds
Started Mar 03 04:21:03 PM PST 24
Finished Mar 03 04:21:05 PM PST 24
Peak memory 200784 kb
Host smart-93123a9e-6e0d-4b8d-bbec-7821c386ae61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302376246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3302376246
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2672056238
Short name T781
Test name
Test status
Simulation time 5670476603 ps
CPU time 9.11 seconds
Started Mar 03 04:21:01 PM PST 24
Finished Mar 03 04:21:11 PM PST 24
Peak memory 200768 kb
Host smart-55c91dd1-a30a-43cc-bbdb-1e501866f25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672056238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2672056238
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1794852382
Short name T548
Test name
Test status
Simulation time 278711031006 ps
CPU time 907.51 seconds
Started Mar 03 04:21:02 PM PST 24
Finished Mar 03 04:36:10 PM PST 24
Peak memory 209628 kb
Host smart-12099bae-4dd9-4943-b740-947f19a87714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794852382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1794852382
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.356676333
Short name T686
Test name
Test status
Simulation time 622981148703 ps
CPU time 243.63 seconds
Started Mar 03 04:21:06 PM PST 24
Finished Mar 03 04:25:10 PM PST 24
Peak memory 209660 kb
Host smart-702fd2d6-172f-491a-821c-ef5f87178fbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356676333 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.356676333
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.337503200
Short name T100
Test name
Test status
Simulation time 355801693 ps
CPU time 1.48 seconds
Started Mar 03 04:21:08 PM PST 24
Finished Mar 03 04:21:10 PM PST 24
Peak memory 200692 kb
Host smart-e04ca911-7078-45c5-81e1-128ff545e911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337503200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.337503200
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1191082118
Short name T287
Test name
Test status
Simulation time 495735164457 ps
CPU time 1228.5 seconds
Started Mar 03 04:21:08 PM PST 24
Finished Mar 03 04:41:37 PM PST 24
Peak memory 200952 kb
Host smart-990d9dc1-8327-4dd0-9084-509aa2c82996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191082118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1191082118
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.496084222
Short name T671
Test name
Test status
Simulation time 329441547082 ps
CPU time 533.24 seconds
Started Mar 03 04:21:03 PM PST 24
Finished Mar 03 04:29:57 PM PST 24
Peak memory 200948 kb
Host smart-ab3b1425-f6b5-4bb1-b3b9-c0ba3c8ecf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496084222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.496084222
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2700998587
Short name T582
Test name
Test status
Simulation time 489565217066 ps
CPU time 1119.23 seconds
Started Mar 03 04:21:02 PM PST 24
Finished Mar 03 04:39:42 PM PST 24
Peak memory 201156 kb
Host smart-ff07b3b3-de08-473e-92aa-5b9b96baa1cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700998587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2700998587
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2525082945
Short name T528
Test name
Test status
Simulation time 493177810964 ps
CPU time 440.3 seconds
Started Mar 03 04:21:04 PM PST 24
Finished Mar 03 04:28:25 PM PST 24
Peak memory 200900 kb
Host smart-6d68eb4a-c5ff-43a8-a340-7b33a807a75a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525082945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2525082945
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.604729502
Short name T733
Test name
Test status
Simulation time 497461364339 ps
CPU time 318.45 seconds
Started Mar 03 04:21:02 PM PST 24
Finished Mar 03 04:26:21 PM PST 24
Peak memory 200904 kb
Host smart-5a4806a4-fd01-4221-ac72-6a220e88bc66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604729502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.604729502
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1728098808
Short name T177
Test name
Test status
Simulation time 320288184611 ps
CPU time 183.42 seconds
Started Mar 03 04:21:06 PM PST 24
Finished Mar 03 04:24:09 PM PST 24
Peak memory 200900 kb
Host smart-8cbb2a88-9a0a-4893-a961-599b88dcb4a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728098808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1728098808
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1029106562
Short name T345
Test name
Test status
Simulation time 121761195188 ps
CPU time 405.2 seconds
Started Mar 03 04:21:08 PM PST 24
Finished Mar 03 04:27:53 PM PST 24
Peak memory 201408 kb
Host smart-4c47f0d8-f031-4d90-92e7-a8f3b1a6cb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029106562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1029106562
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1661982657
Short name T376
Test name
Test status
Simulation time 39227644496 ps
CPU time 26.32 seconds
Started Mar 03 04:21:08 PM PST 24
Finished Mar 03 04:21:35 PM PST 24
Peak memory 200760 kb
Host smart-c4da9f88-c3a7-4288-a4c8-ce36f0fa82dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661982657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1661982657
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2429015629
Short name T537
Test name
Test status
Simulation time 2939021074 ps
CPU time 6.75 seconds
Started Mar 03 04:21:07 PM PST 24
Finished Mar 03 04:21:13 PM PST 24
Peak memory 200696 kb
Host smart-0e626570-6122-41fd-8b0c-7ad9f6977e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429015629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2429015629
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3389760531
Short name T355
Test name
Test status
Simulation time 5845058930 ps
CPU time 2.48 seconds
Started Mar 03 04:21:03 PM PST 24
Finished Mar 03 04:21:06 PM PST 24
Peak memory 200772 kb
Host smart-fbb872a0-3cdb-49dd-ad60-b7a6bd7309a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389760531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3389760531
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2263842602
Short name T743
Test name
Test status
Simulation time 68723204327 ps
CPU time 224.57 seconds
Started Mar 03 04:21:08 PM PST 24
Finished Mar 03 04:24:53 PM PST 24
Peak memory 201408 kb
Host smart-c03a25d6-3c08-41a2-b5f2-5cbce673b0a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263842602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2263842602
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.679214632
Short name T639
Test name
Test status
Simulation time 154083921883 ps
CPU time 57.8 seconds
Started Mar 03 04:21:08 PM PST 24
Finished Mar 03 04:22:06 PM PST 24
Peak memory 210260 kb
Host smart-6981aed5-ba8c-49e6-b0e2-286d2485dcad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679214632 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.679214632
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3023876774
Short name T475
Test name
Test status
Simulation time 432546339 ps
CPU time 0.86 seconds
Started Mar 03 04:21:20 PM PST 24
Finished Mar 03 04:21:21 PM PST 24
Peak memory 200692 kb
Host smart-39295cbc-8e5b-4e8e-a508-70536601b53d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023876774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3023876774
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3254473634
Short name T6
Test name
Test status
Simulation time 161252133755 ps
CPU time 363 seconds
Started Mar 03 04:21:16 PM PST 24
Finished Mar 03 04:27:19 PM PST 24
Peak memory 200900 kb
Host smart-ecad4d6e-2487-4a0d-8b41-d91c3ac68806
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254473634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3254473634
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1514305362
Short name T307
Test name
Test status
Simulation time 326575383462 ps
CPU time 358.11 seconds
Started Mar 03 04:21:15 PM PST 24
Finished Mar 03 04:27:13 PM PST 24
Peak memory 200972 kb
Host smart-be9f33b3-1c9b-458d-8de6-e1660c61fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514305362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1514305362
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.1678975712
Short name T577
Test name
Test status
Simulation time 165772383903 ps
CPU time 94.14 seconds
Started Mar 03 04:21:08 PM PST 24
Finished Mar 03 04:22:43 PM PST 24
Peak memory 200908 kb
Host smart-84169f7f-0ef5-4301-bb0d-065392775b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678975712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.1678975712
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1284567660
Short name T694
Test name
Test status
Simulation time 169389358815 ps
CPU time 402.11 seconds
Started Mar 03 04:21:17 PM PST 24
Finished Mar 03 04:28:00 PM PST 24
Peak memory 200956 kb
Host smart-8e38243e-2104-4084-a68b-ae702435f674
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284567660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1284567660
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3445265825
Short name T1
Test name
Test status
Simulation time 489259717228 ps
CPU time 1204.74 seconds
Started Mar 03 04:21:08 PM PST 24
Finished Mar 03 04:41:13 PM PST 24
Peak memory 200936 kb
Host smart-d2c5473d-f7f5-4cfb-8f6d-00335e871c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445265825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3445265825
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1886028042
Short name T510
Test name
Test status
Simulation time 168302016824 ps
CPU time 102.81 seconds
Started Mar 03 04:21:07 PM PST 24
Finished Mar 03 04:22:50 PM PST 24
Peak memory 200900 kb
Host smart-3fdbab44-234c-4c97-8474-e6f8d54474eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886028042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1886028042
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2518065176
Short name T465
Test name
Test status
Simulation time 324880552352 ps
CPU time 181.15 seconds
Started Mar 03 04:21:17 PM PST 24
Finished Mar 03 04:24:18 PM PST 24
Peak memory 200832 kb
Host smart-afe82fa3-01f9-48e1-8342-6df331048254
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518065176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2518065176
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2347359778
Short name T568
Test name
Test status
Simulation time 484648067047 ps
CPU time 305.25 seconds
Started Mar 03 04:21:16 PM PST 24
Finished Mar 03 04:26:22 PM PST 24
Peak memory 200904 kb
Host smart-6bb30dc9-18fe-4b30-8d43-b909338cee94
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347359778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2347359778
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2084398159
Short name T592
Test name
Test status
Simulation time 112586669123 ps
CPU time 556.81 seconds
Started Mar 03 04:21:15 PM PST 24
Finished Mar 03 04:30:32 PM PST 24
Peak memory 201312 kb
Host smart-0f7fbc99-27dd-4c62-9122-2284ba723c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084398159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2084398159
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.4219380322
Short name T418
Test name
Test status
Simulation time 41619975636 ps
CPU time 24.04 seconds
Started Mar 03 04:21:15 PM PST 24
Finished Mar 03 04:21:39 PM PST 24
Peak memory 200744 kb
Host smart-8f2dd06b-aec0-4f84-a084-cd46c397e8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219380322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.4219380322
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.4284717385
Short name T660
Test name
Test status
Simulation time 3143759789 ps
CPU time 8.71 seconds
Started Mar 03 04:21:16 PM PST 24
Finished Mar 03 04:21:25 PM PST 24
Peak memory 200732 kb
Host smart-b71e1140-2e5d-456b-9926-bd4da8a508af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284717385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.4284717385
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2110647709
Short name T534
Test name
Test status
Simulation time 5510034863 ps
CPU time 6.8 seconds
Started Mar 03 04:21:07 PM PST 24
Finished Mar 03 04:21:14 PM PST 24
Peak memory 200760 kb
Host smart-8ae94503-5f38-42f3-a4c1-220ed5ef90e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110647709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2110647709
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3490930045
Short name T306
Test name
Test status
Simulation time 333410890299 ps
CPU time 137.87 seconds
Started Mar 03 04:21:21 PM PST 24
Finished Mar 03 04:23:39 PM PST 24
Peak memory 200956 kb
Host smart-8d3a9c7e-447a-4dc7-acff-9357503fd79f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490930045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3490930045
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2638420483
Short name T523
Test name
Test status
Simulation time 389571977 ps
CPU time 0.8 seconds
Started Mar 03 04:21:26 PM PST 24
Finished Mar 03 04:21:28 PM PST 24
Peak memory 200704 kb
Host smart-b8f48cc2-397b-4a94-a687-3ead827e4fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638420483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2638420483
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3543989434
Short name T322
Test name
Test status
Simulation time 162918878626 ps
CPU time 354.68 seconds
Started Mar 03 04:21:19 PM PST 24
Finished Mar 03 04:27:14 PM PST 24
Peak memory 200944 kb
Host smart-6d2445da-976c-42c7-8c47-1edf85c5c36e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543989434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3543989434
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1999724488
Short name T183
Test name
Test status
Simulation time 491878941433 ps
CPU time 215.38 seconds
Started Mar 03 04:21:20 PM PST 24
Finished Mar 03 04:24:56 PM PST 24
Peak memory 200984 kb
Host smart-bb90f1b4-3d81-4bdb-bee0-7c181be1c79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999724488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1999724488
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.713795847
Short name T219
Test name
Test status
Simulation time 328899124559 ps
CPU time 754.34 seconds
Started Mar 03 04:21:21 PM PST 24
Finished Mar 03 04:33:56 PM PST 24
Peak memory 200848 kb
Host smart-afc2626d-d9f2-4b6f-beed-29a43cbdafd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713795847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.713795847
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.702195459
Short name T435
Test name
Test status
Simulation time 329512453673 ps
CPU time 422.45 seconds
Started Mar 03 04:21:20 PM PST 24
Finished Mar 03 04:28:23 PM PST 24
Peak memory 200868 kb
Host smart-5e6e80eb-4da7-456e-85b5-4b0378b35c1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=702195459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.702195459
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2488526585
Short name T629
Test name
Test status
Simulation time 485110071950 ps
CPU time 287.59 seconds
Started Mar 03 04:21:18 PM PST 24
Finished Mar 03 04:26:06 PM PST 24
Peak memory 200968 kb
Host smart-402ad68c-ecb1-4265-a295-e2d353264087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488526585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2488526585
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.157073661
Short name T431
Test name
Test status
Simulation time 328719248502 ps
CPU time 782.83 seconds
Started Mar 03 04:21:21 PM PST 24
Finished Mar 03 04:34:24 PM PST 24
Peak memory 200956 kb
Host smart-59c042a8-c1ca-4a06-b58b-7f580c4c4d0c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=157073661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.157073661
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1908193518
Short name T266
Test name
Test status
Simulation time 336616066789 ps
CPU time 187.22 seconds
Started Mar 03 04:21:20 PM PST 24
Finished Mar 03 04:24:28 PM PST 24
Peak memory 200892 kb
Host smart-62a01101-9ce9-4c36-9114-bfecee0ddae5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908193518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1908193518
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.467902072
Short name T10
Test name
Test status
Simulation time 490154230202 ps
CPU time 150.79 seconds
Started Mar 03 04:21:20 PM PST 24
Finished Mar 03 04:23:51 PM PST 24
Peak memory 200892 kb
Host smart-adfa1941-e178-4159-84b7-5ce15ed698b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467902072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.467902072
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3341256686
Short name T396
Test name
Test status
Simulation time 28400771780 ps
CPU time 18.17 seconds
Started Mar 03 04:21:25 PM PST 24
Finished Mar 03 04:21:43 PM PST 24
Peak memory 200644 kb
Host smart-ffaca7b3-6d57-4dff-855f-184c3ef4300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341256686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3341256686
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1549772996
Short name T755
Test name
Test status
Simulation time 5216141151 ps
CPU time 13.15 seconds
Started Mar 03 04:21:21 PM PST 24
Finished Mar 03 04:21:35 PM PST 24
Peak memory 200720 kb
Host smart-c1bcce0f-e568-472f-bce1-b1614f6000e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549772996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1549772996
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.490733250
Short name T390
Test name
Test status
Simulation time 5927066820 ps
CPU time 4.63 seconds
Started Mar 03 04:21:18 PM PST 24
Finished Mar 03 04:21:23 PM PST 24
Peak memory 200700 kb
Host smart-3ce269d6-a818-46be-89c3-697e7dd00a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490733250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.490733250
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.605935807
Short name T342
Test name
Test status
Simulation time 472799113745 ps
CPU time 565.55 seconds
Started Mar 03 04:21:27 PM PST 24
Finished Mar 03 04:30:53 PM PST 24
Peak memory 209588 kb
Host smart-662d05b4-2f3f-4ba1-bfef-d34c6913c7b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605935807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
605935807
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.304629237
Short name T604
Test name
Test status
Simulation time 358037586428 ps
CPU time 218.4 seconds
Started Mar 03 04:21:26 PM PST 24
Finished Mar 03 04:25:04 PM PST 24
Peak memory 201532 kb
Host smart-149b8634-80c8-4ea8-a239-287b87cb71f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304629237 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.304629237
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2297794540
Short name T350
Test name
Test status
Simulation time 579918845 ps
CPU time 0.76 seconds
Started Mar 03 04:21:31 PM PST 24
Finished Mar 03 04:21:34 PM PST 24
Peak memory 200708 kb
Host smart-6eb52ea1-8cd4-4a1a-8cd6-0457212f545b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297794540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2297794540
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3256044000
Short name T317
Test name
Test status
Simulation time 328706431963 ps
CPU time 695.78 seconds
Started Mar 03 04:21:32 PM PST 24
Finished Mar 03 04:33:09 PM PST 24
Peak memory 200968 kb
Host smart-b703a06d-37e7-4b7d-b09f-236b31f85113
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256044000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3256044000
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3607901903
Short name T235
Test name
Test status
Simulation time 167847910649 ps
CPU time 100.83 seconds
Started Mar 03 04:21:25 PM PST 24
Finished Mar 03 04:23:06 PM PST 24
Peak memory 200976 kb
Host smart-5876042d-02d9-4059-ae03-4ed98214ccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607901903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3607901903
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2018213168
Short name T526
Test name
Test status
Simulation time 330694363636 ps
CPU time 404.53 seconds
Started Mar 03 04:21:26 PM PST 24
Finished Mar 03 04:28:12 PM PST 24
Peak memory 200960 kb
Host smart-800173cd-ed69-4494-a50c-2fb6427c2fbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018213168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2018213168
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4014291855
Short name T168
Test name
Test status
Simulation time 321445280564 ps
CPU time 391.4 seconds
Started Mar 03 04:21:26 PM PST 24
Finished Mar 03 04:27:58 PM PST 24
Peak memory 200872 kb
Host smart-17d35451-0bca-4212-80a0-7f2c1c0311cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014291855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4014291855
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3540184911
Short name T571
Test name
Test status
Simulation time 332941369489 ps
CPU time 504.15 seconds
Started Mar 03 04:21:26 PM PST 24
Finished Mar 03 04:29:51 PM PST 24
Peak memory 200904 kb
Host smart-91a39fc0-af01-488d-b772-d38bdacc48d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540184911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3540184911
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3134880173
Short name T747
Test name
Test status
Simulation time 497729504837 ps
CPU time 1095.18 seconds
Started Mar 03 04:21:26 PM PST 24
Finished Mar 03 04:39:41 PM PST 24
Peak memory 200876 kb
Host smart-3091d770-11d6-4b6a-94e4-3a32a864b935
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134880173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3134880173
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2352510241
Short name T515
Test name
Test status
Simulation time 336962792871 ps
CPU time 192.4 seconds
Started Mar 03 04:21:31 PM PST 24
Finished Mar 03 04:24:44 PM PST 24
Peak memory 200792 kb
Host smart-b2e4eceb-95f4-4a7b-9ed9-32a6a154744a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352510241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2352510241
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1151896133
Short name T23
Test name
Test status
Simulation time 89308271242 ps
CPU time 481.44 seconds
Started Mar 03 04:21:29 PM PST 24
Finished Mar 03 04:29:32 PM PST 24
Peak memory 201324 kb
Host smart-fbba6013-1e59-482a-a2b9-b56e438a873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151896133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1151896133
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2736903491
Short name T402
Test name
Test status
Simulation time 44890884193 ps
CPU time 111.53 seconds
Started Mar 03 04:21:31 PM PST 24
Finished Mar 03 04:23:24 PM PST 24
Peak memory 200748 kb
Host smart-593921a8-c161-45b3-871e-1352895504be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736903491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2736903491
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.754013375
Short name T589
Test name
Test status
Simulation time 4568165728 ps
CPU time 7.27 seconds
Started Mar 03 04:21:32 PM PST 24
Finished Mar 03 04:21:40 PM PST 24
Peak memory 200768 kb
Host smart-f696bc02-83d4-4266-843f-20141c1336a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754013375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.754013375
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1360030831
Short name T728
Test name
Test status
Simulation time 5618951069 ps
CPU time 7.44 seconds
Started Mar 03 04:21:25 PM PST 24
Finished Mar 03 04:21:32 PM PST 24
Peak memory 200760 kb
Host smart-f74e84dd-cea6-414f-8239-306f9963e52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360030831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1360030831
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.292331731
Short name T203
Test name
Test status
Simulation time 124581361398 ps
CPU time 293.25 seconds
Started Mar 03 04:21:29 PM PST 24
Finished Mar 03 04:26:23 PM PST 24
Peak memory 209672 kb
Host smart-800dc16b-7f48-4aa6-94dd-88fe188cc35e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292331731 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.292331731
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.226958824
Short name T378
Test name
Test status
Simulation time 441372679 ps
CPU time 1.61 seconds
Started Mar 03 04:21:43 PM PST 24
Finished Mar 03 04:21:44 PM PST 24
Peak memory 200900 kb
Host smart-3c3748f5-ac85-4b0b-a1c8-dfb55ca9805a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226958824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.226958824
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.567252558
Short name T757
Test name
Test status
Simulation time 499713892291 ps
CPU time 561.8 seconds
Started Mar 03 04:21:35 PM PST 24
Finished Mar 03 04:30:58 PM PST 24
Peak memory 200856 kb
Host smart-b2b62788-6e02-4b56-a462-e4cb27821533
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567252558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.567252558
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.230005468
Short name T683
Test name
Test status
Simulation time 332329995336 ps
CPU time 781.32 seconds
Started Mar 03 04:21:40 PM PST 24
Finished Mar 03 04:34:42 PM PST 24
Peak memory 201004 kb
Host smart-964a15bb-7011-4077-bc73-ce7ff69b51ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230005468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.230005468
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2302196524
Short name T581
Test name
Test status
Simulation time 330218733026 ps
CPU time 224.31 seconds
Started Mar 03 04:21:36 PM PST 24
Finished Mar 03 04:25:21 PM PST 24
Peak memory 200996 kb
Host smart-8402d55a-b8d0-4f74-b9f8-280082820b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302196524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2302196524
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.702738173
Short name T512
Test name
Test status
Simulation time 489979412632 ps
CPU time 614.81 seconds
Started Mar 03 04:21:35 PM PST 24
Finished Mar 03 04:31:51 PM PST 24
Peak memory 200840 kb
Host smart-dc45629a-c272-4fb7-8f60-86cd02dbfd04
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=702738173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.702738173
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.151963959
Short name T221
Test name
Test status
Simulation time 491657197625 ps
CPU time 537.16 seconds
Started Mar 03 04:21:30 PM PST 24
Finished Mar 03 04:30:29 PM PST 24
Peak memory 200904 kb
Host smart-c78fcf7b-65ab-4b8c-892d-e7b3ebbde49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151963959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.151963959
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1068298490
Short name T670
Test name
Test status
Simulation time 495117662812 ps
CPU time 259.57 seconds
Started Mar 03 04:21:36 PM PST 24
Finished Mar 03 04:25:56 PM PST 24
Peak memory 200904 kb
Host smart-d1b441fe-8854-4513-8796-264a882a64ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068298490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1068298490
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.4166551406
Short name T295
Test name
Test status
Simulation time 162973263380 ps
CPU time 102.11 seconds
Started Mar 03 04:21:35 PM PST 24
Finished Mar 03 04:23:18 PM PST 24
Peak memory 201100 kb
Host smart-e34b4c00-8472-4a35-a2ce-0c1e9f3eaf07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166551406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.4166551406
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.46607647
Short name T58
Test name
Test status
Simulation time 329337037528 ps
CPU time 88.22 seconds
Started Mar 03 04:21:36 PM PST 24
Finished Mar 03 04:23:05 PM PST 24
Peak memory 200900 kb
Host smart-aa69b3d3-5219-41af-9281-5a816e5bc468
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46607647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.a
dc_ctrl_filters_wakeup_fixed.46607647
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2641348091
Short name T719
Test name
Test status
Simulation time 114926049334 ps
CPU time 627.02 seconds
Started Mar 03 04:21:41 PM PST 24
Finished Mar 03 04:32:08 PM PST 24
Peak memory 201312 kb
Host smart-7d7b5f58-e9ff-48d0-b553-2b1bb7901410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641348091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2641348091
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2241385932
Short name T655
Test name
Test status
Simulation time 27942411217 ps
CPU time 16.97 seconds
Started Mar 03 04:21:42 PM PST 24
Finished Mar 03 04:21:59 PM PST 24
Peak memory 200688 kb
Host smart-5ed48efc-cdeb-4160-b22f-53c064eb92ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241385932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2241385932
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1957349195
Short name T419
Test name
Test status
Simulation time 3156273033 ps
CPU time 4.08 seconds
Started Mar 03 04:21:40 PM PST 24
Finished Mar 03 04:21:44 PM PST 24
Peak memory 200768 kb
Host smart-1b042e18-d055-466d-bf15-056513193ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957349195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1957349195
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2722476107
Short name T659
Test name
Test status
Simulation time 6015489339 ps
CPU time 3.89 seconds
Started Mar 03 04:21:29 PM PST 24
Finished Mar 03 04:21:33 PM PST 24
Peak memory 200704 kb
Host smart-99830f6b-1108-493a-a355-4e5202fc94de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722476107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2722476107
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3957494508
Short name T74
Test name
Test status
Simulation time 167999544839 ps
CPU time 97.7 seconds
Started Mar 03 04:21:40 PM PST 24
Finished Mar 03 04:23:18 PM PST 24
Peak memory 200960 kb
Host smart-f3b56b70-e870-44b5-aae9-8455ac6f40bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957494508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3957494508
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.804346018
Short name T239
Test name
Test status
Simulation time 53007205545 ps
CPU time 58.17 seconds
Started Mar 03 04:21:42 PM PST 24
Finished Mar 03 04:22:40 PM PST 24
Peak memory 201100 kb
Host smart-77f404ae-083f-4c17-a8d2-bcbdaddf1c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804346018 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.804346018
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1539150232
Short name T790
Test name
Test status
Simulation time 547470895 ps
CPU time 0.7 seconds
Started Mar 03 04:21:55 PM PST 24
Finished Mar 03 04:21:56 PM PST 24
Peak memory 200620 kb
Host smart-b1246191-158c-41f2-984a-e28e0e4095f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539150232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1539150232
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.56029840
Short name T328
Test name
Test status
Simulation time 173388452225 ps
CPU time 393.5 seconds
Started Mar 03 04:21:46 PM PST 24
Finished Mar 03 04:28:19 PM PST 24
Peak memory 200896 kb
Host smart-cd8a52fa-de8b-47aa-bac3-76ecdefdaee2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56029840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gatin
g.56029840
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3821129280
Short name T184
Test name
Test status
Simulation time 496113164295 ps
CPU time 283.17 seconds
Started Mar 03 04:21:48 PM PST 24
Finished Mar 03 04:26:31 PM PST 24
Peak memory 200864 kb
Host smart-9ea0b5e5-0c1c-46fb-add8-af521f51a0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821129280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3821129280
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2221182157
Short name T199
Test name
Test status
Simulation time 329325763914 ps
CPU time 207.36 seconds
Started Mar 03 04:21:47 PM PST 24
Finished Mar 03 04:25:15 PM PST 24
Peak memory 200924 kb
Host smart-a5948f32-b870-48a1-9906-923c5d67bb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221182157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2221182157
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3931124182
Short name T678
Test name
Test status
Simulation time 326941351920 ps
CPU time 229.2 seconds
Started Mar 03 04:21:46 PM PST 24
Finished Mar 03 04:25:36 PM PST 24
Peak memory 200960 kb
Host smart-39b6386f-671b-4a37-9e2b-baad94427997
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931124182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3931124182
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1490449507
Short name T95
Test name
Test status
Simulation time 493171621571 ps
CPU time 1141.69 seconds
Started Mar 03 04:21:42 PM PST 24
Finished Mar 03 04:40:44 PM PST 24
Peak memory 200936 kb
Host smart-b7d55d17-b29e-46f2-91fe-4b0b0d2dc778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490449507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1490449507
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1014650464
Short name T492
Test name
Test status
Simulation time 165401703524 ps
CPU time 93.15 seconds
Started Mar 03 04:21:41 PM PST 24
Finished Mar 03 04:23:15 PM PST 24
Peak memory 200952 kb
Host smart-e6f0c257-4001-43e7-85b8-1f705201a12a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014650464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1014650464
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2246172117
Short name T476
Test name
Test status
Simulation time 163609638150 ps
CPU time 100.17 seconds
Started Mar 03 04:21:47 PM PST 24
Finished Mar 03 04:23:27 PM PST 24
Peak memory 200904 kb
Host smart-2ed48075-4c10-486f-9a0e-6d3df83bb456
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246172117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2246172117
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1520712071
Short name T88
Test name
Test status
Simulation time 77722916476 ps
CPU time 436.35 seconds
Started Mar 03 04:21:47 PM PST 24
Finished Mar 03 04:29:04 PM PST 24
Peak memory 201292 kb
Host smart-389f769b-ecde-45c9-9de2-dc0ed4891c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520712071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1520712071
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1301305261
Short name T352
Test name
Test status
Simulation time 43809754668 ps
CPU time 97.43 seconds
Started Mar 03 04:21:47 PM PST 24
Finished Mar 03 04:23:25 PM PST 24
Peak memory 200680 kb
Host smart-900a6038-a98b-49e9-bbd1-c4243676b02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301305261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1301305261
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1035517699
Short name T543
Test name
Test status
Simulation time 4341813403 ps
CPU time 5.98 seconds
Started Mar 03 04:21:47 PM PST 24
Finished Mar 03 04:21:53 PM PST 24
Peak memory 200772 kb
Host smart-f7a32d63-7f9c-4994-ba3f-d77c7b2de7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035517699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1035517699
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.389214832
Short name T351
Test name
Test status
Simulation time 5875999286 ps
CPU time 3.87 seconds
Started Mar 03 04:21:41 PM PST 24
Finished Mar 03 04:21:45 PM PST 24
Peak memory 200692 kb
Host smart-3ccb6f8b-50c2-4b8e-ba27-fd5458969820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389214832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.389214832
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.4255268700
Short name T339
Test name
Test status
Simulation time 278015327522 ps
CPU time 289.12 seconds
Started Mar 03 04:21:53 PM PST 24
Finished Mar 03 04:26:42 PM PST 24
Peak memory 209596 kb
Host smart-93d40239-058c-4683-8ff3-a49463a488e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255268700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.4255268700
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1565494737
Short name T63
Test name
Test status
Simulation time 23997476057 ps
CPU time 49.27 seconds
Started Mar 03 04:21:45 PM PST 24
Finished Mar 03 04:22:34 PM PST 24
Peak memory 201144 kb
Host smart-8ada4a7d-b4f2-4339-991e-f86863cebea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565494737 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1565494737
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1138257540
Short name T484
Test name
Test status
Simulation time 467642144 ps
CPU time 1.69 seconds
Started Mar 03 04:22:03 PM PST 24
Finished Mar 03 04:22:05 PM PST 24
Peak memory 200632 kb
Host smart-5b5e6913-fafe-4606-abae-6867f6e026f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138257540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1138257540
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3185661676
Short name T84
Test name
Test status
Simulation time 324831252189 ps
CPU time 72.36 seconds
Started Mar 03 04:21:59 PM PST 24
Finished Mar 03 04:23:11 PM PST 24
Peak memory 200892 kb
Host smart-7e1fb097-0135-484e-83b0-727139a2e566
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185661676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3185661676
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3729994831
Short name T693
Test name
Test status
Simulation time 161958320641 ps
CPU time 205.19 seconds
Started Mar 03 04:21:58 PM PST 24
Finished Mar 03 04:25:23 PM PST 24
Peak memory 200888 kb
Host smart-fc96ff4d-52ad-46ac-8775-5d45323245bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729994831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3729994831
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1123448209
Short name T752
Test name
Test status
Simulation time 166668861858 ps
CPU time 208.75 seconds
Started Mar 03 04:21:55 PM PST 24
Finished Mar 03 04:25:24 PM PST 24
Peak memory 200904 kb
Host smart-6e656534-fb1b-451c-a05c-eff8a7107569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123448209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1123448209
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3699961309
Short name T86
Test name
Test status
Simulation time 331332596555 ps
CPU time 724.42 seconds
Started Mar 03 04:21:57 PM PST 24
Finished Mar 03 04:34:01 PM PST 24
Peak memory 200960 kb
Host smart-3dad9b9f-d7e4-4d22-95ba-285c73145c21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699961309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3699961309
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.657639200
Short name T425
Test name
Test status
Simulation time 493443993055 ps
CPU time 666.07 seconds
Started Mar 03 04:21:52 PM PST 24
Finished Mar 03 04:32:59 PM PST 24
Peak memory 200892 kb
Host smart-b8a2136c-14fc-48bc-af7e-9a7be190254a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657639200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.657639200
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.235578711
Short name T687
Test name
Test status
Simulation time 493019442998 ps
CPU time 310.05 seconds
Started Mar 03 04:21:52 PM PST 24
Finished Mar 03 04:27:03 PM PST 24
Peak memory 200908 kb
Host smart-ee53fd6c-ab00-4d92-9566-9ecbf1cc4965
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=235578711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.235578711
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.908623252
Short name T155
Test name
Test status
Simulation time 161526919615 ps
CPU time 101.79 seconds
Started Mar 03 04:21:52 PM PST 24
Finished Mar 03 04:23:34 PM PST 24
Peak memory 200864 kb
Host smart-d4751af7-0d64-4ce3-aca0-d3426f7d9676
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908623252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.908623252
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3612703763
Short name T392
Test name
Test status
Simulation time 495578811721 ps
CPU time 202.26 seconds
Started Mar 03 04:21:56 PM PST 24
Finished Mar 03 04:25:18 PM PST 24
Peak memory 200888 kb
Host smart-d42dd48a-553e-41b3-90be-db59cd2335b9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612703763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3612703763
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2560487289
Short name T344
Test name
Test status
Simulation time 109168246747 ps
CPU time 626.18 seconds
Started Mar 03 04:21:55 PM PST 24
Finished Mar 03 04:32:22 PM PST 24
Peak memory 201400 kb
Host smart-ed84eae5-3aac-4211-90b3-51484f8af76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560487289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2560487289
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2994339483
Short name T406
Test name
Test status
Simulation time 35235054010 ps
CPU time 21.84 seconds
Started Mar 03 04:21:55 PM PST 24
Finished Mar 03 04:22:18 PM PST 24
Peak memory 200764 kb
Host smart-dfe56190-daf3-473e-967c-29082f604b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994339483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2994339483
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.872975669
Short name T552
Test name
Test status
Simulation time 3532202279 ps
CPU time 8.91 seconds
Started Mar 03 04:21:57 PM PST 24
Finished Mar 03 04:22:06 PM PST 24
Peak memory 200768 kb
Host smart-298e847e-a672-46a3-83e9-be8eb8d45870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872975669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.872975669
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3528834546
Short name T189
Test name
Test status
Simulation time 5722312663 ps
CPU time 8.09 seconds
Started Mar 03 04:21:55 PM PST 24
Finished Mar 03 04:22:04 PM PST 24
Peak memory 200644 kb
Host smart-6518fc32-a6ab-4935-a8eb-20920df57361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528834546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3528834546
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2972706647
Short name T332
Test name
Test status
Simulation time 194809574009 ps
CPU time 74.08 seconds
Started Mar 03 04:22:03 PM PST 24
Finished Mar 03 04:23:17 PM PST 24
Peak memory 200964 kb
Host smart-b0ee92c1-1171-4740-99b6-e9c67c79bc63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972706647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2972706647
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.631526646
Short name T174
Test name
Test status
Simulation time 331255804701 ps
CPU time 323.93 seconds
Started Mar 03 04:22:04 PM PST 24
Finished Mar 03 04:27:28 PM PST 24
Peak memory 209688 kb
Host smart-f3b5380e-9553-494c-ba39-4a01624dea75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631526646 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.631526646
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1690338277
Short name T658
Test name
Test status
Simulation time 414751312 ps
CPU time 1.1 seconds
Started Mar 03 04:16:20 PM PST 24
Finished Mar 03 04:16:22 PM PST 24
Peak memory 200688 kb
Host smart-e3c57842-3e6b-4157-9a01-11aad0929107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690338277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1690338277
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.707255250
Short name T55
Test name
Test status
Simulation time 490853720044 ps
CPU time 1134.25 seconds
Started Mar 03 04:16:14 PM PST 24
Finished Mar 03 04:35:08 PM PST 24
Peak memory 200940 kb
Host smart-b0333a01-21fb-4a5b-86c3-dedf79ae6e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707255250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.707255250
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4264608764
Short name T319
Test name
Test status
Simulation time 336009466430 ps
CPU time 673.55 seconds
Started Mar 03 04:16:14 PM PST 24
Finished Mar 03 04:27:28 PM PST 24
Peak memory 200852 kb
Host smart-d1f0a75e-e389-4ffe-a816-5b4d05f96b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264608764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4264608764
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.449745723
Short name T377
Test name
Test status
Simulation time 327884516606 ps
CPU time 729.58 seconds
Started Mar 03 04:16:13 PM PST 24
Finished Mar 03 04:28:23 PM PST 24
Peak memory 200940 kb
Host smart-2ea04fd4-a56b-4fd0-b03a-bfe63259d16c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=449745723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.449745723
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.2395722391
Short name T684
Test name
Test status
Simulation time 490732847236 ps
CPU time 269.6 seconds
Started Mar 03 04:16:07 PM PST 24
Finished Mar 03 04:20:37 PM PST 24
Peak memory 200904 kb
Host smart-1199cda8-6de2-4880-bfc2-3f5d6cf7e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395722391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.2395722391
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.935318422
Short name T369
Test name
Test status
Simulation time 482888570112 ps
CPU time 498.69 seconds
Started Mar 03 04:16:09 PM PST 24
Finished Mar 03 04:24:28 PM PST 24
Peak memory 200880 kb
Host smart-9ef63b35-d85c-404e-9c4c-3beb441ead0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=935318422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.935318422
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.2122964895
Short name T779
Test name
Test status
Simulation time 165414638957 ps
CPU time 101.07 seconds
Started Mar 03 04:16:13 PM PST 24
Finished Mar 03 04:17:54 PM PST 24
Peak memory 200964 kb
Host smart-52e61030-64da-4157-850d-f428801b4108
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122964895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.2122964895
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.1880761667
Short name T411
Test name
Test status
Simulation time 487347786325 ps
CPU time 1071.52 seconds
Started Mar 03 04:16:13 PM PST 24
Finished Mar 03 04:34:05 PM PST 24
Peak memory 200908 kb
Host smart-b6f000ad-3190-4e7b-8022-66e92bac334c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880761667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.1880761667
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2556666326
Short name T564
Test name
Test status
Simulation time 89706764820 ps
CPU time 466.84 seconds
Started Mar 03 04:16:14 PM PST 24
Finished Mar 03 04:24:01 PM PST 24
Peak memory 201336 kb
Host smart-6ad7bfc8-d158-42ea-950a-8345e3ab7bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556666326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2556666326
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1402713756
Short name T753
Test name
Test status
Simulation time 35197429604 ps
CPU time 36.66 seconds
Started Mar 03 04:16:15 PM PST 24
Finished Mar 03 04:16:51 PM PST 24
Peak memory 200768 kb
Host smart-2c4aab5b-7533-4479-b6fd-d1200e4d8834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402713756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1402713756
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.742051172
Short name T775
Test name
Test status
Simulation time 4979513987 ps
CPU time 3.73 seconds
Started Mar 03 04:16:13 PM PST 24
Finished Mar 03 04:16:17 PM PST 24
Peak memory 200732 kb
Host smart-b740ce08-9701-49a4-a6b1-3d3bc19eb96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742051172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.742051172
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.4027244798
Short name T49
Test name
Test status
Simulation time 8064572522 ps
CPU time 3.01 seconds
Started Mar 03 04:16:21 PM PST 24
Finished Mar 03 04:16:24 PM PST 24
Peak memory 217288 kb
Host smart-16e926c8-f4ee-4731-8be9-063cfbc47ef5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027244798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.4027244798
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1316263298
Short name T424
Test name
Test status
Simulation time 6018215068 ps
CPU time 8.06 seconds
Started Mar 03 04:16:09 PM PST 24
Finished Mar 03 04:16:18 PM PST 24
Peak memory 200764 kb
Host smart-26981c02-3251-4402-86d8-618609228100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316263298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1316263298
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4033184792
Short name T187
Test name
Test status
Simulation time 237221181594 ps
CPU time 145.29 seconds
Started Mar 03 04:16:20 PM PST 24
Finished Mar 03 04:18:46 PM PST 24
Peak memory 200968 kb
Host smart-82ee7f6f-1681-4ea3-8b6e-d568c1306602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033184792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4033184792
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.991834785
Short name T59
Test name
Test status
Simulation time 372387055 ps
CPU time 0.85 seconds
Started Mar 03 04:22:07 PM PST 24
Finished Mar 03 04:22:08 PM PST 24
Peak memory 200700 kb
Host smart-733aebe4-cc3a-43d2-a0a7-9c2fe0e7b435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991834785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.991834785
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1317562315
Short name T220
Test name
Test status
Simulation time 167514903338 ps
CPU time 376.77 seconds
Started Mar 03 04:22:07 PM PST 24
Finished Mar 03 04:28:24 PM PST 24
Peak memory 200884 kb
Host smart-990eba63-94b2-453b-9e41-630250df4c3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317562315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1317562315
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.4294578008
Short name T193
Test name
Test status
Simulation time 495406803771 ps
CPU time 265.78 seconds
Started Mar 03 04:22:14 PM PST 24
Finished Mar 03 04:26:40 PM PST 24
Peak memory 200916 kb
Host smart-796bfb13-86cc-4227-a8e8-c7b7012f3a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294578008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.4294578008
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3672842153
Short name T374
Test name
Test status
Simulation time 496661755514 ps
CPU time 281.24 seconds
Started Mar 03 04:22:08 PM PST 24
Finished Mar 03 04:26:50 PM PST 24
Peak memory 200872 kb
Host smart-316c7799-105c-4f38-a836-4a3201fe5777
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672842153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3672842153
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.808817522
Short name T481
Test name
Test status
Simulation time 492378790397 ps
CPU time 113.26 seconds
Started Mar 03 04:22:03 PM PST 24
Finished Mar 03 04:23:57 PM PST 24
Peak memory 200900 kb
Host smart-392c5d41-f424-4ca8-90d6-0d2831e04074
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=808817522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.808817522
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3033343700
Short name T574
Test name
Test status
Simulation time 168932878053 ps
CPU time 50.38 seconds
Started Mar 03 04:22:14 PM PST 24
Finished Mar 03 04:23:04 PM PST 24
Peak memory 200896 kb
Host smart-6de4abb2-2113-4175-8a08-60d05e7e6c76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033343700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3033343700
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2283913899
Short name T451
Test name
Test status
Simulation time 168763024023 ps
CPU time 392.72 seconds
Started Mar 03 04:22:07 PM PST 24
Finished Mar 03 04:28:40 PM PST 24
Peak memory 200904 kb
Host smart-1d693ac0-0afe-46c0-a254-430550f87942
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283913899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2283913899
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1061549927
Short name T720
Test name
Test status
Simulation time 118976635601 ps
CPU time 439.39 seconds
Started Mar 03 04:22:09 PM PST 24
Finished Mar 03 04:29:28 PM PST 24
Peak memory 201344 kb
Host smart-bfff5cfe-7333-4f20-9233-1f3fc342fb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061549927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1061549927
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3513629651
Short name T380
Test name
Test status
Simulation time 24641531795 ps
CPU time 12.23 seconds
Started Mar 03 04:22:10 PM PST 24
Finished Mar 03 04:22:22 PM PST 24
Peak memory 200748 kb
Host smart-90a140ca-7ba6-406b-b7c1-7be1d94bfdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513629651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3513629651
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1874952397
Short name T21
Test name
Test status
Simulation time 4060840486 ps
CPU time 3.31 seconds
Started Mar 03 04:22:08 PM PST 24
Finished Mar 03 04:22:11 PM PST 24
Peak memory 200772 kb
Host smart-2ec79e61-73a0-4dac-a6e6-652e065e5af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874952397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1874952397
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3557801280
Short name T668
Test name
Test status
Simulation time 5888792755 ps
CPU time 2.52 seconds
Started Mar 03 04:22:04 PM PST 24
Finished Mar 03 04:22:07 PM PST 24
Peak memory 200724 kb
Host smart-571f7751-a842-4f74-ba8a-0422dcb186d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557801280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3557801280
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1199663926
Short name T66
Test name
Test status
Simulation time 78714260040 ps
CPU time 31.5 seconds
Started Mar 03 04:22:10 PM PST 24
Finished Mar 03 04:22:41 PM PST 24
Peak memory 209284 kb
Host smart-91858364-c7e2-4dbf-a5b2-801ed7630b4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199663926 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1199663926
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1908907866
Short name T15
Test name
Test status
Simulation time 534203377 ps
CPU time 1.2 seconds
Started Mar 03 04:22:19 PM PST 24
Finished Mar 03 04:22:21 PM PST 24
Peak memory 200688 kb
Host smart-38f71787-da88-4cc5-babe-67744d4de4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908907866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1908907866
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2245462914
Short name T645
Test name
Test status
Simulation time 320926640354 ps
CPU time 768.37 seconds
Started Mar 03 04:22:20 PM PST 24
Finished Mar 03 04:35:08 PM PST 24
Peak memory 200932 kb
Host smart-b73a8db6-cf96-42ce-bc1d-9f26fd386487
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245462914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2245462914
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.147370043
Short name T195
Test name
Test status
Simulation time 168613393645 ps
CPU time 384 seconds
Started Mar 03 04:22:15 PM PST 24
Finished Mar 03 04:28:39 PM PST 24
Peak memory 200896 kb
Host smart-106aed6e-e9a3-4040-9db2-0cfd92b2f56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147370043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.147370043
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2788522572
Short name T618
Test name
Test status
Simulation time 324758655230 ps
CPU time 731.33 seconds
Started Mar 03 04:22:20 PM PST 24
Finished Mar 03 04:34:31 PM PST 24
Peak memory 200960 kb
Host smart-84090ee0-c7f1-4953-bd26-25c4998bd9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788522572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2788522572
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4118568915
Short name T691
Test name
Test status
Simulation time 494939603709 ps
CPU time 1080.03 seconds
Started Mar 03 04:22:18 PM PST 24
Finished Mar 03 04:40:19 PM PST 24
Peak memory 200884 kb
Host smart-c0929667-f4c3-4d6e-b9d1-1aecad6fd98d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118568915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.4118568915
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1834553132
Short name T391
Test name
Test status
Simulation time 168797935927 ps
CPU time 107.46 seconds
Started Mar 03 04:22:14 PM PST 24
Finished Mar 03 04:24:02 PM PST 24
Peak memory 200908 kb
Host smart-2770adc5-5e83-4367-9fb9-29e138c5c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834553132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1834553132
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1457341689
Short name T567
Test name
Test status
Simulation time 170947427928 ps
CPU time 40.87 seconds
Started Mar 03 04:22:19 PM PST 24
Finished Mar 03 04:23:00 PM PST 24
Peak memory 200944 kb
Host smart-77f35a16-867a-40e4-923d-8eef58661b5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457341689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1457341689
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1806991978
Short name T271
Test name
Test status
Simulation time 332025366818 ps
CPU time 79.57 seconds
Started Mar 03 04:22:15 PM PST 24
Finished Mar 03 04:23:34 PM PST 24
Peak memory 200904 kb
Host smart-731406cc-a79f-4fc2-8dc5-11266fb7ca1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806991978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1806991978
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3148763518
Short name T615
Test name
Test status
Simulation time 329531164521 ps
CPU time 727.72 seconds
Started Mar 03 04:22:17 PM PST 24
Finished Mar 03 04:34:25 PM PST 24
Peak memory 200872 kb
Host smart-f45d09d7-c1a3-4e3b-a92f-f2695260bc5e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148763518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3148763518
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.67059079
Short name T212
Test name
Test status
Simulation time 106169377396 ps
CPU time 404.93 seconds
Started Mar 03 04:22:20 PM PST 24
Finished Mar 03 04:29:05 PM PST 24
Peak memory 201348 kb
Host smart-3471b81e-4098-46fa-ae36-f33c0e2bc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67059079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.67059079
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1718782552
Short name T430
Test name
Test status
Simulation time 26265293017 ps
CPU time 18.72 seconds
Started Mar 03 04:22:19 PM PST 24
Finished Mar 03 04:22:38 PM PST 24
Peak memory 200736 kb
Host smart-8daf0ae0-61cb-4d55-98da-d7fbddb5b458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718782552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1718782552
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3930956752
Short name T368
Test name
Test status
Simulation time 5376534781 ps
CPU time 6.77 seconds
Started Mar 03 04:22:13 PM PST 24
Finished Mar 03 04:22:20 PM PST 24
Peak memory 200768 kb
Host smart-89e2b36f-14bb-4bb7-9b76-b812ee43e13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930956752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3930956752
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.4188794320
Short name T732
Test name
Test status
Simulation time 6006668581 ps
CPU time 7.74 seconds
Started Mar 03 04:22:09 PM PST 24
Finished Mar 03 04:22:17 PM PST 24
Peak memory 200764 kb
Host smart-930bd6ad-06f5-4fc2-b15d-277252672d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188794320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4188794320
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1265281334
Short name T299
Test name
Test status
Simulation time 561937743509 ps
CPU time 1414.07 seconds
Started Mar 03 04:22:18 PM PST 24
Finished Mar 03 04:45:52 PM PST 24
Peak memory 212396 kb
Host smart-fd9be3ae-b9ff-49b0-8369-b932867e9b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265281334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1265281334
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2623937032
Short name T433
Test name
Test status
Simulation time 496214585 ps
CPU time 0.94 seconds
Started Mar 03 04:22:30 PM PST 24
Finished Mar 03 04:22:31 PM PST 24
Peak memory 200632 kb
Host smart-902d84d4-6e2a-4607-8c33-88be986b575a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623937032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2623937032
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1138830312
Short name T267
Test name
Test status
Simulation time 329988675916 ps
CPU time 187.16 seconds
Started Mar 03 04:22:19 PM PST 24
Finished Mar 03 04:25:26 PM PST 24
Peak memory 200896 kb
Host smart-c1c739f5-acea-4588-bc3b-41a06c1de7fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138830312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1138830312
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3817857014
Short name T309
Test name
Test status
Simulation time 162439015717 ps
CPU time 384.1 seconds
Started Mar 03 04:22:23 PM PST 24
Finished Mar 03 04:28:47 PM PST 24
Peak memory 200912 kb
Host smart-514c88a1-e139-4063-a155-e80fb643c391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817857014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3817857014
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.208603812
Short name T769
Test name
Test status
Simulation time 166524055943 ps
CPU time 426.54 seconds
Started Mar 03 04:22:21 PM PST 24
Finished Mar 03 04:29:28 PM PST 24
Peak memory 201172 kb
Host smart-424fa8c0-ea71-40b9-b78f-aea60861955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208603812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.208603812
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2969033865
Short name T394
Test name
Test status
Simulation time 329368878629 ps
CPU time 775.08 seconds
Started Mar 03 04:22:19 PM PST 24
Finished Mar 03 04:35:14 PM PST 24
Peak memory 200980 kb
Host smart-2e603520-d1c2-4317-b279-17863c3dc7ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969033865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2969033865
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1571807389
Short name T758
Test name
Test status
Simulation time 326082097338 ps
CPU time 212.3 seconds
Started Mar 03 04:22:20 PM PST 24
Finished Mar 03 04:25:52 PM PST 24
Peak memory 200908 kb
Host smart-0c519d0e-d0b1-4ab6-b857-16718a2ba80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571807389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1571807389
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1326855897
Short name T545
Test name
Test status
Simulation time 163472021608 ps
CPU time 198.78 seconds
Started Mar 03 04:22:19 PM PST 24
Finished Mar 03 04:25:38 PM PST 24
Peak memory 200904 kb
Host smart-50fbe69b-3d22-416c-a604-fa54a15b77cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326855897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1326855897
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3230451274
Short name T157
Test name
Test status
Simulation time 493656435120 ps
CPU time 294.87 seconds
Started Mar 03 04:22:24 PM PST 24
Finished Mar 03 04:27:19 PM PST 24
Peak memory 200792 kb
Host smart-f31d70b7-ecd4-4c8a-be2a-599cf0a7d0c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230451274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3230451274
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3573833766
Short name T664
Test name
Test status
Simulation time 322579008062 ps
CPU time 205.56 seconds
Started Mar 03 04:22:20 PM PST 24
Finished Mar 03 04:25:46 PM PST 24
Peak memory 200892 kb
Host smart-30c854ea-5f42-45ee-9483-dbcff4e0f616
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573833766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3573833766
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1897703682
Short name T210
Test name
Test status
Simulation time 111774460954 ps
CPU time 656.03 seconds
Started Mar 03 04:22:24 PM PST 24
Finished Mar 03 04:33:20 PM PST 24
Peak memory 201332 kb
Host smart-e73d6a2c-098a-4256-a105-70528f2ed3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897703682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1897703682
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1949895602
Short name T356
Test name
Test status
Simulation time 25846475144 ps
CPU time 27.61 seconds
Started Mar 03 04:22:23 PM PST 24
Finished Mar 03 04:22:51 PM PST 24
Peak memory 200748 kb
Host smart-ce833ad3-0b7a-4cbc-9933-3b98a2d8e95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949895602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1949895602
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1915694183
Short name T186
Test name
Test status
Simulation time 3873787706 ps
CPU time 10.75 seconds
Started Mar 03 04:22:27 PM PST 24
Finished Mar 03 04:22:38 PM PST 24
Peak memory 200776 kb
Host smart-4337e656-4ae9-4ab7-99b9-0544be080268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915694183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1915694183
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2899937773
Short name T442
Test name
Test status
Simulation time 5627995047 ps
CPU time 6.96 seconds
Started Mar 03 04:22:18 PM PST 24
Finished Mar 03 04:22:25 PM PST 24
Peak memory 200748 kb
Host smart-879e423c-153e-4a33-a934-93bd72f33273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899937773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2899937773
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2812186713
Short name T623
Test name
Test status
Simulation time 334131687700 ps
CPU time 660.06 seconds
Started Mar 03 04:22:25 PM PST 24
Finished Mar 03 04:33:25 PM PST 24
Peak memory 200892 kb
Host smart-f443cee2-0580-4f34-b431-d7f9b5fb47df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812186713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2812186713
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.765275827
Short name T68
Test name
Test status
Simulation time 251553145717 ps
CPU time 164.99 seconds
Started Mar 03 04:22:23 PM PST 24
Finished Mar 03 04:25:08 PM PST 24
Peak memory 217736 kb
Host smart-ceb7135c-0f48-4b8e-b2fc-c3ce1ac0a6e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765275827 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.765275827
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.241894367
Short name T349
Test name
Test status
Simulation time 414669417 ps
CPU time 1.56 seconds
Started Mar 03 04:22:39 PM PST 24
Finished Mar 03 04:22:41 PM PST 24
Peak memory 200696 kb
Host smart-50e26a3b-b935-4b41-aa84-fff0a3527d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241894367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.241894367
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.65237945
Short name T750
Test name
Test status
Simulation time 167863796625 ps
CPU time 237.1 seconds
Started Mar 03 04:22:36 PM PST 24
Finished Mar 03 04:26:34 PM PST 24
Peak memory 200800 kb
Host smart-06b770d0-b057-438b-8872-9701bfdddb15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65237945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gatin
g.65237945
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.683473102
Short name T544
Test name
Test status
Simulation time 327615099375 ps
CPU time 536.37 seconds
Started Mar 03 04:22:36 PM PST 24
Finished Mar 03 04:31:33 PM PST 24
Peak memory 200904 kb
Host smart-02599599-c8f9-4b43-a8a5-7e4947e38ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683473102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.683473102
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1423482076
Short name T192
Test name
Test status
Simulation time 489634578896 ps
CPU time 217.6 seconds
Started Mar 03 04:22:29 PM PST 24
Finished Mar 03 04:26:07 PM PST 24
Peak memory 200968 kb
Host smart-436feacc-7228-4dfb-9633-1bf00b39845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423482076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1423482076
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2915032482
Short name T470
Test name
Test status
Simulation time 326992192213 ps
CPU time 747.63 seconds
Started Mar 03 04:22:30 PM PST 24
Finished Mar 03 04:34:58 PM PST 24
Peak memory 200900 kb
Host smart-103794fe-e971-4bc6-a6eb-5a0d1c600279
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915032482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2915032482
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2120649698
Short name T617
Test name
Test status
Simulation time 324592111561 ps
CPU time 181.91 seconds
Started Mar 03 04:22:28 PM PST 24
Finished Mar 03 04:25:30 PM PST 24
Peak memory 201156 kb
Host smart-460a44db-9a09-40d6-b167-1c2d6f8c22c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120649698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2120649698
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2303927470
Short name T386
Test name
Test status
Simulation time 160628804945 ps
CPU time 359.74 seconds
Started Mar 03 04:22:29 PM PST 24
Finished Mar 03 04:28:29 PM PST 24
Peak memory 200900 kb
Host smart-f498c7f7-4bd3-4cf2-a39a-0ca022283c0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303927470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2303927470
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.402038510
Short name T579
Test name
Test status
Simulation time 163818989236 ps
CPU time 385.43 seconds
Started Mar 03 04:22:35 PM PST 24
Finished Mar 03 04:29:00 PM PST 24
Peak memory 200788 kb
Host smart-33e9fe06-c611-44df-ae1c-be1d5ecd94cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402038510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.402038510
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2584546127
Short name T597
Test name
Test status
Simulation time 490418164256 ps
CPU time 305.84 seconds
Started Mar 03 04:22:35 PM PST 24
Finished Mar 03 04:27:42 PM PST 24
Peak memory 200972 kb
Host smart-2d1562bc-d860-446d-bb39-df94c83b1be7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584546127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2584546127
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.309765614
Short name T87
Test name
Test status
Simulation time 99421291715 ps
CPU time 421.39 seconds
Started Mar 03 04:22:42 PM PST 24
Finished Mar 03 04:29:45 PM PST 24
Peak memory 201396 kb
Host smart-425b0603-33e6-452b-883b-f960c5348a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309765614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.309765614
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1125200426
Short name T633
Test name
Test status
Simulation time 35651326634 ps
CPU time 85.58 seconds
Started Mar 03 04:22:35 PM PST 24
Finished Mar 03 04:24:01 PM PST 24
Peak memory 200760 kb
Host smart-42434b7a-dc26-47f4-8c33-651aa5bd3f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125200426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1125200426
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4049469979
Short name T489
Test name
Test status
Simulation time 3071897343 ps
CPU time 4.28 seconds
Started Mar 03 04:22:33 PM PST 24
Finished Mar 03 04:22:37 PM PST 24
Peak memory 200792 kb
Host smart-82ca9e12-9bf3-4997-98c0-9ac85cd9814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049469979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4049469979
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1675741637
Short name T494
Test name
Test status
Simulation time 5812413108 ps
CPU time 14.61 seconds
Started Mar 03 04:22:30 PM PST 24
Finished Mar 03 04:22:44 PM PST 24
Peak memory 200756 kb
Host smart-cd546f4c-93e8-482c-b29c-b2df7cb26957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675741637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1675741637
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1440317371
Short name T735
Test name
Test status
Simulation time 209696914194 ps
CPU time 484.29 seconds
Started Mar 03 04:22:40 PM PST 24
Finished Mar 03 04:30:45 PM PST 24
Peak memory 200904 kb
Host smart-5039529e-2e8d-4637-8ad3-dcf745c6622a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440317371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1440317371
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3068375187
Short name T54
Test name
Test status
Simulation time 510148548 ps
CPU time 0.79 seconds
Started Mar 03 04:22:45 PM PST 24
Finished Mar 03 04:22:47 PM PST 24
Peak memory 200664 kb
Host smart-ad839886-3f11-44da-99f4-3ed795e13b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068375187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3068375187
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.4110389703
Short name T57
Test name
Test status
Simulation time 166214158799 ps
CPU time 102.52 seconds
Started Mar 03 04:22:43 PM PST 24
Finished Mar 03 04:24:26 PM PST 24
Peak memory 200880 kb
Host smart-09b8b60e-ab6a-43ca-920f-5a2ed1f08d10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110389703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.4110389703
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.44186044
Short name T273
Test name
Test status
Simulation time 164805142466 ps
CPU time 327.1 seconds
Started Mar 03 04:22:40 PM PST 24
Finished Mar 03 04:28:08 PM PST 24
Peak memory 200956 kb
Host smart-0a74716e-1e5e-430d-ac7d-0603d8710853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44186044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.44186044
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1378009538
Short name T446
Test name
Test status
Simulation time 330734882110 ps
CPU time 395.76 seconds
Started Mar 03 04:22:40 PM PST 24
Finished Mar 03 04:29:16 PM PST 24
Peak memory 200960 kb
Host smart-ab0a726b-2173-4c60-bcf5-f90514ee5a81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378009538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1378009538
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3607346440
Short name T438
Test name
Test status
Simulation time 331472493993 ps
CPU time 750.31 seconds
Started Mar 03 04:22:41 PM PST 24
Finished Mar 03 04:35:12 PM PST 24
Peak memory 200836 kb
Host smart-7da2c09a-7279-4c96-87fd-74ffc8de6f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607346440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3607346440
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2737713219
Short name T405
Test name
Test status
Simulation time 322857471126 ps
CPU time 88.01 seconds
Started Mar 03 04:22:41 PM PST 24
Finished Mar 03 04:24:09 PM PST 24
Peak memory 200904 kb
Host smart-0e8c8f68-8211-452d-8ac1-de627e91176b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737713219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2737713219
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1968420012
Short name T557
Test name
Test status
Simulation time 163001347534 ps
CPU time 103.48 seconds
Started Mar 03 04:22:41 PM PST 24
Finished Mar 03 04:24:26 PM PST 24
Peak memory 200904 kb
Host smart-7a942dbd-2911-4d8d-b8a3-0155a9c120bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968420012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1968420012
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.1962563248
Short name T505
Test name
Test status
Simulation time 326154857190 ps
CPU time 86 seconds
Started Mar 03 04:22:41 PM PST 24
Finished Mar 03 04:24:08 PM PST 24
Peak memory 200956 kb
Host smart-858880c1-6dbc-4258-856d-35495dd750a8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962563248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.1962563248
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2233290676
Short name T546
Test name
Test status
Simulation time 71793528153 ps
CPU time 241.04 seconds
Started Mar 03 04:22:43 PM PST 24
Finished Mar 03 04:26:45 PM PST 24
Peak memory 201388 kb
Host smart-63dd023e-c512-41a2-901d-51315ae51042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233290676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2233290676
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2647987056
Short name T348
Test name
Test status
Simulation time 42616985664 ps
CPU time 91.67 seconds
Started Mar 03 04:22:44 PM PST 24
Finished Mar 03 04:24:17 PM PST 24
Peak memory 200748 kb
Host smart-64e0b53c-3492-42e0-9667-bce62045dffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647987056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2647987056
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.47378010
Short name T626
Test name
Test status
Simulation time 2776192124 ps
CPU time 3.83 seconds
Started Mar 03 04:22:43 PM PST 24
Finished Mar 03 04:22:48 PM PST 24
Peak memory 200760 kb
Host smart-acbd88fd-2c51-4466-a8d8-e129739d65fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47378010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.47378010
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2830258677
Short name T447
Test name
Test status
Simulation time 5953361107 ps
CPU time 13.69 seconds
Started Mar 03 04:22:41 PM PST 24
Finished Mar 03 04:22:55 PM PST 24
Peak memory 200648 kb
Host smart-c439c65f-ee1d-4b71-8655-92eebdc2c0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830258677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2830258677
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3664496248
Short name T330
Test name
Test status
Simulation time 106196440105 ps
CPU time 101.28 seconds
Started Mar 03 04:22:46 PM PST 24
Finished Mar 03 04:24:27 PM PST 24
Peak memory 209660 kb
Host smart-3770f0d1-dcd6-4e5d-a763-f7cc61a43d68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664496248 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3664496248
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.176417668
Short name T696
Test name
Test status
Simulation time 526631245 ps
CPU time 1.28 seconds
Started Mar 03 04:22:55 PM PST 24
Finished Mar 03 04:22:57 PM PST 24
Peak memory 200704 kb
Host smart-5fe43386-506a-4048-8dc2-45e152b4fa00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176417668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.176417668
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2728510073
Short name T161
Test name
Test status
Simulation time 320411939080 ps
CPU time 400.2 seconds
Started Mar 03 04:22:51 PM PST 24
Finished Mar 03 04:29:32 PM PST 24
Peak memory 200920 kb
Host smart-24951655-e074-4360-8bf8-242cde9b13c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728510073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2728510073
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3352676952
Short name T190
Test name
Test status
Simulation time 165758164301 ps
CPU time 365.52 seconds
Started Mar 03 04:22:50 PM PST 24
Finished Mar 03 04:28:56 PM PST 24
Peak memory 200972 kb
Host smart-2d945227-8682-421e-acba-e98a5ec5b220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352676952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3352676952
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3742573788
Short name T231
Test name
Test status
Simulation time 165281358091 ps
CPU time 398.41 seconds
Started Mar 03 04:22:52 PM PST 24
Finished Mar 03 04:29:31 PM PST 24
Peak memory 200904 kb
Host smart-e5a54b7c-1863-4c1a-b5ee-e63175fe9f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742573788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3742573788
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3502749566
Short name T429
Test name
Test status
Simulation time 161432428758 ps
CPU time 95.61 seconds
Started Mar 03 04:22:49 PM PST 24
Finished Mar 03 04:24:25 PM PST 24
Peak memory 200960 kb
Host smart-e24f79d8-75ef-46c8-8d77-d3a44d7068f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502749566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3502749566
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2194639372
Short name T159
Test name
Test status
Simulation time 501158459273 ps
CPU time 1103.71 seconds
Started Mar 03 04:22:53 PM PST 24
Finished Mar 03 04:41:17 PM PST 24
Peak memory 200908 kb
Host smart-87313e87-bdea-49d5-a426-156fc69cc35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194639372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2194639372
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2018565440
Short name T541
Test name
Test status
Simulation time 163769838223 ps
CPU time 377.24 seconds
Started Mar 03 04:22:50 PM PST 24
Finished Mar 03 04:29:08 PM PST 24
Peak memory 200900 kb
Host smart-e17e2ed0-57a0-424a-b968-2c3ebea94bbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018565440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2018565440
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3272959413
Short name T296
Test name
Test status
Simulation time 333153747292 ps
CPU time 724.84 seconds
Started Mar 03 04:22:50 PM PST 24
Finished Mar 03 04:34:55 PM PST 24
Peak memory 200960 kb
Host smart-5cf8fbf6-9505-4007-9138-02f11bd5ab77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272959413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3272959413
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2988329125
Short name T731
Test name
Test status
Simulation time 496639152752 ps
CPU time 85.22 seconds
Started Mar 03 04:22:50 PM PST 24
Finished Mar 03 04:24:16 PM PST 24
Peak memory 200900 kb
Host smart-f2b62d48-3a68-45bd-857b-d6afe22435c1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988329125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2988329125
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.3216910544
Short name T741
Test name
Test status
Simulation time 126733472585 ps
CPU time 418.16 seconds
Started Mar 03 04:22:55 PM PST 24
Finished Mar 03 04:29:54 PM PST 24
Peak memory 201340 kb
Host smart-c6971470-8393-42e3-8096-13d16f4b8384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216910544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.3216910544
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3677020097
Short name T606
Test name
Test status
Simulation time 24535494390 ps
CPU time 14.38 seconds
Started Mar 03 04:22:54 PM PST 24
Finished Mar 03 04:23:08 PM PST 24
Peak memory 200752 kb
Host smart-2b96f2b8-ecb4-4d95-aa6d-5f0b8e82294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677020097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3677020097
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.818595372
Short name T500
Test name
Test status
Simulation time 4174797282 ps
CPU time 5.96 seconds
Started Mar 03 04:22:55 PM PST 24
Finished Mar 03 04:23:02 PM PST 24
Peak memory 200772 kb
Host smart-907a2673-4b24-42a2-a402-6fcdde04bfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818595372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.818595372
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.417450563
Short name T690
Test name
Test status
Simulation time 5734077989 ps
CPU time 2.18 seconds
Started Mar 03 04:22:46 PM PST 24
Finished Mar 03 04:22:48 PM PST 24
Peak memory 200716 kb
Host smart-19d929ee-32fc-40f4-b16f-74441415dd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417450563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.417450563
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2493335193
Short name T132
Test name
Test status
Simulation time 1454750708 ps
CPU time 1.21 seconds
Started Mar 03 04:22:57 PM PST 24
Finished Mar 03 04:22:58 PM PST 24
Peak memory 200692 kb
Host smart-8cb1d3ff-0005-4124-9262-ff5aa33624d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493335193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2493335193
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2249268303
Short name T554
Test name
Test status
Simulation time 300343956 ps
CPU time 0.85 seconds
Started Mar 03 04:23:07 PM PST 24
Finished Mar 03 04:23:08 PM PST 24
Peak memory 200708 kb
Host smart-9deb3dc8-3789-4e0b-b1ea-c95767580309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249268303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2249268303
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3200985308
Short name T226
Test name
Test status
Simulation time 325709244133 ps
CPU time 403.9 seconds
Started Mar 03 04:22:59 PM PST 24
Finished Mar 03 04:29:43 PM PST 24
Peak memory 200864 kb
Host smart-5cf150f0-154f-44d0-8cfd-5131510c632f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200985308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3200985308
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2353893962
Short name T261
Test name
Test status
Simulation time 332764535219 ps
CPU time 808.48 seconds
Started Mar 03 04:23:01 PM PST 24
Finished Mar 03 04:36:30 PM PST 24
Peak memory 200932 kb
Host smart-a4f694a0-1d3f-47fe-b234-d07793110777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353893962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2353893962
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.376177810
Short name T614
Test name
Test status
Simulation time 335532188577 ps
CPU time 800.6 seconds
Started Mar 03 04:23:00 PM PST 24
Finished Mar 03 04:36:21 PM PST 24
Peak memory 200912 kb
Host smart-fc665f69-3bc6-4fe3-8147-78e17414db4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376177810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.376177810
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3169003188
Short name T501
Test name
Test status
Simulation time 496572166690 ps
CPU time 1166.16 seconds
Started Mar 03 04:22:59 PM PST 24
Finished Mar 03 04:42:25 PM PST 24
Peak memory 200884 kb
Host smart-8d95e296-61dd-410e-9f0d-683853358c8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169003188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3169003188
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.499306119
Short name T148
Test name
Test status
Simulation time 484644799228 ps
CPU time 582.39 seconds
Started Mar 03 04:22:55 PM PST 24
Finished Mar 03 04:32:38 PM PST 24
Peak memory 200968 kb
Host smart-5778efb2-cd72-4073-9268-3b3759b57b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499306119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.499306119
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.540510864
Short name T160
Test name
Test status
Simulation time 484405879808 ps
CPU time 281.17 seconds
Started Mar 03 04:22:56 PM PST 24
Finished Mar 03 04:27:37 PM PST 24
Peak memory 200888 kb
Host smart-fcca317e-0d1a-448b-8507-fcf1fa898ed3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=540510864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.540510864
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.718006394
Short name T320
Test name
Test status
Simulation time 494892631076 ps
CPU time 952.92 seconds
Started Mar 03 04:22:58 PM PST 24
Finished Mar 03 04:38:51 PM PST 24
Peak memory 200872 kb
Host smart-1acb729d-103b-4824-80b5-2f7561db43ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718006394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.718006394
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3950927519
Short name T421
Test name
Test status
Simulation time 333204855173 ps
CPU time 755.19 seconds
Started Mar 03 04:22:58 PM PST 24
Finished Mar 03 04:35:33 PM PST 24
Peak memory 200896 kb
Host smart-614dd50d-6c83-4332-864e-0defa3a37c43
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950927519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3950927519
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3225617379
Short name T416
Test name
Test status
Simulation time 27201513944 ps
CPU time 14.69 seconds
Started Mar 03 04:23:06 PM PST 24
Finished Mar 03 04:23:22 PM PST 24
Peak memory 200748 kb
Host smart-472879d5-cc81-49d1-9d18-5929dc81328f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225617379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3225617379
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3484356409
Short name T507
Test name
Test status
Simulation time 5064539768 ps
CPU time 2.99 seconds
Started Mar 03 04:23:00 PM PST 24
Finished Mar 03 04:23:03 PM PST 24
Peak memory 200708 kb
Host smart-8a34f0ff-6a55-48db-bb5a-ecd3e096415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484356409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3484356409
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.3309809276
Short name T555
Test name
Test status
Simulation time 5890909929 ps
CPU time 3.57 seconds
Started Mar 03 04:22:54 PM PST 24
Finished Mar 03 04:22:58 PM PST 24
Peak memory 200752 kb
Host smart-5813baea-4e67-49c7-9d6f-63a3a87daa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309809276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.3309809276
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.894263889
Short name T89
Test name
Test status
Simulation time 164343974110 ps
CPU time 391.83 seconds
Started Mar 03 04:23:03 PM PST 24
Finished Mar 03 04:29:35 PM PST 24
Peak memory 200904 kb
Host smart-564e58af-ba8b-40eb-8777-a1653ca85db8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894263889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
894263889
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3166174116
Short name T759
Test name
Test status
Simulation time 612714381 ps
CPU time 0.73 seconds
Started Mar 03 04:23:10 PM PST 24
Finished Mar 03 04:23:11 PM PST 24
Peak memory 200684 kb
Host smart-18c58d44-6374-4a2f-a2cd-bc3ce11bd7a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166174116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3166174116
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3602196709
Short name T730
Test name
Test status
Simulation time 493096678180 ps
CPU time 1019.74 seconds
Started Mar 03 04:23:11 PM PST 24
Finished Mar 03 04:40:11 PM PST 24
Peak memory 200944 kb
Host smart-f7d9c6b3-d626-41c0-b74b-6a75a5042d50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602196709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3602196709
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1614267247
Short name T230
Test name
Test status
Simulation time 334428113920 ps
CPU time 787.62 seconds
Started Mar 03 04:23:10 PM PST 24
Finished Mar 03 04:36:18 PM PST 24
Peak memory 200924 kb
Host smart-0d77b0a1-726a-4d67-b52e-cbc644bea7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614267247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1614267247
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1952246496
Short name T625
Test name
Test status
Simulation time 165242805796 ps
CPU time 97.09 seconds
Started Mar 03 04:23:11 PM PST 24
Finished Mar 03 04:24:48 PM PST 24
Peak memory 200876 kb
Host smart-6c16f7ea-7462-4265-9f33-ee4a24004eb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952246496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1952246496
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3943041779
Short name T62
Test name
Test status
Simulation time 167299337874 ps
CPU time 181.92 seconds
Started Mar 03 04:23:11 PM PST 24
Finished Mar 03 04:26:14 PM PST 24
Peak memory 200828 kb
Host smart-bb079574-03a0-4745-985a-79a91a6d1206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943041779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3943041779
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1495432056
Short name T75
Test name
Test status
Simulation time 480607161638 ps
CPU time 253.26 seconds
Started Mar 03 04:23:10 PM PST 24
Finished Mar 03 04:27:24 PM PST 24
Peak memory 200956 kb
Host smart-40c9a047-a272-4f78-9df3-352ea76f71a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495432056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1495432056
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1500296980
Short name T302
Test name
Test status
Simulation time 500161625965 ps
CPU time 1166.31 seconds
Started Mar 03 04:23:11 PM PST 24
Finished Mar 03 04:42:38 PM PST 24
Peak memory 200976 kb
Host smart-e4f1d945-5aef-43a8-a574-27d13abb49ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500296980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1500296980
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1206628611
Short name T593
Test name
Test status
Simulation time 166334160795 ps
CPU time 88.28 seconds
Started Mar 03 04:23:11 PM PST 24
Finished Mar 03 04:24:39 PM PST 24
Peak memory 200900 kb
Host smart-c55e088c-f73c-4ff7-9bf0-946a661bc7af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206628611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1206628611
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.708078148
Short name T90
Test name
Test status
Simulation time 127331236179 ps
CPU time 517.44 seconds
Started Mar 03 04:23:10 PM PST 24
Finished Mar 03 04:31:48 PM PST 24
Peak memory 201332 kb
Host smart-5e1ad8da-a800-4019-8b81-e8c033f626c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708078148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.708078148
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3931266433
Short name T596
Test name
Test status
Simulation time 22273402744 ps
CPU time 25.17 seconds
Started Mar 03 04:23:11 PM PST 24
Finished Mar 03 04:23:37 PM PST 24
Peak memory 200752 kb
Host smart-7d01588f-1abe-4aae-8935-2201409ec7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931266433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3931266433
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.682267243
Short name T491
Test name
Test status
Simulation time 3117594830 ps
CPU time 1.9 seconds
Started Mar 03 04:23:12 PM PST 24
Finished Mar 03 04:23:14 PM PST 24
Peak memory 200776 kb
Host smart-db50351d-20dd-4c75-9cba-51a2d56cc5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682267243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.682267243
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4048169741
Short name T569
Test name
Test status
Simulation time 5982800735 ps
CPU time 15.71 seconds
Started Mar 03 04:23:10 PM PST 24
Finished Mar 03 04:23:26 PM PST 24
Peak memory 200756 kb
Host smart-b4c75620-b3bb-448b-9378-3626e7d6a00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048169741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4048169741
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2735437202
Short name T636
Test name
Test status
Simulation time 493320446518 ps
CPU time 91.42 seconds
Started Mar 03 04:23:11 PM PST 24
Finished Mar 03 04:24:43 PM PST 24
Peak memory 200940 kb
Host smart-89d504c4-d16b-4299-a3d4-4cbe0de7f24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735437202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2735437202
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1864535497
Short name T363
Test name
Test status
Simulation time 364295713 ps
CPU time 1.43 seconds
Started Mar 03 04:23:28 PM PST 24
Finished Mar 03 04:23:29 PM PST 24
Peak memory 200744 kb
Host smart-c11ef0be-8651-464c-a17f-5e0a83180921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864535497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1864535497
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2749366573
Short name T252
Test name
Test status
Simulation time 159872485930 ps
CPU time 33.35 seconds
Started Mar 03 04:23:22 PM PST 24
Finished Mar 03 04:23:55 PM PST 24
Peak memory 200968 kb
Host smart-e5076b68-0e49-47d9-8557-683f7b434e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749366573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2749366573
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3227009097
Short name T771
Test name
Test status
Simulation time 158533068600 ps
CPU time 192.2 seconds
Started Mar 03 04:23:16 PM PST 24
Finished Mar 03 04:26:28 PM PST 24
Peak memory 200912 kb
Host smart-e90f78df-a770-4c30-8311-97a3a2f345a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227009097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3227009097
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.978532916
Short name T408
Test name
Test status
Simulation time 165848474645 ps
CPU time 90.94 seconds
Started Mar 03 04:23:15 PM PST 24
Finished Mar 03 04:24:46 PM PST 24
Peak memory 200968 kb
Host smart-34d76b57-efbc-4552-b7a5-a15cd1d1d4ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=978532916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.978532916
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2908913707
Short name T508
Test name
Test status
Simulation time 162896648870 ps
CPU time 97.88 seconds
Started Mar 03 04:23:15 PM PST 24
Finished Mar 03 04:24:53 PM PST 24
Peak memory 200968 kb
Host smart-50b1cd88-b5e4-4036-9821-a1642a48d8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908913707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2908913707
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2687933739
Short name T426
Test name
Test status
Simulation time 163960405180 ps
CPU time 362.84 seconds
Started Mar 03 04:23:16 PM PST 24
Finished Mar 03 04:29:19 PM PST 24
Peak memory 200956 kb
Host smart-ac5782d8-0704-442c-a6e1-6aa29fd51020
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687933739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2687933739
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2354312681
Short name T642
Test name
Test status
Simulation time 165734562981 ps
CPU time 262.25 seconds
Started Mar 03 04:23:16 PM PST 24
Finished Mar 03 04:27:38 PM PST 24
Peak memory 200928 kb
Host smart-3b182efa-143a-4bd2-9cd1-b8cb8f679795
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354312681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2354312681
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1107338034
Short name T469
Test name
Test status
Simulation time 130817011218 ps
CPU time 483.68 seconds
Started Mar 03 04:23:21 PM PST 24
Finished Mar 03 04:31:25 PM PST 24
Peak memory 201400 kb
Host smart-acd15714-b0e1-42af-a8d8-f6edf620996c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107338034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1107338034
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.111785452
Short name T765
Test name
Test status
Simulation time 31192329578 ps
CPU time 10.99 seconds
Started Mar 03 04:23:28 PM PST 24
Finished Mar 03 04:23:39 PM PST 24
Peak memory 200804 kb
Host smart-d23b4893-bff6-4b2b-a63a-3fc943e037c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111785452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.111785452
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1502975246
Short name T96
Test name
Test status
Simulation time 4600786892 ps
CPU time 3.04 seconds
Started Mar 03 04:23:21 PM PST 24
Finished Mar 03 04:23:24 PM PST 24
Peak memory 200708 kb
Host smart-540a84fc-99a5-4350-9d3b-1450e9ca37c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502975246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1502975246
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1239164292
Short name T2
Test name
Test status
Simulation time 6083187373 ps
CPU time 4.67 seconds
Started Mar 03 04:23:16 PM PST 24
Finished Mar 03 04:23:20 PM PST 24
Peak memory 200716 kb
Host smart-088e012b-c081-4034-8939-4ff412104572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239164292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1239164292
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1782996078
Short name T716
Test name
Test status
Simulation time 496824474 ps
CPU time 1.81 seconds
Started Mar 03 04:23:31 PM PST 24
Finished Mar 03 04:23:33 PM PST 24
Peak memory 200908 kb
Host smart-299c779c-14b4-4504-a686-0e63a14d7aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782996078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1782996078
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.547284678
Short name T682
Test name
Test status
Simulation time 329134394618 ps
CPU time 409.51 seconds
Started Mar 03 04:23:27 PM PST 24
Finished Mar 03 04:30:16 PM PST 24
Peak memory 200908 kb
Host smart-f32bd2eb-b047-4482-8175-acff0897b17b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547284678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gati
ng.547284678
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3100487648
Short name T333
Test name
Test status
Simulation time 157943165713 ps
CPU time 72.37 seconds
Started Mar 03 04:23:27 PM PST 24
Finished Mar 03 04:24:40 PM PST 24
Peak memory 201008 kb
Host smart-b0a53fc5-ac72-4207-a232-e29a33ab5cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100487648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3100487648
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1103970893
Short name T158
Test name
Test status
Simulation time 166132917112 ps
CPU time 56.8 seconds
Started Mar 03 04:23:22 PM PST 24
Finished Mar 03 04:24:19 PM PST 24
Peak memory 200904 kb
Host smart-b826c792-697b-4862-987e-edc8aafc73ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103970893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1103970893
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3172164728
Short name T613
Test name
Test status
Simulation time 493421374938 ps
CPU time 1167.09 seconds
Started Mar 03 04:23:28 PM PST 24
Finished Mar 03 04:42:55 PM PST 24
Peak memory 201016 kb
Host smart-46d11e63-8f78-402b-95a5-e7d9e38bf025
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172164728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3172164728
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3373390682
Short name T700
Test name
Test status
Simulation time 153754171012 ps
CPU time 106.31 seconds
Started Mar 03 04:23:21 PM PST 24
Finished Mar 03 04:25:08 PM PST 24
Peak memory 200840 kb
Host smart-8e13174f-83fb-42dc-ae98-06d6c367041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373390682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3373390682
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1251891035
Short name T474
Test name
Test status
Simulation time 165683374254 ps
CPU time 232.82 seconds
Started Mar 03 04:23:21 PM PST 24
Finished Mar 03 04:27:14 PM PST 24
Peak memory 200908 kb
Host smart-7f0887f4-4f2e-41fb-babb-a27bb483bbdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251891035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1251891035
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2142081138
Short name T101
Test name
Test status
Simulation time 332850927359 ps
CPU time 181.46 seconds
Started Mar 03 04:23:26 PM PST 24
Finished Mar 03 04:26:28 PM PST 24
Peak memory 200904 kb
Host smart-742b787b-3f4c-4925-9732-4384a39c4b9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142081138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2142081138
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.128682501
Short name T698
Test name
Test status
Simulation time 492394026540 ps
CPU time 1170.27 seconds
Started Mar 03 04:23:27 PM PST 24
Finished Mar 03 04:42:57 PM PST 24
Peak memory 200896 kb
Host smart-45593b2a-c597-4b17-aa16-c0cfd3fa96a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128682501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.128682501
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3320677319
Short name T213
Test name
Test status
Simulation time 111962291811 ps
CPU time 371 seconds
Started Mar 03 04:23:27 PM PST 24
Finished Mar 03 04:29:38 PM PST 24
Peak memory 201440 kb
Host smart-594b60fa-8e41-4c77-b2ba-1dad9b823ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320677319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3320677319
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1362177381
Short name T375
Test name
Test status
Simulation time 42368654843 ps
CPU time 49.62 seconds
Started Mar 03 04:23:26 PM PST 24
Finished Mar 03 04:24:16 PM PST 24
Peak memory 200752 kb
Host smart-b8c25660-9e58-4aa3-a038-40bfd58fa2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362177381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1362177381
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3045167845
Short name T364
Test name
Test status
Simulation time 3165385083 ps
CPU time 1.8 seconds
Started Mar 03 04:23:25 PM PST 24
Finished Mar 03 04:23:27 PM PST 24
Peak memory 200772 kb
Host smart-d3f5ba66-262e-4ca6-b390-fe3d8d27048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045167845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3045167845
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1616575994
Short name T711
Test name
Test status
Simulation time 5635364469 ps
CPU time 6.84 seconds
Started Mar 03 04:23:21 PM PST 24
Finished Mar 03 04:23:28 PM PST 24
Peak memory 200760 kb
Host smart-d0296272-e261-4b17-9123-22ab84210d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616575994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1616575994
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.4219769459
Short name T785
Test name
Test status
Simulation time 337387325073 ps
CPU time 223.56 seconds
Started Mar 03 04:23:33 PM PST 24
Finished Mar 03 04:27:17 PM PST 24
Peak memory 201016 kb
Host smart-822ba492-7362-479b-879c-6ae012dd1583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219769459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.4219769459
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.321733637
Short name T314
Test name
Test status
Simulation time 416308818722 ps
CPU time 730.94 seconds
Started Mar 03 04:23:32 PM PST 24
Finished Mar 03 04:35:43 PM PST 24
Peak memory 209672 kb
Host smart-23c9d1af-9a09-4748-b7ff-c4e907f110dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321733637 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.321733637
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.716609151
Short name T600
Test name
Test status
Simulation time 323484909 ps
CPU time 1.37 seconds
Started Mar 03 04:16:38 PM PST 24
Finished Mar 03 04:16:39 PM PST 24
Peak memory 200680 kb
Host smart-d3d14929-6c93-4597-ba2a-892ce7a8edbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716609151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.716609151
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2820219679
Short name T38
Test name
Test status
Simulation time 162600597235 ps
CPU time 353.9 seconds
Started Mar 03 04:16:34 PM PST 24
Finished Mar 03 04:22:28 PM PST 24
Peak memory 200892 kb
Host smart-5d23bde0-e013-4b9a-8d3e-f663b4fd5d6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820219679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2820219679
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2829569394
Short name T181
Test name
Test status
Simulation time 165234722996 ps
CPU time 98.72 seconds
Started Mar 03 04:16:35 PM PST 24
Finished Mar 03 04:18:13 PM PST 24
Peak memory 200948 kb
Host smart-cebf723d-f98d-429d-b959-327590dcc85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829569394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2829569394
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.4219366716
Short name T200
Test name
Test status
Simulation time 484994956433 ps
CPU time 1153.83 seconds
Started Mar 03 04:16:29 PM PST 24
Finished Mar 03 04:35:43 PM PST 24
Peak memory 200900 kb
Host smart-1601787d-bb49-40d6-ac15-10f2d9e3d73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219366716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.4219366716
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3345198357
Short name T251
Test name
Test status
Simulation time 162475883483 ps
CPU time 47.53 seconds
Started Mar 03 04:16:29 PM PST 24
Finished Mar 03 04:17:16 PM PST 24
Peak memory 200892 kb
Host smart-6532128e-533c-4ee7-a623-a55c79c57092
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345198357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3345198357
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.7492092
Short name T457
Test name
Test status
Simulation time 494169383427 ps
CPU time 1045.93 seconds
Started Mar 03 04:16:29 PM PST 24
Finished Mar 03 04:33:56 PM PST 24
Peak memory 200856 kb
Host smart-7932376a-f0ee-440e-8339-459abed810c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7492092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.7492092
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1179767210
Short name T399
Test name
Test status
Simulation time 480848471971 ps
CPU time 1068.08 seconds
Started Mar 03 04:16:29 PM PST 24
Finished Mar 03 04:34:18 PM PST 24
Peak memory 200992 kb
Host smart-39d72eeb-409e-40fa-a840-1625074c044d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179767210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1179767210
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.929052078
Short name T300
Test name
Test status
Simulation time 164320921109 ps
CPU time 403.66 seconds
Started Mar 03 04:16:34 PM PST 24
Finished Mar 03 04:23:18 PM PST 24
Peak memory 200856 kb
Host smart-44439453-fd4b-481a-8b64-e0626699594a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929052078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.929052078
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2191191379
Short name T370
Test name
Test status
Simulation time 333943533945 ps
CPU time 688.42 seconds
Started Mar 03 04:16:34 PM PST 24
Finished Mar 03 04:28:03 PM PST 24
Peak memory 200888 kb
Host smart-adcd616d-6d0b-48d8-b6c5-feca238372df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191191379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2191191379
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2847436895
Short name T605
Test name
Test status
Simulation time 77094361875 ps
CPU time 297.49 seconds
Started Mar 03 04:16:35 PM PST 24
Finished Mar 03 04:21:32 PM PST 24
Peak memory 201340 kb
Host smart-26aa1fd6-8d80-44c9-8922-ab01404c50f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847436895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2847436895
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2496496590
Short name T440
Test name
Test status
Simulation time 32541393702 ps
CPU time 79.27 seconds
Started Mar 03 04:16:35 PM PST 24
Finished Mar 03 04:17:55 PM PST 24
Peak memory 200768 kb
Host smart-422b90d5-9e61-4b58-aa4c-75d226a120a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496496590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2496496590
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.4274659118
Short name T387
Test name
Test status
Simulation time 5088754401 ps
CPU time 7.85 seconds
Started Mar 03 04:16:38 PM PST 24
Finished Mar 03 04:16:46 PM PST 24
Peak memory 200756 kb
Host smart-96eef282-2e54-471a-b189-82801f9f6e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274659118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.4274659118
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3911566940
Short name T585
Test name
Test status
Simulation time 6050340844 ps
CPU time 7.64 seconds
Started Mar 03 04:16:22 PM PST 24
Finished Mar 03 04:16:30 PM PST 24
Peak memory 200764 kb
Host smart-4710e9ef-8e76-4889-86a3-484cfc14a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911566940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3911566940
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1903613126
Short name T649
Test name
Test status
Simulation time 499228095493 ps
CPU time 313.64 seconds
Started Mar 03 04:16:35 PM PST 24
Finished Mar 03 04:21:49 PM PST 24
Peak memory 200828 kb
Host smart-72d66f3b-cd88-444d-bece-7e70bea02585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903613126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1903613126
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3284867601
Short name T610
Test name
Test status
Simulation time 382560171 ps
CPU time 0.97 seconds
Started Mar 03 04:16:47 PM PST 24
Finished Mar 03 04:16:48 PM PST 24
Peak memory 200676 kb
Host smart-2933286d-2299-4153-9953-ebe40e8a60ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284867601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3284867601
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1670330586
Short name T61
Test name
Test status
Simulation time 497030120786 ps
CPU time 452.87 seconds
Started Mar 03 04:16:42 PM PST 24
Finished Mar 03 04:24:16 PM PST 24
Peak memory 200844 kb
Host smart-852976a9-b973-464d-a7cf-8d3dc62ad465
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670330586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1670330586
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1987374077
Short name T248
Test name
Test status
Simulation time 339175917356 ps
CPU time 80.71 seconds
Started Mar 03 04:16:39 PM PST 24
Finished Mar 03 04:18:00 PM PST 24
Peak memory 200908 kb
Host smart-2fbcf679-7383-48ee-9efe-26e7466c35c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987374077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1987374077
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1925058495
Short name T445
Test name
Test status
Simulation time 162350050548 ps
CPU time 108.63 seconds
Started Mar 03 04:16:40 PM PST 24
Finished Mar 03 04:18:29 PM PST 24
Peak memory 200896 kb
Host smart-fa8b9f98-7250-4f73-8184-4be41a6bdae3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925058495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1925058495
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3223594911
Short name T602
Test name
Test status
Simulation time 485228359282 ps
CPU time 618.11 seconds
Started Mar 03 04:16:40 PM PST 24
Finished Mar 03 04:26:58 PM PST 24
Peak memory 200956 kb
Host smart-e45eb047-a62f-46f9-a025-dc01aa0d8fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223594911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3223594911
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3801464451
Short name T502
Test name
Test status
Simulation time 496432684668 ps
CPU time 1176.33 seconds
Started Mar 03 04:16:42 PM PST 24
Finished Mar 03 04:36:18 PM PST 24
Peak memory 201088 kb
Host smart-a64acd95-1d8b-4020-b4a6-755353d7606c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801464451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3801464451
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3367937338
Short name T695
Test name
Test status
Simulation time 165795630486 ps
CPU time 60.13 seconds
Started Mar 03 04:16:42 PM PST 24
Finished Mar 03 04:17:43 PM PST 24
Peak memory 200900 kb
Host smart-0e102ba6-d711-4adb-bb45-66afa636a036
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367937338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3367937338
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2907851445
Short name T463
Test name
Test status
Simulation time 326438925342 ps
CPU time 190.57 seconds
Started Mar 03 04:16:40 PM PST 24
Finished Mar 03 04:19:51 PM PST 24
Peak memory 200896 kb
Host smart-604df77a-64cd-4531-80b3-7681a18b7994
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907851445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2907851445
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3395336894
Short name T28
Test name
Test status
Simulation time 75412544057 ps
CPU time 414.57 seconds
Started Mar 03 04:16:46 PM PST 24
Finished Mar 03 04:23:41 PM PST 24
Peak memory 201332 kb
Host smart-186efffb-d0a4-4ad2-85bc-b93dad522124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395336894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3395336894
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2429454917
Short name T736
Test name
Test status
Simulation time 36383222207 ps
CPU time 84.31 seconds
Started Mar 03 04:16:47 PM PST 24
Finished Mar 03 04:18:12 PM PST 24
Peak memory 200768 kb
Host smart-5d8a07a4-ffbf-4850-8aed-5b212cff9dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429454917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2429454917
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2830470900
Short name T144
Test name
Test status
Simulation time 3608810374 ps
CPU time 2.38 seconds
Started Mar 03 04:16:45 PM PST 24
Finished Mar 03 04:16:47 PM PST 24
Peak memory 200764 kb
Host smart-8e489efb-51da-4ad7-91eb-d1c9885b0247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830470900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2830470900
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1326227630
Short name T467
Test name
Test status
Simulation time 5824944409 ps
CPU time 1.84 seconds
Started Mar 03 04:16:35 PM PST 24
Finished Mar 03 04:16:37 PM PST 24
Peak memory 200760 kb
Host smart-d2c7b558-d8bb-43a0-a7a6-cbb18df0a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326227630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1326227630
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2863843526
Short name T85
Test name
Test status
Simulation time 327081311867 ps
CPU time 179.12 seconds
Started Mar 03 04:16:46 PM PST 24
Finished Mar 03 04:19:45 PM PST 24
Peak memory 200852 kb
Host smart-eb2a9a07-5178-4de2-9604-5eb38f505778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863843526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2863843526
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1863822838
Short name T449
Test name
Test status
Simulation time 506589656 ps
CPU time 1.55 seconds
Started Mar 03 04:17:21 PM PST 24
Finished Mar 03 04:17:23 PM PST 24
Peak memory 200668 kb
Host smart-e993ccd0-2cc4-42b5-89b2-381b80bf6c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863822838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1863822838
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1642162274
Short name T298
Test name
Test status
Simulation time 332467289239 ps
CPU time 438.33 seconds
Started Mar 03 04:17:17 PM PST 24
Finished Mar 03 04:24:36 PM PST 24
Peak memory 200932 kb
Host smart-8010f7b7-f266-4ce3-ad79-35fa65960048
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642162274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1642162274
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.158607103
Short name T551
Test name
Test status
Simulation time 332387477849 ps
CPU time 806.93 seconds
Started Mar 03 04:17:19 PM PST 24
Finished Mar 03 04:30:46 PM PST 24
Peak memory 200948 kb
Host smart-f66c4e89-06ba-426f-a99c-a1d91879a5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158607103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.158607103
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3055396774
Short name T764
Test name
Test status
Simulation time 492316055264 ps
CPU time 1100.48 seconds
Started Mar 03 04:17:18 PM PST 24
Finished Mar 03 04:35:39 PM PST 24
Peak memory 201096 kb
Host smart-8b871ed7-7d97-4b4f-9311-1e58ad7e88d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055396774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3055396774
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1214483210
Short name T327
Test name
Test status
Simulation time 328606189919 ps
CPU time 793.92 seconds
Started Mar 03 04:17:17 PM PST 24
Finished Mar 03 04:30:32 PM PST 24
Peak memory 200904 kb
Host smart-369530c4-e1d6-4dd5-a21e-74ad69d0cdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214483210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1214483210
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1240669017
Short name T420
Test name
Test status
Simulation time 337078371777 ps
CPU time 749.18 seconds
Started Mar 03 04:17:18 PM PST 24
Finished Mar 03 04:29:47 PM PST 24
Peak memory 200948 kb
Host smart-7befef08-ec23-4f7d-8244-662787c492ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240669017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1240669017
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1394560167
Short name T269
Test name
Test status
Simulation time 162659311431 ps
CPU time 181.13 seconds
Started Mar 03 04:17:18 PM PST 24
Finished Mar 03 04:20:19 PM PST 24
Peak memory 200916 kb
Host smart-43ed9a75-e0ca-4071-a04d-189b593b8f58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394560167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1394560167
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1379311241
Short name T627
Test name
Test status
Simulation time 489577019028 ps
CPU time 297.48 seconds
Started Mar 03 04:17:18 PM PST 24
Finished Mar 03 04:22:15 PM PST 24
Peak memory 200900 kb
Host smart-4af74969-79e9-4ad3-bb54-0bcc886d5f1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379311241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1379311241
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.844055181
Short name T343
Test name
Test status
Simulation time 85071085804 ps
CPU time 371.78 seconds
Started Mar 03 04:17:21 PM PST 24
Finished Mar 03 04:23:33 PM PST 24
Peak memory 201380 kb
Host smart-d9007f41-09ac-4390-affb-50ec51f9dd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844055181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.844055181
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2095300208
Short name T414
Test name
Test status
Simulation time 32857065644 ps
CPU time 40.05 seconds
Started Mar 03 04:17:20 PM PST 24
Finished Mar 03 04:18:00 PM PST 24
Peak memory 200768 kb
Host smart-0a8dac06-1ab1-49b0-a520-cd54d876cdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095300208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2095300208
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.4281231716
Short name T145
Test name
Test status
Simulation time 5234775017 ps
CPU time 13.77 seconds
Started Mar 03 04:17:21 PM PST 24
Finished Mar 03 04:17:35 PM PST 24
Peak memory 200764 kb
Host smart-de633446-c8cf-4ccd-a03e-6b6032137bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281231716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.4281231716
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1788794716
Short name T490
Test name
Test status
Simulation time 5527677750 ps
CPU time 11.67 seconds
Started Mar 03 04:16:46 PM PST 24
Finished Mar 03 04:16:58 PM PST 24
Peak memory 200724 kb
Host smart-20c43312-a888-4fe7-8ddb-a9f8ef497603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788794716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1788794716
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1691957003
Short name T232
Test name
Test status
Simulation time 389685098616 ps
CPU time 662.42 seconds
Started Mar 03 04:17:20 PM PST 24
Finished Mar 03 04:28:23 PM PST 24
Peak memory 200960 kb
Host smart-77f21f2e-a2e4-44af-8ff6-c56ca1ca02f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691957003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1691957003
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3865354581
Short name T46
Test name
Test status
Simulation time 363356346 ps
CPU time 0.84 seconds
Started Mar 03 04:17:22 PM PST 24
Finished Mar 03 04:17:23 PM PST 24
Peak memory 200696 kb
Host smart-5ee72d57-db0f-4eff-8d81-e9c9a50e6aec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865354581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3865354581
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.245179015
Short name T619
Test name
Test status
Simulation time 597928369198 ps
CPU time 214.3 seconds
Started Mar 03 04:17:22 PM PST 24
Finished Mar 03 04:20:56 PM PST 24
Peak memory 200944 kb
Host smart-16f14371-e14d-4ba2-94aa-3920c57ab247
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245179015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.245179015
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1803331692
Short name T768
Test name
Test status
Simulation time 322041955784 ps
CPU time 200.7 seconds
Started Mar 03 04:17:23 PM PST 24
Finished Mar 03 04:20:44 PM PST 24
Peak memory 200960 kb
Host smart-bbdb8310-3d66-4675-a9a1-b8ae509de40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803331692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1803331692
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2952787951
Short name T225
Test name
Test status
Simulation time 492534016599 ps
CPU time 524.42 seconds
Started Mar 03 04:17:23 PM PST 24
Finished Mar 03 04:26:08 PM PST 24
Peak memory 200832 kb
Host smart-f3fa4bdf-bdc8-4bc4-9ee9-5aa0db685238
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952787951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2952787951
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1471862291
Short name T290
Test name
Test status
Simulation time 493875521490 ps
CPU time 600.16 seconds
Started Mar 03 04:17:22 PM PST 24
Finished Mar 03 04:27:22 PM PST 24
Peak memory 200936 kb
Host smart-f9ff49a9-7d0f-4263-8b03-3e0d7f75b128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471862291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1471862291
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2267813886
Short name T361
Test name
Test status
Simulation time 324656121264 ps
CPU time 152.92 seconds
Started Mar 03 04:17:21 PM PST 24
Finished Mar 03 04:19:54 PM PST 24
Peak memory 200880 kb
Host smart-fc71485f-7671-452b-9c1d-acfbd21a90d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267813886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2267813886
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4020925286
Short name T97
Test name
Test status
Simulation time 334311968469 ps
CPU time 216.1 seconds
Started Mar 03 04:17:22 PM PST 24
Finished Mar 03 04:20:58 PM PST 24
Peak memory 200976 kb
Host smart-e80bc12b-be87-4281-85af-22c1e09c646b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020925286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4020925286
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.641832523
Short name T789
Test name
Test status
Simulation time 322647972095 ps
CPU time 76.79 seconds
Started Mar 03 04:17:21 PM PST 24
Finished Mar 03 04:18:38 PM PST 24
Peak memory 200948 kb
Host smart-57b9c929-f0db-4f04-9ee4-b241d7b28ebc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641832523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.641832523
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2265564825
Short name T524
Test name
Test status
Simulation time 84421999993 ps
CPU time 293.04 seconds
Started Mar 03 04:17:24 PM PST 24
Finished Mar 03 04:22:17 PM PST 24
Peak memory 201388 kb
Host smart-8ba8abc4-3e2f-4db4-82b6-e0e8051115f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265564825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2265564825
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.454878154
Short name T471
Test name
Test status
Simulation time 38429554156 ps
CPU time 47.71 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:18:19 PM PST 24
Peak memory 200768 kb
Host smart-4a7de96a-9577-4eb2-9b42-ec6b36097b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454878154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.454878154
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3920259077
Short name T487
Test name
Test status
Simulation time 2764171551 ps
CPU time 6.85 seconds
Started Mar 03 04:17:20 PM PST 24
Finished Mar 03 04:17:27 PM PST 24
Peak memory 200768 kb
Host smart-2e3c95aa-b446-465d-a273-7642b451e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920259077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3920259077
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.193696994
Short name T540
Test name
Test status
Simulation time 5809758350 ps
CPU time 7.76 seconds
Started Mar 03 04:17:20 PM PST 24
Finished Mar 03 04:17:28 PM PST 24
Peak memory 200760 kb
Host smart-0903d777-f037-4775-b24d-2f3e052c7cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193696994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.193696994
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2792056813
Short name T30
Test name
Test status
Simulation time 295336890466 ps
CPU time 568.9 seconds
Started Mar 03 04:17:24 PM PST 24
Finished Mar 03 04:26:53 PM PST 24
Peak memory 217020 kb
Host smart-847bba8a-cef9-41d9-8d01-a3a2975059d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792056813 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2792056813
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.417087005
Short name T106
Test name
Test status
Simulation time 520981514 ps
CPU time 0.82 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:17:32 PM PST 24
Peak memory 200632 kb
Host smart-e05fd67a-3718-487d-85e8-0b9e1dd97c71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417087005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.417087005
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1835014793
Short name T616
Test name
Test status
Simulation time 162520052420 ps
CPU time 316 seconds
Started Mar 03 04:17:33 PM PST 24
Finished Mar 03 04:22:49 PM PST 24
Peak memory 200940 kb
Host smart-ed6e3042-e0bd-4ce4-a161-081f45c63f35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835014793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1835014793
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3351695646
Short name T662
Test name
Test status
Simulation time 161943540389 ps
CPU time 352.91 seconds
Started Mar 03 04:17:31 PM PST 24
Finished Mar 03 04:23:25 PM PST 24
Peak memory 200900 kb
Host smart-3304a130-32a3-4a39-a3b8-534bced83499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351695646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3351695646
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.371810452
Short name T385
Test name
Test status
Simulation time 491885818309 ps
CPU time 208.1 seconds
Started Mar 03 04:17:24 PM PST 24
Finished Mar 03 04:20:52 PM PST 24
Peak memory 200900 kb
Host smart-2d9ab802-00a0-4ac0-bad7-068a188e6165
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=371810452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.371810452
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4240912134
Short name T153
Test name
Test status
Simulation time 168866837831 ps
CPU time 191.2 seconds
Started Mar 03 04:17:32 PM PST 24
Finished Mar 03 04:20:44 PM PST 24
Peak memory 200824 kb
Host smart-d8c63dd7-b365-49fd-968a-927187066be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240912134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4240912134
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.42279400
Short name T718
Test name
Test status
Simulation time 327504447259 ps
CPU time 761.52 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:30:13 PM PST 24
Peak memory 200988 kb
Host smart-177fcacc-bed5-40de-8d5f-9865e27bac11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=42279400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed.42279400
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2514306969
Short name T583
Test name
Test status
Simulation time 160094159293 ps
CPU time 182.77 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:20:34 PM PST 24
Peak memory 200868 kb
Host smart-ac552426-95f6-4ec0-b2cb-e8696b0ac978
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514306969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2514306969
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.919655010
Short name T676
Test name
Test status
Simulation time 160978527316 ps
CPU time 354.45 seconds
Started Mar 03 04:17:33 PM PST 24
Finished Mar 03 04:23:28 PM PST 24
Peak memory 200896 kb
Host smart-38d2ea6f-8dfe-48be-a562-5f59b6aaa450
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919655010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.919655010
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3260982846
Short name T725
Test name
Test status
Simulation time 31482624410 ps
CPU time 17.17 seconds
Started Mar 03 04:17:29 PM PST 24
Finished Mar 03 04:17:47 PM PST 24
Peak memory 200780 kb
Host smart-f592678b-0699-410f-8aa0-2381c38df867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260982846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3260982846
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4052647542
Short name T634
Test name
Test status
Simulation time 5195505516 ps
CPU time 1.61 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:17:33 PM PST 24
Peak memory 200732 kb
Host smart-b3737bfd-81d2-4a12-8f00-bd73831381f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052647542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4052647542
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3572204329
Short name T111
Test name
Test status
Simulation time 5907929389 ps
CPU time 4.29 seconds
Started Mar 03 04:17:22 PM PST 24
Finished Mar 03 04:17:27 PM PST 24
Peak memory 200760 kb
Host smart-a6129ee1-11ea-497b-947f-0319b81de017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572204329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3572204329
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3397586581
Short name T766
Test name
Test status
Simulation time 173575463888 ps
CPU time 80.77 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:18:52 PM PST 24
Peak memory 200004 kb
Host smart-f56514f9-c525-4136-8192-d1f93252caa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397586581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3397586581
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1164247586
Short name T31
Test name
Test status
Simulation time 20930068966 ps
CPU time 38.29 seconds
Started Mar 03 04:17:30 PM PST 24
Finished Mar 03 04:18:10 PM PST 24
Peak memory 208892 kb
Host smart-affb9417-0d79-43d1-90e9-c4b6a05a14c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164247586 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1164247586
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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