Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6586	1			T3	58		T5	45		T15	3
testmodes[AdcCtrlTestmodeNormal]	5231	1			T3	51		T5	8		T7	3
testmodes[AdcCtrlTestmodeLowpower]	5272	1			T1	3		T2	2		T3	52
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3588	1			T3	21		T5	43		T15	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1658	1			T3	18		T5	1		T15	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1238	1			T3	19		T24	18		T29	2
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1674	1			T3	17		T5	2		T15	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1896	1			T3	15		T5	6		T10	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1315	1			T3	18		T7	2		T13	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1199	1			T3	19		T24	20		T116	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1350	1			T3	18		T7	2		T15	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2477	1			T1	2		T2	1		T3	15