Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19241

1

T1

27

T3

161

T5

55

auto[ADC_CTRL_FILTER_COND_OUT]

5287

1

T1

8

T2

22

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18874

1

T1

12

T3

161

T5

55

auto[1]

5654

1

T1

23

T2

22

T10

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	12	1			T137	12		-	-		-	-
values[0]	36	1			T56	1		T181	26		T135	1
values[1]	496	1			T1	8		T13	28		T18	12
values[2]	757	1			T7	6		T10	1		T12	1
values[3]	589	1			T1	15		T29	10		T123	1
values[4]	621	1			T7	11		T12	1		T14	13
values[5]	681	1			T7	1		T10	1		T22	2
values[6]	602	1			T8	10		T17	7		T29	12
values[7]	809	1			T13	1		T144	12		T117	12
values[8]	655	1			T15	2		T122	4		T19	20
values[9]	3065	1			T1	12		T2	22		T7	1
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	708	1			T1	8		T10	1		T13	28
values[1]	2787	1			T2	22		T7	6		T11	3
values[2]	467	1			T1	15		T7	11		T12	1
values[3]	661	1			T115	16		T132	23		T147	1
values[4]	688	1			T7	1		T8	10		T10	1
values[5]	740	1			T17	7		T29	12		T174	4
values[6]	621	1			T13	1		T122	4		T116	28
values[7]	750	1			T1	12		T7	1		T15	2
values[8]	819	1			T12	1		T14	13		T123	1
values[9]	82	1			T19	11		T198	9		T38	4
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	13		T56	1		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	8		T10	1		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	3		T12	1		T52	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1275	1			T2	22		T11	1		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T1	15		T16	6		T29	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	1		T12	1		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T200	1		T201	1		T130	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T115	16		T132	14		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	1		T8	10		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	1		T117	13		T125	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	8		T174	4		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T17	5		T25	1		T129	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	1		T122	1		T116	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T124	10		T51	1		T126	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T1	12		T7	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T15	1		T19	12		T115	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	1		T53	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	1		T123	1		T65	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T198	1		T38	3		T202	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T19	9		T203	1		T204	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	14		T128	2		T205	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T18	8		T124	9		T206	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	3		T52	2		T53	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1093	1			T11	2		T58	16		T81	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T16	9		T29	4		T207	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T7	10		T14	12		T208	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T130	14		T207	15		T209	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T132	9		T59	2		T209	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T108	15		T22	1		T120	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T125	15		T38	10		T202	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T29	4		T158	8		T53	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T17	2		T25	13		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T122	3		T116	13		T144	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T124	5		T51	1		T126	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T122	7		T132	2		T124	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T15	1		T19	8		T211	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T53	11		T165	1		T212	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T14	12		T65	9		T67	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T198	8		T38	1		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T19	2		T204	1		T213	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T137	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T56	1		T181	15		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T13	13		T199	1		T64	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	8		T13	1		T18	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	3		T12	1		T52	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	1		T25	1		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	15		T29	6		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T123	1		T148	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T16	6		T200	1		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	1		T12	1		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T7	1		T22	1		T120	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T10	1		T215	12		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	10		T29	8		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T17	5		T117	13		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	1		T144	1		T117	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T51	1		T126	13		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T122	1		T116	15		T124	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	1		T19	12		T115	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T1	12		T7	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1425	1			T2	22		T11	1		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T137	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T181	11		T216	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T13	14		T128	2		T217	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	8		T124	9		T206	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	3		T52	2		T53	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T25	14		T214	7		T158	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T29	4		T207	9		T218	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T27	12		T219	8		T208	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	9		T207	15		T220	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	10		T14	12		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T22	1		T120	20		T49	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T209	6		T202	1		T161	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T29	4		T108	15		T221	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T17	2		T25	13		T125	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T144	11		T119	12		T158	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T51	1		T126	14		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T122	3		T116	13		T124	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	1		T19	8		T124	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T122	7		T132	2		T53	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1140	1			T11	2		T14	12		T58	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	15		T56	1		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T1	1		T10	1		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	4		T12	1		T52	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1421	1			T2	2		T11	3		T58	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	1		T16	10		T29	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T7	11		T12	1		T14	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T200	1		T201	1		T130	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T115	1		T132	10		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	1		T8	1		T108	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	1		T117	1		T125	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T29	10		T174	1		T158	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T17	6		T25	14		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T13	1		T122	4		T116	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T124	6		T51	2		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T7	1		T122	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T15	2		T19	9		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	1		T53	12		T165	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T14	13		T123	1		T65	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T198	9		T38	3		T202	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T19	3		T203	1		T204	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T13	12		T64	8		T128	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	7		T18	3		T124	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	2		T52	12		T64	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	947	1			T2	20		T20	27		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	14		T16	5		T29	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T208	4		T180	7		T223	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T130	12		T224	2		T225	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T115	15		T132	13		T179	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T8	9		T120	25		T49	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T117	12		T125	14		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T29	2		T174	3		T70	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T17	1		T129	12		T179	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T116	14		T117	11		T119	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T124	9		T126	12		T64	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	11		T132	4		T124	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T19	11		T115	4		T211	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T212	14		T66	2		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T65	9		T67	11		T226	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T38	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T19	8		T227	8		T228	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T137	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T56	1		T181	12		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T13	15		T199	1		T64	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	1		T13	1		T18	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	4		T12	1		T52	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T10	1		T25	15		T214	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	1		T29	6		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T123	1		T148	1		T27	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T16	10		T200	1		T207	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	11		T12	1		T14	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	1		T22	2		T120	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	1		T215	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T29	10		T108	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T17	6		T117	1		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T13	1		T144	12		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T51	2		T126	15		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T122	4		T116	14		T124	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T15	2		T19	9		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T1	1		T7	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1487	1			T2	2		T11	3		T14	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T137	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T181	14		T216	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T13	12		T64	8		T128	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	7		T18	3		T124	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	2		T52	12		T64	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T159	11		T224	7		T152	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	14		T29	4		T59	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T219	7		T208	4		T180	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T16	5		T179	10		T220	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T115	15		T132	13		T179	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T120	25		T49	6		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T215	11		T161	4		T230	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	9		T29	2		T70	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	1		T117	12		T125	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T117	11		T174	3		T119	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T126	12		T179	11		T222	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T116	14		T124	2		T68	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T19	11		T115	4		T124	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	11		T132	4		T212	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1078	1			T2	20		T19	8		T20	27

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21202

1

T1

15

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3326

1

T1

20

T8

10

T12

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18826

1

T1

12

T3

161

T5

55

auto[1]

5702

1

T1

23

T2

22

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	30	1			T201	1		T207	6		T231	11
values[0]	29	1			T27	15		T232	5		T233	9
values[1]	667	1			T12	2		T13	1		T132	7
values[2]	767	1			T1	15		T18	12		T17	7
values[3]	619	1			T108	16		T118	1		T123	1
values[4]	528	1			T1	8		T14	13		T122	4
values[5]	611	1			T1	12		T14	13		T16	15
values[6]	569	1			T7	6		T10	2		T29	12
values[7]	828	1			T12	1		T115	5		T132	23
values[8]	529	1			T7	2		T13	1		T25	29
values[9]	3146	1			T2	22		T7	11		T8	10
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	842	1			T12	2		T13	1		T17	7
values[1]	687	1			T1	15		T18	12		T29	10
values[2]	708	1			T14	13		T118	1		T59	4
values[3]	546	1			T1	8		T122	4		T19	20
values[4]	549	1			T1	12		T14	13		T117	13
values[5]	718	1			T7	6		T10	2		T12	1
values[6]	2649	1			T2	22		T11	3		T13	1
values[7]	710	1			T7	2		T8	10		T13	27
values[8]	766	1			T7	11		T15	2		T122	8
values[9]	148	1			T117	12		T128	2		T207	6
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	1		T13	1		T132	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T12	1		T17	5		T27	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T1	15		T108	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T18	4		T29	6		T115	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T70	19		T129	3		T159	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	1		T118	1		T59	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T122	1		T16	6		T226	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	8		T19	12		T211	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T14	1		T117	13		T52	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T1	12		T120	1		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	3		T10	2		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T29	8		T116	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1382	1			T2	22		T11	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T121	6		T126	13		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	2		T25	1		T49	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T8	10		T13	13		T120	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	1		T19	9		T174	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	1		T122	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T128	1		T235	1		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T117	12		T207	1		T237	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T132	2		T124	5		T214	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T17	2		T27	7		T238	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T108	15		T66	6		T219	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T18	8		T29	4		T53	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T129	2		T217	4		T206	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	12		T180	10		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T122	3		T16	9		T205	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T19	8		T211	1		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	12		T52	2		T128	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T39	2		T240	4		T79	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	3		T22	1		T59	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T29	4		T116	13		T124	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T11	2		T58	16		T81	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T126	14		T127	9		T27	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T25	13		T49	2		T67	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	14		T120	17		T27	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	10		T19	2		T119	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	1		T122	7		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T128	1		T235	13		T236	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T207	5		T237	3		T181	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T231	1		T241	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T201	1		T207	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T232	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T27	8		T233	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T13	1		T132	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	1		T238	5		T129	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	15		T56	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T18	4		T17	5		T29	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T108	1		T123	1		T66	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T118	1		T53	1		T59	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T122	1		T52	13		T226	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	8		T14	1		T19	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	1		T16	6		T117	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	12		T211	12		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	3		T10	2		T22	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	8		T116	15		T124	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T115	5		T132	14		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T124	9		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T7	2		T13	1		T25	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T120	16		T121	6		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T2	22		T7	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T8	10		T13	13		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T231	10		T241	11		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T207	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T232	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T27	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T132	2		T124	5		T214	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T238	3		T129	12		T130	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T234	3		T128	1		T219	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T18	8		T17	2		T29	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T108	15		T66	6		T129	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T53	13		T239	7		T243	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T122	3		T52	2		T217	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T14	12		T19	8		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	12		T16	9		T128	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T211	1		T65	2		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T7	3		T22	1		T59	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T29	4		T116	13		T124	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T132	9		T158	8		T165	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T124	9		T126	14		T65	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T25	27		T49	2		T207	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T120	17		T242	3		T210	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T7	10		T11	2		T58	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T13	14		T15	1		T122	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2