Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21402

1

T1

8

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3126

1

T1

27

T7

17

T8

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19173

1

T3

161

T5

55

T6

12

auto[1]

5355

1

T1

35

T2

22

T7

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T162	13		T153	1		T299	12
values[0]	72	1			T203	1		T279	16		T300	16
values[1]	744	1			T18	12		T17	7		T25	14
values[2]	2681	1			T1	8		T2	22		T7	12
values[3]	687	1			T132	23		T56	1		T147	1
values[4]	414	1			T12	1		T124	18		T242	4
values[5]	528	1			T7	6		T13	1		T144	12
values[6]	603	1			T13	1		T117	12		T174	4
values[7]	469	1			T8	10		T15	2		T19	20
values[8]	790	1			T7	1		T10	1		T12	1
values[9]	1304	1			T1	27		T10	1		T14	26
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	928	1			T1	8		T7	12		T17	7
values[1]	2724	1			T2	22		T11	3		T12	1
values[2]	512	1			T117	13		T56	1		T147	1
values[3]	584	1			T12	1		T124	18		T49	9
values[4]	409	1			T7	6		T13	1		T144	12
values[5]	629	1			T8	10		T13	1		T19	20
values[6]	623	1			T7	1		T10	1		T12	1
values[7]	779	1			T1	12		T10	1		T14	13
values[8]	898	1			T1	15		T14	13		T122	8
values[9]	195	1			T132	7		T108	16		T158	16
minimum	16247	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T1	8		T7	1		T124	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	1		T17	5		T25	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T2	22		T11	1		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T18	4		T16	6		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T56	1		T186	1		T288	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T117	13		T147	1		T64	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T59	4		T257	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T124	9		T49	7		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	1		T120	11		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T7	3		T144	1		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T13	1		T117	12		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	10		T19	12		T174	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	1		T12	1		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T10	1		T13	13		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T212	15		T215	10		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	12		T10	1		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	1		T19	9		T29	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	15		T122	1		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T158	1		T188	4		T159	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T132	5		T108	1		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16073	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T199	1		T206	8		T271	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T124	5		T158	8		T234	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	10		T17	2		T25	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1059	1			T11	2		T58	16		T81	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T18	8		T16	9		T22	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T207	9		T241	4		T253	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T67	2		T253	5		T152	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T257	5		T208	4		T38	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T124	9		T49	2		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T120	3		T229	1		T221	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T7	3		T144	11		T128	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T52	2		T65	7		T66	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T19	8		T119	12		T59	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T234	3		T129	2		T250	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	14		T15	1		T127	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T212	13		T210	11		T284	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	12		T122	3		T29	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	12		T19	2		T29	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T122	7		T27	12		T207	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T158	15		T188	2		T231	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T132	2		T108	15		T171	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T206	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T299	1		T301	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T162	1		T153	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T300	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T203	1		T279	7		T302	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T124	10		T158	1		T128	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T18	4		T17	5		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T1	8		T2	22		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	1		T16	6		T117	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T132	14		T56	1		T126	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T147	1		T199	1		T64	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T12	1		T186	1		T257	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T124	9		T242	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T120	11		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	3		T144	1		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	1		T117	12		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T174	4		T119	10		T205	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T65	4		T131	1		T220	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T8	10		T15	1		T19	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	1		T12	1		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	1		T13	13		T29	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T14	1		T19	9		T29	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T1	27		T10	1		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T299	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T162	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T300	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T279	9		T302	14		T303	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T124	5		T158	8		T128	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T18	8		T17	2		T25	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1015	1			T11	2		T58	16		T81	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	10		T16	9		T22	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T132	9		T126	14		T207	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T65	2		T253	5		T284	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T257	5		T208	4		T38	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T124	9		T242	3		T130	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T120	3		T229	1		T296	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	3		T144	11		T49	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T52	2		T66	6		T221	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T119	12		T205	2		T130	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T65	7		T131	7		T220	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T15	1		T19	8		T59	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T234	3		T129	2		T210	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	14		T29	4		T124	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T14	12		T19	2		T29	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T14	12		T122	10		T132	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	1		T7	1		T124	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T7	11		T17	6		T25	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1387	1			T2	2		T11	3		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T18	9		T16	10		T22	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T56	1		T186	1		T288	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T117	1		T147	1		T64	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	1		T59	3		T257	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T124	10		T49	3		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	1		T120	4		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	4		T144	12		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	1		T117	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	1		T19	9		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	1		T12	1		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	1		T13	15		T15	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T212	14		T215	1		T201	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	1		T10	1		T14	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T14	13		T19	3		T29	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T1	1		T122	8		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T158	16		T188	6		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T132	3		T108	16		T56	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16219	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T199	1		T206	5		T271	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	7		T124	9		T128	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	1		T64	8		T68	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T2	20		T20	27		T115	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T18	3		T16	5		T27	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T253	2		T235	8		T266	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T117	12		T64	14		T67	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T59	1		T257	2		T179	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T124	8		T49	6		T65	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T120	10		T64	11		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T7	2		T128	2		T205	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T117	11		T52	12		T65	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	9		T19	11		T174	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T226	2		T129	2		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T13	12		T127	4		T304	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T212	14		T215	9		T159	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	11		T29	2		T124	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T19	8		T29	4		T116	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	14		T218	9		T172	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T159	4		T224	2		T225	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T132	4		T179	11		T293	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T206	7		T271	13		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T299	12		T301	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T162	13		T153	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T300	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T203	1		T279	10		T302	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T124	6		T158	9		T128	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T18	9		T17	6		T25	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T1	1		T2	2		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	11		T16	10		T117	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T132	10		T56	1		T126	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T147	1		T199	1		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T12	1		T186	1		T257	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T124	10		T242	4		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	1		T120	4		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	4		T144	12		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	1		T117	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T174	1		T119	13		T205	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T65	8		T131	8		T220	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T8	1		T15	2		T19	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	1		T12	1		T118	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	1		T13	15		T29	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	399	1			T14	13		T19	3		T29	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T1	2		T10	1		T14	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T301	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T300	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T279	6		T302	13		T303	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T124	9		T128	1		T125	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T18	3		T17	1		T64	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T1	7		T2	20		T20	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	5		T117	12		T67	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T132	13		T126	12		T161	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T64	14		T65	6		T159	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T257	2		T179	10		T208	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T124	8		T130	10		T267	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T120	10		T59	1		T64	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T7	2		T49	6		T226	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T117	11		T52	12		T66	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T174	3		T119	9		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T65	3		T220	2		T237	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T8	9		T19	11		T127	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T226	2		T129	2		T215	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	12		T29	2		T124	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T19	8		T29	4		T116	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T1	25		T132	4		T206	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2