Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19277

1

T1

27

T3

161

T5

55

auto[ADC_CTRL_FILTER_COND_OUT]

5251

1

T1

8

T2

22

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18943

1

T1

12

T3

161

T5

55

auto[1]

5585

1

T1

23

T2

22

T10

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	192	1			T19	11		T260	1		T65	20
values[0]	35	1			T181	26		T135	1		T138	1
values[1]	489	1			T1	8		T13	28		T18	12
values[2]	760	1			T7	6		T10	1		T12	1
values[3]	558	1			T1	15		T12	1		T29	10
values[4]	626	1			T7	11		T14	13		T16	15
values[5]	711	1			T7	1		T10	1		T22	2
values[6]	637	1			T8	10		T17	7		T29	12
values[7]	722	1			T13	1		T144	12		T117	12
values[8]	668	1			T15	2		T122	4		T19	20
values[9]	2925	1			T1	12		T2	22		T7	1
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	465	1			T1	8		T10	1		T13	28
values[1]	2809	1			T2	22		T7	6		T11	3
values[2]	434	1			T1	15		T7	11		T12	1
values[3]	735	1			T7	1		T14	13		T115	16
values[4]	630	1			T10	1		T108	16		T117	13
values[5]	751	1			T8	10		T17	7		T29	12
values[6]	676	1			T13	1		T122	4		T116	28
values[7]	660	1			T1	12		T7	1		T15	2
values[8]	887	1			T12	1		T14	13		T19	11
values[9]	56	1			T203	1		T202	2		T39	3
minimum	16425	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	13		T52	13		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	8		T10	1		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T7	3		T12	1		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1283	1			T2	22		T11	1		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	15		T16	6		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	1		T12	1		T29	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	1		T200	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T14	1		T115	16		T132	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T108	1		T22	1		T120	27
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	1		T117	13		T125	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	10		T29	8		T174	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T17	5		T25	1		T129	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	1		T122	1		T116	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T124	10		T51	1		T126	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	12		T7	1		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	1		T19	12		T115	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	1		T53	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T14	1		T19	9		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T202	2		T39	1		T236	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T203	1		T204	1		T79	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16103	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T206	14		T133	1		T172	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	14		T52	2		T128	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T18	8		T124	9		T244	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	3		T53	3		T189	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1105	1			T11	2		T58	16		T81	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T16	9		T207	9		T220	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T7	10		T29	4		T208	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T130	14		T207	15		T209	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	12		T132	9		T59	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T108	15		T22	1		T120	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T125	15		T202	1		T161	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T29	4		T53	13		T221	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T17	2		T25	13		T210	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T122	3		T116	13		T144	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T124	5		T51	1		T126	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T122	7		T132	2		T124	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T15	1		T19	8		T211	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T53	11		T165	1		T212	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	12		T19	2		T65	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T39	2		T236	4		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T204	1		T79	3		T213	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T206	14		T172	15		T305	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T260	1		T66	3		T39	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T19	9		T65	11		T67	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T181	15		T135	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T216	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T13	13		T56	1		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	8		T13	1		T18	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T7	3		T12	1		T52	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T25	1		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	15		T120	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T29	6		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T16	6		T200	1		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	1		T14	1		T115	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	1		T22	1		T120	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	1		T215	12		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T8	10		T29	8		T108	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T17	5		T117	13		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T13	1		T144	1		T117	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	1		T126	13		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T122	1		T116	15		T124	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T15	1		T19	12		T115	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T1	12		T7	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1356	1			T2	22		T11	1		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T66	6		T39	2		T306	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T19	2		T65	9		T67	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T181	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T216	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T13	14		T128	2		T217	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T18	8		T124	9		T206	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	3		T52	2		T53	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T25	14		T214	7		T289	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T207	9		T218	7		T204	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	4		T158	15		T27	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T16	9		T207	15		T220	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	10		T14	12		T132	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T22	1		T120	20		T49	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T209	6		T202	1		T161	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T29	4		T108	15		T53	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T17	2		T25	13		T125	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T144	11		T119	12		T158	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T51	1		T126	14		T222	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T122	3		T116	13		T124	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T15	1		T19	8		T124	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T122	7		T132	2		T53	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1106	1			T11	2		T14	12		T58	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	15		T52	3		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	1		T10	1		T13	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	4		T12	1		T53	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1431	1			T2	2		T11	3		T58	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T1	1		T16	10		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	11		T12	1		T29	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T200	1		T201	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T14	13		T115	1		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T108	16		T22	2		T120	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	1		T117	1		T125	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	1		T29	10		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T17	6		T25	14		T129	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T13	1		T122	4		T116	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T124	6		T51	2		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	1		T7	1		T122	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	2		T19	9		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T12	1		T53	12		T165	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T14	13		T19	3		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T202	2		T39	3		T236	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T203	1		T204	2		T79	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16241	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T206	15		T133	1		T172	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	12		T52	12		T64	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	7		T18	3		T124	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	2		T59	1		T64	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	957	1			T2	20		T20	27		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T1	14		T16	5		T206	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T29	4		T208	4		T180	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T130	12		T224	2		T279	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T115	15		T132	13		T179	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T120	25		T49	6		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T117	12		T125	14		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	9		T29	2		T174	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T17	1		T129	12		T179	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T116	14		T117	11		T119	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T124	9		T126	12		T258	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	11		T132	4		T124	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T19	11		T115	4		T211	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T212	14		T66	2		T130	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T19	8		T65	9		T67	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T79	3		T227	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T181	14		T307	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T206	13		T172	4		T236	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T260	1		T66	7		T39	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T19	3		T65	11		T67	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T181	12		T135	1		T138	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T216	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T13	15		T56	1		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	1		T13	1		T18	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	4		T12	1		T52	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	1		T25	15		T214	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	1		T120	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T29	6		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T16	10		T200	1		T207	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	11		T14	13		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	1		T22	2		T120	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	1		T215	1		T196	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	1		T29	10		T108	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T17	6		T117	1		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	1		T144	12		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	2		T126	15		T199	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T122	4		T116	14		T124	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T15	2		T19	9		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T1	1		T7	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1445	1			T2	2		T11	3		T14	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T66	2		T306	7		T290	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T19	8		T65	9		T67	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T181	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T216	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T13	12		T64	8		T128	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	7		T18	3		T124	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	2		T52	12		T64	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T221	7		T159	11		T224	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	14		T59	1		T226	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T29	4		T219	7		T208	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T16	5		T220	2		T224	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T115	15		T132	13		T179	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T120	25		T49	6		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T215	11		T161	4		T230	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	9		T29	2		T70	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T17	1		T117	12		T125	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T117	11		T174	3		T119	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T126	12		T222	10		T308	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T116	14		T124	2		T68	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T19	11		T115	4		T124	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T1	11		T132	4		T212	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1017	1			T2	20		T20	27		T141	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2