Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21483

1

T1

12

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3045

1

T1

23

T7

19

T8

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18783

1

T1

8

T3

160

T5

55

auto[1]

5745

1

T1

27

T2

22

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	702	1			T3	1		T24	1		T21	4
values[0]	56	1			T203	1		T308	19		T272	1
values[1]	697	1			T13	27		T116	28		T22	2
values[2]	2586	1			T2	22		T11	3		T58	19
values[3]	428	1			T12	1		T25	14		T67	14
values[4]	783	1			T1	15		T13	1		T16	15
values[5]	642	1			T1	12		T19	20		T144	12
values[6]	559	1			T7	6		T10	1		T12	2
values[7]	659	1			T14	13		T108	16		T214	8
values[8]	589	1			T7	1		T8	10		T19	11
values[9]	1032	1			T1	8		T7	12		T10	1
minimum	15795	1			T3	160		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	628	1			T13	27		T17	7		T22	2
values[1]	2521	1			T2	22		T11	3		T58	19
values[2]	530	1			T1	15		T12	1		T16	15
values[3]	713	1			T13	1		T29	12		T144	12
values[4]	651	1			T1	12		T12	1		T19	20
values[5]	588	1			T7	6		T10	1		T12	1
values[6]	611	1			T14	13		T108	16		T117	12
values[7]	580	1			T7	1		T8	10		T19	11
values[8]	979	1			T1	8		T7	12		T10	1
values[9]	219	1			T18	12		T118	1		T70	19
minimum	16508	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T52	13		T53	1		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	13		T17	5		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T2	22		T11	1		T58	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T122	1		T25	1		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T16	6		T67	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	15		T212	15		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T29	8		T144	1		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	1		T211	12		T120	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T1	12		T12	1		T174	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T19	12		T148	1		T125	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T115	5		T214	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	3		T10	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T117	12		T200	1		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	1		T108	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T19	9		T117	13		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	1		T8	10		T132	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T29	6		T115	16		T124	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	8		T7	2		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T18	4		T201	1		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T118	1		T70	19		T224	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16163	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T116	15		T234	1		T151	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T52	2		T53	3		T188	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	14		T17	2		T22	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T11	2		T58	16		T81	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T122	3		T25	13		T27	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	9		T67	2		T128	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T212	13		T129	2		T189	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	4		T144	11		T226	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T211	1		T120	17		T128	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T119	12		T158	8		T49	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T19	8		T125	15		T207	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T214	7		T68	2		T27	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	3		T15	1		T120	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T130	15		T220	7		T209	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	12		T108	15		T53	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T19	2		T27	12		T130	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T132	11		T59	2		T66	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T29	4		T124	11		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	10		T14	12		T122	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T18	8		T246	5		T275	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T239	7		T277	12		T309	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T116	13		T234	4		T218	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	479	1			T3	1		T24	1		T21	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T118	1		T70	19		T130	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T204	15		T232	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T203	1		T308	11		T272	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T25	1		T52	13		T53	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	13		T116	15		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T2	22		T11	1		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T122	1		T17	5		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T67	12		T128	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T25	1		T148	1		T129	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T16	6		T29	8		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T1	15		T13	1		T211	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	12		T144	1		T174	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T19	12		T148	1		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T12	2		T115	5		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	3		T10	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T214	1		T27	1		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T14	1		T108	1		T53	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T19	9		T117	12		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	1		T8	10		T132	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T18	4		T29	6		T115	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	8		T7	2		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15662	1			T3	160		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T124	2		T246	5		T261	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T130	14		T210	17		T284	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T204	12		T232	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T308	8		T278	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T25	14		T52	2		T53	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	14		T116	13		T22	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T11	2		T58	16		T81	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T122	3		T17	2		T27	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T67	2		T128	5		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T25	13		T129	2		T209	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T16	9		T29	4		T226	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T211	1		T120	17		T212	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T144	11		T119	12		T49	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T19	8		T207	15		T253	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T158	8		T68	2		T208	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	3		T15	1		T120	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T214	7		T27	1		T130	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T14	12		T108	15		T53	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T19	2		T27	12		T209	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T132	11		T66	6		T219	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T18	8		T29	4		T124	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	10		T14	12		T122	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T52	3		T53	4		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	15		T17	6		T22	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T2	2		T11	3		T58	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T122	4		T25	14		T27	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T16	10		T67	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T1	1		T212	14		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T29	10		T144	12		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	1		T211	2		T120	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T12	1		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T19	9		T148	1		T125	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	1		T115	1		T214	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	4		T10	1		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T117	1		T200	1		T130	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T14	13		T108	16		T53	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	3		T117	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	1		T8	1		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T29	6		T115	1		T124	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	1		T7	12		T10	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T18	9		T201	1		T288	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T118	1		T70	1		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16327	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T116	14		T234	5		T151	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T52	12		T206	2		T295	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	12		T17	1		T124	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T2	20		T20	27		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T27	7		T304	11		T224	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	5		T67	11		T128	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T1	14		T212	14		T129	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	2		T226	14		T248	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T211	11		T120	15		T128	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	11		T174	3		T119	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T19	11		T125	14		T253	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T115	4		T68	2		T221	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	2		T120	10		T126	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T117	11		T130	11		T220	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T165	1		T238	4		T179	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T19	8		T117	12		T130	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T8	9		T132	17		T121	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T29	4		T115	15		T124	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T1	7		T64	11		T130	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T18	3		T246	2		T251	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T70	18		T224	2		T239	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T215	9		T161	10		T182	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T116	14		T218	8		T308	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	519	1			T3	1		T24	1		T21	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T118	1		T70	1		T130	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T204	13		T232	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T203	1		T308	9		T272	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T25	15		T52	3		T53	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	15		T116	14		T22	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T2	2		T11	3		T58	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T122	4		T17	6		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	1		T67	3		T128	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T25	14		T148	1		T129	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T16	10		T29	10		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T13	1		T211	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	1		T144	12		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T19	9		T148	1		T207	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	2		T115	1		T158	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	4		T10	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T214	8		T27	2		T200	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T14	13		T108	16		T53	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T19	3		T117	1		T56	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	1		T8	1		T132	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T18	9		T29	6		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T7	12		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15795	1			T3	160		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T124	2		T246	2		T261	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T70	18		T130	12		T277	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T204	14		T232	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T308	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T52	12		T215	9		T206	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	12		T116	14		T124	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T2	20		T20	27		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T17	1		T27	7		T190	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T67	11		T128	1		T159	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T129	2		T304	11		T224	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T16	5		T29	2		T226	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	14		T211	11		T120	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	11		T174	3		T119	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T19	11		T253	5		T180	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T115	4		T68	2		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T7	2		T120	10		T59	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T130	11		T159	11		T219	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T165	1		T126	12		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T19	8		T117	11		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T8	9		T132	17		T121	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T18	3		T29	4		T115	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	7		T64	11		T127	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2