Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21250

1

T1

35

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3278

1

T7

1

T10

1

T12

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19041

1

T1

35

T3

161

T5

55

auto[1]

5487

1

T2

22

T7

18

T8

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	320	1			T19	20		T29	10		T211	13
values[0]	94	1			T127	14		T200	1		T284	11
values[1]	705	1			T10	1		T13	2		T108	16
values[2]	756	1			T7	11		T14	13		T132	7
values[3]	544	1			T1	15		T15	2		T56	1
values[4]	531	1			T7	7		T18	12		T19	11
values[5]	2523	1			T1	12		T2	22		T7	1
values[6]	635	1			T10	1		T13	27		T17	7
values[7]	579	1			T1	8		T122	4		T115	5
values[8]	667	1			T8	10		T12	1		T16	15
values[9]	969	1			T12	1		T14	13		T29	12
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	691	1			T10	1		T13	1		T132	7
values[1]	680	1			T1	15		T7	11		T14	13
values[2]	497	1			T7	6		T19	11		T119	22
values[3]	2495	1			T2	22		T7	2		T11	3
values[4]	543	1			T1	12		T10	1		T122	8
values[5]	632	1			T13	27		T17	7		T53	26
values[6]	734	1			T1	8		T8	10		T122	4
values[7]	454	1			T12	1		T144	12		T117	13
values[8]	1070	1			T12	1		T14	13		T19	20
values[9]	159	1			T52	15		T210	18		T250	12
minimum	16573	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T10	1		T108	1		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	1		T132	5		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	15		T7	1		T15	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	1		T56	1		T165	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	3		T133	1		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T19	9		T119	10		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T2	22		T7	1		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	1		T12	1		T132	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	12		T121	6		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	1		T122	1		T65	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	13		T17	5		T53	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T260	1		T179	3		T246	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	8		T8	10		T16	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T122	1		T115	16		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T144	1		T117	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T158	1		T165	5		T68	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	1		T19	12		T29	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	401	1			T12	1		T29	6		T117	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T210	1		T75	5		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T52	13		T250	1		T291	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16158	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T220	10		T198	1		T171	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T108	15		T120	17		T289	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T132	2		T214	7		T125	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	10		T15	1		T128	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	12		T165	1		T66	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	3		T187	14		T285	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T19	2		T119	12		T53	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T11	2		T58	16		T81	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T132	9		T229	1		T226	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T67	2		T220	5		T208	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T122	7		T65	7		T234	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	14		T17	2		T53	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T246	5		T253	6		T172	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	9		T49	2		T130	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T122	3		T231	10		T209	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T144	11		T25	13		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T158	8		T68	2		T128	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	12		T19	8		T29	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T29	4		T25	14		T211	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T210	17		T75	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T52	2		T250	11		T291	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T220	7		T198	3		T171	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T19	12		T188	4		T200	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T29	6		T211	12		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T127	5		T200	1		T284	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T310	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T10	1		T13	1		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	1		T199	1		T220	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	1		T123	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	1		T132	5		T119	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	15		T15	1		T128	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T56	1		T165	1		T64	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	4		T18	4		T116	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T19	9		T53	1		T229	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T1	12		T2	22		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	1		T12	1		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	13		T17	5		T53	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T10	1		T206	8		T179	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	8		T115	5		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T122	1		T120	1		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	10		T12	1		T16	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T115	16		T158	1		T165	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	1		T29	8		T124	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T12	1		T117	12		T25	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T19	8		T188	2		T210	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T29	4		T211	1		T130	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T127	9		T284	10		T266	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T310	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T108	15		T120	17		T289	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T220	7		T198	3		T171	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	10		T129	12		T261	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T14	12		T132	2		T119	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T15	1		T128	1		T39	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T165	1		T27	20		T189	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	3		T18	8		T116	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T19	2		T53	3		T229	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T11	2		T58	16		T81	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T122	7		T132	9		T65	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	14		T17	2		T53	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T206	4		T246	5		T253	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T49	2		T131	7		T161	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T122	3		T231	10		T209	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	9		T144	11		T25	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T158	8		T231	10		T172	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T14	12		T29	4		T124	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T25	14		T52	2		T68	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T10	1		T108	16		T123	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	1		T132	3		T214	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	1		T7	11		T15	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	13		T56	1		T165	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	4		T133	1		T187	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T19	3		T119	13		T53	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T2	2		T7	1		T11	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	1		T12	1		T132	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T1	1		T121	1		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	1		T122	8		T65	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	15		T17	6		T53	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T260	1		T179	1		T246	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T8	1		T16	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T122	4		T115	1		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	1		T144	12		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T158	9		T165	4		T68	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T14	13		T19	9		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T12	1		T29	6		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T210	18		T75	12		-	-
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T52	3		T250	12		T291	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16338	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T220	8		T198	4		T171	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T120	15		T206	2		T179	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T132	4		T125	14		T215	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	14		T129	11		T261	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T66	2		T129	2		T130	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	2		T285	13		T290	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T19	8		T119	9		T64	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T2	20		T18	3		T20	27
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T132	13		T229	2		T226	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T1	11		T121	5		T67	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T65	3		T205	2		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	12		T17	1		T65	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T179	2		T246	2		T253	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T1	7		T8	9		T16	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T115	15		T59	1		T64	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T117	12		T226	2		T159	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T165	1		T68	2		T128	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T19	11		T29	2		T124	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T29	4		T117	11		T211	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T75	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T52	12		T291	4		T311	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T127	4		T225	4		T222	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T220	9		T181	14		T292	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T19	9		T188	6		T200	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T29	6		T211	2		T199	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T127	10		T200	1		T284	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T310	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	1		T13	1		T108	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T199	1		T220	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	11		T123	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	13		T132	3		T119	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T1	1		T15	2		T128	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T56	1		T165	2		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	5		T18	9		T116	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	3		T53	4		T229	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T1	1		T2	2		T11	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T12	1		T122	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	15		T17	6		T53	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	1		T206	5		T179	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	1		T115	1		T118	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T122	4		T120	1		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	1		T12	1		T16	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T115	1		T158	9		T165	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T14	13		T29	10		T124	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T12	1		T117	1		T25	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T19	11		T75	1		T283	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T29	4		T211	11		T64	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T127	4		T266	6		T204	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T310	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T120	15		T179	11		T267	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T220	9		T295	10		T181	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T129	11		T206	2		T261	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T132	4		T119	9		T66	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	14		T285	13		T294	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T64	8		T27	7		T189	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T7	2		T18	3		T116	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T19	8		T229	2		T206	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T1	11		T2	20		T20	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T132	13		T65	3		T226	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	12		T17	1		T65	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T206	7		T179	2		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	7		T115	4		T49	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T159	4		T179	10		T282	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T8	9		T16	5		T117	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T115	15		T165	1		T59	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T29	2		T124	10		T238	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T117	11		T52	12		T68	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2