Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21222

1

T1

15

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3306

1

T1

20

T8

10

T12

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18792

1

T1

12

T3

161

T5

55

auto[1]

5736

1

T1

23

T2

22

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	238	1			T19	11		T144	12		T119	22
values[0]	60	1			T27	15		T312	35		T313	1
values[1]	633	1			T12	2		T13	1		T132	7
values[2]	761	1			T1	15		T18	12		T17	7
values[3]	584	1			T108	16		T118	1		T123	1
values[4]	569	1			T14	13		T122	4		T19	20
values[5]	580	1			T1	20		T14	13		T16	15
values[6]	647	1			T7	6		T10	2		T12	1
values[7]	742	1			T115	5		T132	23		T22	2
values[8]	570	1			T7	2		T13	1		T25	29
values[9]	2939	1			T2	22		T7	11		T8	10
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	480	1			T12	1		T17	7		T132	7
values[1]	780	1			T1	15		T18	12		T29	10
values[2]	678	1			T14	13		T118	1		T59	4
values[3]	576	1			T122	4		T19	20		T16	15
values[4]	507	1			T1	20		T14	13		T117	13
values[5]	712	1			T7	6		T10	2		T12	1
values[6]	2646	1			T2	22		T7	1		T11	3
values[7]	666	1			T7	1		T8	10		T13	28
values[8]	842	1			T7	11		T15	2		T122	8
values[9]	128	1			T117	12		T174	4		T207	6
minimum	16513	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T132	5		T199	1		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	1		T17	5		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	15		T123	1		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T18	4		T29	6		T115	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T70	19		T129	3		T159	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T14	1		T118	1		T59	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T122	1		T16	6		T234	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T19	12		T211	12		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	1		T117	13		T52	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T1	20		T120	1		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	3		T10	2		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T29	8		T116	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T2	22		T7	1		T11	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T132	14		T121	6		T126	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	1		T13	1		T25	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	10		T13	13		T120	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T19	9		T119	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T15	1		T122	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T231	1		T151	1		T314	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T117	12		T174	4		T207	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16166	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T27	8		T129	12		T152	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T132	2		T128	1		T189	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T17	2		T214	7		T238	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T66	6		T234	3		T219	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T18	8		T29	4		T108	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T129	2		T206	4		T241	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	12		T180	10		T239	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T122	3		T16	9		T234	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T19	8		T211	1		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T14	12		T52	2		T128	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T171	7		T39	2		T240	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	3		T22	1		T59	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T29	4		T116	13		T124	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T11	2		T58	16		T81	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T132	9		T126	14		T127	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T25	13		T49	2		T67	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	14		T120	17		T242	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	10		T19	2		T119	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	1		T122	7		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T231	10		T314	15		T315	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T207	5		T237	3		T154	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T27	7		T129	12		T152	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T19	9		T119	10		T53	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T144	1		T165	5		T201	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T312	20		T313	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T27	8		T233	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T13	1		T132	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T214	1		T238	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	15		T56	1		T260	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T18	4		T17	5		T29	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T123	1		T66	3		T70	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T108	1		T118	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T122	1		T234	1		T226	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	1		T19	12		T51	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T16	6		T117	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	20		T211	12		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	3		T10	2		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	1		T29	8		T116	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T115	5		T22	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T132	14		T121	6		T126	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T7	2		T13	1		T25	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T120	16		T242	1		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T2	22		T7	1		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T8	10		T13	13		T15	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T19	2		T119	12		T53	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T144	11		T250	5		T162	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T312	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T27	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T132	2		T124	5		T188	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T214	7		T238	3		T129	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T234	3		T128	1		T219	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T18	8		T17	2		T29	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T66	6		T129	2		T206	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T108	15		T53	13		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T122	3		T234	4		T130	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T14	12		T19	8		T51	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T14	12		T16	9		T52	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T211	1		T65	2		T171	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T7	3		T59	2		T247	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T29	4		T116	13		T124	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T22	1		T158	8		T165	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T132	9		T126	14		T65	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T25	27		T49	2		T67	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T120	17		T242	3		T210	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1075	1			T7	10		T11	2		T58	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	14		T15	1		T122	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T132	3		T199	1		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T17	6		T214	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T1	1		T123	1		T56	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T18	9		T29	6		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T70	1		T129	3		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	13		T118	1		T59	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T122	4		T16	10		T234	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	9		T211	2		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	13		T117	1		T52	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T1	2		T120	1		T171	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	4		T10	2		T22	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T12	1		T29	10		T116	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T2	2		T7	1		T11	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T132	10		T121	1		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	1		T13	1		T25	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	1		T13	15		T120	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	11		T19	3		T119	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T15	2		T122	8		T144	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T231	11		T151	1		T314	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T117	1		T174	1		T207	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16284	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T27	8		T129	13		T152	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T132	4		T128	2		T189	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T17	1		T238	4		T130	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	14		T66	2		T219	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T18	3		T29	4		T115	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T70	18		T129	2		T159	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T59	1		T179	10		T180	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T16	5		T226	2		T205	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T19	11		T211	11		T64	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T117	12		T52	12		T128	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T1	18		T244	11		T245	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	2		T246	2		T230	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	2		T116	14		T124	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T2	20		T20	27		T115	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T132	13		T121	5		T126	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T49	6		T67	11		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T8	9		T13	12		T120	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T19	8		T119	9		T226	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T120	10		T165	1		T159	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T316	2		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T117	11		T174	3		T237	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T124	9		T134	16		T182	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T27	7		T129	11		T152	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T19	3		T119	13		T53	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T144	12		T165	4		T201	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T312	16		T313	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T27	8		T233	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T13	1		T132	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	1		T214	8		T238	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	1		T56	1		T260	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T18	9		T17	6		T29	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T123	1		T66	7		T70	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T108	16		T118	1		T53	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T122	4		T234	5		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	13		T19	9		T51	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	13		T16	10		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	2		T211	2		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	4		T10	2		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	1		T29	10		T116	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T115	1		T22	2		T158	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T132	10		T121	1		T126	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	2		T13	1		T25	29
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T120	18		T242	4		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T2	2		T7	11		T11	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	1		T13	15		T15	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T19	8		T119	9		T302	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T165	1		T268	5		T317	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T312	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T27	7		T233	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T132	4		T124	9		T189	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T238	4		T129	11		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	14		T128	2		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T18	3		T17	1		T29	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T66	2		T70	18		T129	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T59	1		T179	12		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T226	2		T130	10		T159	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T19	11		T206	2		T180	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	5		T117	12		T52	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T1	18		T211	11		T64	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	2		T247	7		T240	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T29	2		T116	14		T124	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T115	4		T257	2		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T132	13		T121	5		T126	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T49	6		T67	11		T129	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T120	15		T215	9		T248	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T2	20		T20	27		T141	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	9		T13	12		T117	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2