Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21092

1

T1

8

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3436

1

T1

27

T7

2

T8

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19112

1

T1

35

T3

161

T5

55

auto[1]

5416

1

T2

22

T8

10

T10

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	241	1			T1	12		T119	22		T200	1
values[0]	47	1			T209	7		T253	9		T280	21
values[1]	681	1			T1	8		T132	23		T144	12
values[2]	597	1			T12	2		T14	13		T115	16
values[3]	619	1			T7	6		T14	13		T16	15
values[4]	548	1			T19	20		T117	12		T123	1
values[5]	2565	1			T2	22		T7	1		T11	3
values[6]	726	1			T7	11		T13	1		T18	12
values[7]	611	1			T8	10		T12	1		T15	2
values[8]	772	1			T10	1		T13	1		T29	10
values[9]	916	1			T1	15		T7	1		T10	1
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	663	1			T115	16		T132	23		T144	12
values[1]	550	1			T12	2		T14	13		T132	7
values[2]	665	1			T7	6		T14	13		T16	15
values[3]	2562	1			T2	22		T11	3		T58	19
values[4]	659	1			T7	1		T13	1		T122	4
values[5]	618	1			T7	11		T12	1		T18	12
values[6]	607	1			T8	10		T15	2		T115	5
values[7]	767	1			T7	1		T10	1		T13	1
values[8]	912	1			T1	27		T10	1		T13	27
values[9]	133	1			T119	22		T200	1		T253	11
minimum	16392	1			T1	8		T3	161		T5	55

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T144	1		T211	12		T165	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T115	16		T132	14		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T132	5		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	1		T14	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	3		T16	6		T117	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	1		T214	1		T215	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T2	22		T11	1		T58	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T19	12		T117	12		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	5		T147	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	1		T13	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	1		T18	4		T49	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T19	9		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T115	5		T53	1		T59	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T8	10		T15	1		T126	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	1		T13	1		T116	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T29	6		T124	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	1		T13	13		T124	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T1	27		T188	4		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T119	10		T203	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T200	1		T253	6		T182	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16106	1			T1	8		T3	161		T5	53
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T120	11		T221	8		T267	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T144	11		T211	1		T181	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T132	9		T22	1		T124	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T132	2		T108	15		T59	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	12		T27	12		T128	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	3		T16	9		T158	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	12		T214	7		T296	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T11	2		T58	16		T122	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T19	8		T221	6		T210	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T17	2		T129	2		T161	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T122	3		T29	4		T158	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	10		T18	8		T49	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T19	2		T25	13		T208	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T53	3		T261	10		T198	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T15	1		T126	14		T212	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T116	13		T25	14		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T29	4		T124	9		T67	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	14		T124	5		T120	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T188	2		T27	1		T206	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T119	12		T291	10		T276	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T253	5		T192	4		T318	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T120	3		T235	13		T266	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T119	10		T179	3		T162	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T1	12		T200	1		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T280	11		T272	1		T305	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T209	1		T253	3		T319	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	8		T144	1		T211	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T132	14		T22	1		T120	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T132	5		T174	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	1		T14	1		T115	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	3		T16	6		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	1		T214	1		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T123	1		T51	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	12		T117	12		T215	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T2	22		T11	1		T58	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T122	1		T29	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	1		T18	4		T65	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T13	1		T118	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T115	5		T49	7		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T8	10		T12	1		T15	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	1		T13	1		T116	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	6		T199	1		T128	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T10	1		T13	13		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T1	15		T7	1		T124	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T119	12		T162	10		T139	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T241	4		T253	5		T172	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T280	10		T305	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T209	6		T253	6		T319	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T144	11		T211	1		T218	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T132	9		T22	1		T120	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T132	2		T59	2		T189	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	12		T124	2		T27	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	3		T16	9		T108	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T14	12		T214	7		T257	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T51	1		T53	13		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T19	8		T221	6		T296	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T11	2		T58	16		T122	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T122	3		T29	4		T158	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	10		T18	8		T65	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T207	15		T208	4		T180	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T49	2		T53	3		T261	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T15	1		T19	2		T25	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T116	13		T25	14		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	4		T128	1		T130	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	14		T124	5		T120	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T124	9		T67	2		T188	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T144	12		T211	2		T165	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T115	1		T132	10		T22	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	1		T132	3		T108	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T14	13		T27	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	4		T16	10		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	13		T214	8		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T2	2		T11	3		T58	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T19	9		T117	1		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T17	6		T147	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	1		T13	1		T122	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	11		T18	9		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T19	3		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T115	1		T53	4		T59	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T15	2		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	1		T13	1		T116	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	1		T29	6		T124	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T10	1		T13	15		T124	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T1	2		T188	6		T27	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T119	13		T203	1		T135	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T200	1		T253	6		T182	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16237	1			T1	1		T3	161		T5	55
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T120	4		T221	1		T267	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T211	11		T165	1		T64	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T115	15		T132	13		T124	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T132	4		T174	3		T189	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T128	1		T130	10		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T7	2		T16	5		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T215	12		T304	11		T152	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T2	20		T20	27		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T19	11		T117	11		T70	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T17	1		T129	2		T159	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	2		T64	8		T65	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T18	3		T49	6		T65	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T19	8		T226	2		T219	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T115	4		T59	1		T261	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	9		T126	12		T212	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T116	14		T205	2		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T29	4		T124	8		T67	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	12		T124	9		T120	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T1	25		T206	7		T237	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T119	9		T291	4		T265	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T253	5		T182	12		T192	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T1	7		T121	5		T218	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T120	10		T221	7		T267	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T119	13		T179	1		T162	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T1	1		T200	1		T241	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T280	11		T272	1		T305	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T209	7		T253	7		T319	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T1	1		T144	12		T211	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T132	10		T22	2		T120	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	1		T132	3		T174	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T14	13		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T7	4		T16	10		T108	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	13		T214	8		T200	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T123	1		T51	2		T53	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T19	9		T117	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T2	2		T11	3		T58	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	1		T122	4		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	11		T18	9		T65	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	1		T118	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T115	1		T49	3		T53	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T8	1		T12	1		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	1		T13	1		T116	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T29	6		T199	1		T128	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T10	1		T13	15		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	1		T7	1		T124	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T119	9		T179	2		T139	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T1	11		T253	5		T172	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T280	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T253	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T1	7		T211	11		T121	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T132	13		T120	10		T64	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T132	4		T174	3		T64	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T115	15		T124	2		T128	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T7	2		T16	5		T117	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T159	11		T257	2		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T229	2		T181	14		T240	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T19	11		T117	11		T215	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	915	1			T2	20		T20	27		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	2		T64	8		T65	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T18	3		T65	3		T253	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T226	2		T129	12		T219	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T115	4		T49	6		T59	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	9		T19	8		T126	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T116	14		T205	2		T219	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T29	4		T128	2		T215	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	12		T124	9		T120	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T1	14		T124	8		T67	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2