Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21327

1

T1

8

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3201

1

T1

27

T7

17

T8

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19205

1

T3

161

T5

55

T6

12

auto[1]

5323

1

T1

35

T2

22

T7

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	198	1			T188	6		T257	1		T179	12
values[0]	62	1			T199	1		T219	9		T206	12
values[1]	720	1			T18	12		T17	7		T25	14
values[2]	2682	1			T1	8		T2	22		T7	12
values[3]	682	1			T132	23		T117	13		T56	1
values[4]	503	1			T12	1		T124	18		T242	4
values[5]	423	1			T7	6		T13	1		T144	12
values[6]	658	1			T13	1		T117	12		T174	4
values[7]	492	1			T7	1		T8	10		T15	2
values[8]	723	1			T10	1		T12	1		T13	27
values[9]	1180	1			T1	27		T10	1		T14	26
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	794	1			T7	12		T18	12		T17	7
values[1]	2688	1			T1	8		T2	22		T11	3
values[2]	555	1			T117	13		T56	1		T147	1
values[3]	569	1			T12	1		T124	18		T49	9
values[4]	429	1			T7	6		T13	1		T144	12
values[5]	581	1			T8	10		T13	1		T19	20
values[6]	643	1			T7	1		T13	27		T15	2
values[7]	701	1			T1	12		T10	2		T12	1
values[8]	1067	1			T1	15		T14	13		T122	8
values[9]	91	1			T108	16		T188	6		T159	5
minimum	16410	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	1		T124	10		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T18	4		T17	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1315	1			T1	8		T2	22		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	6		T22	1		T129	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T117	13		T56	1		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T147	1		T199	1		T64	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T12	1		T59	4		T257	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T124	9		T49	7		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	1		T120	11		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T7	3		T144	1		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	1		T117	12		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	10		T19	12		T174	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	1		T118	1		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	13		T15	1		T124	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T12	1		T212	15		T215	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	12		T10	2		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	1		T19	9		T29	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T1	15		T122	1		T132	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T188	4		T159	5		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T108	1		T257	1		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16137	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T199	1		T189	5		T219	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T124	5		T234	4		T125	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	10		T18	8		T17	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1049	1			T11	2		T58	16		T81	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T16	9		T22	1		T130	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T207	9		T241	4		T210	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T67	2		T253	5		T152	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T257	5		T208	4		T38	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T124	9		T49	2		T51	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T120	3		T229	1		T221	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T7	3		T144	11		T128	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T52	2		T65	7		T66	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T19	8		T119	12		T59	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T234	3		T129	2		T250	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	14		T15	1		T124	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T212	13		T210	11		T284	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	12		T122	3		T29	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T14	12		T19	2		T29	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T122	7		T132	2		T165	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T188	2		T171	7		T302	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T108	15		T171	16		T320	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T189	2		T206	4		T62	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T188	4		T225	5		T321	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T257	1		T179	12		T295	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T322	10		T269	1		T300	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T199	1		T219	9		T206	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T124	10		T158	1		T128	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T18	4		T17	5		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T1	8		T2	22		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T7	1		T16	6		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T132	14		T117	13		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T147	1		T199	1		T64	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T12	1		T186	1		T257	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T124	9		T242	1		T65	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	1		T120	11		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T7	3		T144	1		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T117	12		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T174	4		T119	10		T128	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	1		T234	1		T215	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T8	10		T15	1		T19	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T12	1		T118	1		T226	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T10	1		T13	13		T29	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T14	1		T19	9		T29	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T1	27		T10	1		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T188	2		T225	7		T243	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T171	16		T323	2		T277	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T269	10		T300	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T206	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T124	5		T158	8		T128	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T18	8		T17	2		T25	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T11	2		T58	16		T81	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	10		T16	9		T22	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T132	9		T126	14		T207	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T253	5		T161	6		T152	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T257	5		T208	4		T38	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T124	9		T242	3		T65	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T120	3		T229	1		T296	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T7	3		T144	11		T49	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T52	2		T65	7		T66	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T119	12		T128	1		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T234	3		T131	7		T220	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T15	1		T19	8		T59	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T129	2		T210	11		T284	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	14		T29	4		T124	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T14	12		T19	2		T29	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T14	12		T122	10		T132	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	1		T124	6		T234	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T7	11		T18	9		T17	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T1	1		T2	2		T11	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T16	10		T22	2		T129	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T117	1		T56	1		T186	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T147	1		T199	1		T64	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	1		T59	3		T257	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T124	10		T49	3		T51	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	1		T120	4		T199	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T7	4		T144	12		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	1		T117	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	1		T19	9		T174	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T7	1		T118	1		T234	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	15		T15	2		T124	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	1		T212	14		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T10	2		T14	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T14	13		T19	3		T29	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T1	1		T122	8		T132	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T188	6		T159	1		T171	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T108	16		T257	1		T171	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16287	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T199	1		T189	6		T219	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T124	9		T125	14		T206	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T18	3		T17	1		T64	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T1	7		T2	20		T20	27
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T16	5		T129	12		T221	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T117	12		T253	2		T235	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T64	14		T67	11		T159	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T59	1		T257	2		T179	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T124	8		T49	6		T65	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T120	10		T64	11		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	2		T128	2		T205	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T117	11		T52	12		T65	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	9		T19	11		T174	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T226	2		T129	2		T215	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T13	12		T124	2		T127	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T212	14		T215	9		T159	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	11		T29	2		T121	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T19	8		T29	4		T116	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	14		T132	4		T206	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T159	4		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T320	8		T324	7		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T128	1		T271	9		T322	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T189	1		T219	8		T206	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T188	6		T225	8		T321	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T257	1		T179	1		T295	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T322	1		T269	11		T300	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T199	1		T219	1		T206	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T124	6		T158	9		T128	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T18	9		T17	6		T25	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T1	1		T2	2		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	11		T16	10		T22	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T132	10		T117	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T147	1		T199	1		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T12	1		T186	1		T257	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T124	10		T242	4		T65	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	1		T120	4		T199	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T7	4		T144	12		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	1		T117	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T174	1		T119	13		T128	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	1		T234	4		T215	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T8	1		T15	2		T19	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T12	1		T118	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	1		T13	15		T29	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T14	13		T19	3		T29	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T1	2		T10	1		T14	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T225	4		T243	14		T301	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T179	11		T277	14		T292	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T322	9		T300	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T219	8		T206	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T124	9		T128	1		T125	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T18	3		T17	1		T64	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T1	7		T2	20		T20	27
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T16	5		T67	11		T68	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T132	13		T117	12		T126	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T64	14		T159	11		T248	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T257	2		T179	10		T208	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T124	8		T65	6		T226	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T120	10		T59	1		T64	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T7	2		T49	6		T161	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T117	11		T52	12		T65	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T174	3		T119	9		T128	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T215	11		T220	2		T237	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T8	9		T19	11		T127	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T226	2		T129	2		T215	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	12		T29	2		T124	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T19	8		T29	4		T116	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T1	25		T132	4		T206	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2