Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T12	1		T13	1		T132	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T12	1		T17	6		T27	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T1	1		T108	16		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T18	9		T29	6		T115	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T70	1		T129	3		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T14	13		T118	1		T59	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T122	4		T16	10		T226	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	1		T19	9		T211	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T14	13		T117	1		T52	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T1	1		T120	1		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T7	4		T10	2		T22	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T12	1		T29	10		T116	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T2	2		T11	3		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T121	1		T126	15		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	2		T25	14		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T8	1		T13	15		T120	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	11		T19	3		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T15	2		T122	8		T144	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T128	2		T235	14		T236	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T117	1		T207	6		T237	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T132	4		T124	9		T128	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T17	1		T27	7		T238	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T1	14		T66	2		T219	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T18	3		T29	4		T115	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T70	18		T129	2		T159	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T59	1		T179	10		T180	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T16	5		T226	2		T205	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	7		T19	11		T211	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T117	12		T52	12		T128	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T1	11		T244	11		T245	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	2		T246	2		T172	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T29	2		T116	14		T124	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T2	20		T20	27		T115	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T121	5		T126	12		T127	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T49	6		T67	11		T229	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	9		T13	12		T120	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T19	8		T174	3		T119	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T120	10		T165	1		T159	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T117	11		T237	9		T181	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T231	11		T241	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T201	1		T207	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T232	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T27	8		T233	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	1		T13	1		T132	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T238	4		T129	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	1		T56	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T18	9		T17	6		T29	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T108	16		T123	1		T66	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T118	1		T53	14		T59	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T122	4		T52	3		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	1		T14	13		T19	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T14	13		T16	10		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T1	1		T211	2		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T7	4		T10	2		T22	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	10		T116	14		T124	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T115	1		T132	10		T158	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T124	10		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T7	2		T13	1		T25	29
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T120	18		T121	1		T242	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1423	1			T2	2		T7	11		T11	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T8	1		T13	15		T15	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T232	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T27	7		T233	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T132	4		T124	9		T189	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T238	4		T129	11		T130	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	14		T128	2		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T18	3		T17	1		T29	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T66	2		T70	18		T129	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T59	1		T179	12		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T52	12		T226	2		T159	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	7		T19	11		T206	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T16	5		T117	12		T128	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	11		T211	11		T64	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T7	2		T247	7		T240	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T29	2		T116	14		T124	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T115	4		T132	13		T67	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T124	8		T126	12		T65	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T49	6		T129	12		T208	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T120	15		T121	5		T248	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1043	1			T2	20		T19	8		T20	27
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T8	9		T13	12		T117	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2