Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21384

1

T1

15

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3144

1

T1

20

T7

8

T12

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19164

1

T3

161

T5

55

T6

12

auto[1]

5364

1

T1

35

T2

22

T7

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	40	1			T131	8		T259	32		-	-
values[0]	97	1			T70	19		T159	5		T254	10
values[1]	578	1			T7	6		T12	1		T14	13
values[2]	686	1			T13	27		T16	15		T117	12
values[3]	623	1			T13	1		T15	2		T19	11
values[4]	2937	1			T1	8		T2	22		T11	3
values[5]	546	1			T1	12		T122	4		T115	16
values[6]	666	1			T7	1		T12	1		T108	16
values[7]	615	1			T1	15		T10	1		T132	7
values[8]	588	1			T7	1		T10	1		T13	1
values[9]	947	1			T7	11		T8	10		T12	1
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	905	1			T7	6		T12	1		T29	12
values[1]	531	1			T13	28		T16	15		T25	14
values[2]	746	1			T1	8		T15	2		T18	12
values[3]	2839	1			T1	12		T2	22		T11	3
values[4]	474	1			T7	1		T12	1		T132	23
values[5]	756	1			T1	15		T115	16		T214	8
values[6]	604	1			T7	1		T10	1		T29	10
values[7]	594	1			T7	11		T10	1		T13	1
values[8]	626	1			T8	10		T12	1		T14	13
values[9]	223	1			T123	1		T199	1		T260	1
minimum	16230	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T29	8		T56	1		T126	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T7	3		T12	1		T117	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	14		T25	1		T49	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T16	6		T119	10		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	1		T18	4		T116	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	8		T19	9		T174	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1393	1			T2	22		T11	1		T58	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	12		T17	5		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T120	11		T149	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	1		T12	1		T132	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	15		T115	16		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T214	1		T238	1		T205	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	1		T124	3		T121	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	1		T29	6		T117	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T10	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T132	5		T52	13		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	10		T12	1		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T19	12		T53	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T199	1		T260	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T123	1		T65	4		T131	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16075	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T14	1		T201	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T29	4		T126	14		T231	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T7	3		T22	1		T212	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T13	14		T25	13		T49	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T16	9		T119	12		T198	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T15	1		T18	8		T116	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T19	2		T120	17		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1097	1			T11	2		T58	16		T122	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T17	2		T144	11		T25	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T120	3		T27	1		T187	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T132	9		T108	15		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T158	15		T229	1		T188	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T214	7		T205	2		T130	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T124	2		T234	3		T128	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T29	4		T242	3		T59	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	10		T67	2		T128	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T132	2		T52	2		T165	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	12		T122	7		T124	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T19	8		T53	3		T220	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T261	10		T193	3		T262	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T65	7		T131	7		T219	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T14	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T131	1		T259	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T159	5		T254	8		T263	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T70	19		T264	1		T265	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	8		T56	1		T126	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	3		T12	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	13		T25	1		T49	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T16	6		T117	12		T22	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T15	1		T116	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T19	9		T174	4		T120	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1440	1			T2	22		T11	1		T58	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	8		T17	5		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T122	1		T115	16		T120	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	12		T132	14		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T158	1		T56	1		T229	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	1		T12	1		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	15		T10	1		T121	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T132	5		T117	13		T165	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	1		T13	1		T124	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	1		T29	6		T159	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T7	1		T8	10		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T19	12		T123	1		T52	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T131	7		T259	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T254	2		T263	11		T197	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T29	4		T126	14		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	3		T14	12		T65	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	14		T25	13		T49	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T16	9		T22	1		T119	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T15	1		T116	13		T124	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T19	2		T120	17		T158	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T11	2		T58	16		T81	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T17	2		T144	11		T25	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T122	3		T120	3		T27	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T132	9		T187	7		T266	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T158	15		T229	1		T129	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T108	15		T214	7		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T188	2		T234	3		T128	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T132	2		T59	2		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T124	2		T67	2		T128	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T29	4		T207	9		T206	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T7	10		T14	12		T122	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	8		T52	2		T53	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T29	10		T56	1		T126	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T7	4		T12	1		T117	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	16		T25	14		T49	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T16	10		T119	13		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T15	2		T18	9		T116	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	1		T19	3		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1428	1			T2	2		T11	3		T58	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	1		T17	6		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T120	4		T149	1		T27	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	1		T12	1		T132	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T115	1		T158	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T214	8		T238	1		T205	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T10	1		T124	3		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	1		T29	6		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T7	11		T10	1		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T132	3		T52	3		T165	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T12	1		T14	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T19	9		T53	4		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T199	1		T260	1		T200	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T123	1		T65	8		T131	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16214	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T14	13		T201	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T29	2		T126	12		T159	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T7	2		T117	11		T212	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T13	12		T49	6		T238	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T16	5		T119	9		T64	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T18	3		T116	14		T124	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	7		T19	8		T174	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T2	20		T20	27		T115	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T1	11		T17	1		T211	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T120	10		T267	11		T248	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T132	13		T268	5		T187	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	14		T115	15		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T205	2		T130	11		T161	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T124	2		T121	5		T128	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T29	4		T117	12		T165	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T67	11		T128	2		T215	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T132	4		T52	12		T27	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	9		T124	8		T129	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T19	11		T220	9		T224	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T261	12		T193	9		T262	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T65	3		T219	7		T259	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T139	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T131	8		T259	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T159	1		T254	3		T263	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T70	1		T264	1		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T29	10		T56	1		T126	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	4		T12	1		T14	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	15		T25	14		T49	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T16	10		T117	1		T22	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	1		T15	2		T116	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T19	3		T174	1		T120	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T2	2		T11	3		T58	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	1		T17	6		T144	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T122	4		T115	1		T120	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	1		T132	10		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T158	16		T56	1		T229	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T7	1		T12	1		T108	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T10	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T132	3		T117	1		T165	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	1		T13	1		T124	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	1		T29	6		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T7	11		T8	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T19	9		T123	1		T52	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T259	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T159	4		T254	7		T263	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T70	18		T265	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T29	2		T126	12		T248	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	2		T65	6		T66	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T13	12		T49	6		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T16	5		T117	11		T119	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T116	14		T124	9		T190	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T19	8		T174	3		T120	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1104	1			T2	20		T18	3		T20	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	7		T17	1		T211	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T115	15		T120	10		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	11		T132	13		T268	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T229	2		T129	11		T267	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T130	11		T161	10		T134	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	14		T121	5		T128	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T132	4		T117	12		T165	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T124	2		T67	11		T128	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T29	4		T159	5		T206	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T8	9		T124	8		T129	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	11		T52	12		T65	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2