Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21130

1

T1

8

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3398

1

T1

27

T7

13

T8

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18940

1

T1

23

T3

161

T5

55

auto[1]

5588

1

T1

12

T2

22

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	236	1			T13	1		T18	12		T29	12
values[0]	48	1			T122	8		T171	15		T269	11
values[1]	719	1			T1	12		T10	1		T12	1
values[2]	510	1			T8	10		T15	2		T116	28
values[3]	757	1			T19	20		T132	23		T22	2
values[4]	689	1			T14	13		T19	11		T16	15
values[5]	501	1			T7	2		T13	1		T122	4
values[6]	624	1			T123	1		T124	18		T53	12
values[7]	623	1			T1	8		T10	1		T13	27
values[8]	2615	1			T2	22		T11	3		T12	1
values[9]	1001	1			T1	15		T7	17		T12	1
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	629	1			T1	12		T8	10		T122	8
values[1]	599	1			T15	2		T116	28		T132	23
values[2]	742	1			T14	13		T19	20		T16	15
values[3]	701	1			T19	11		T124	15		T120	33
values[4]	508	1			T7	2		T13	1		T122	4
values[5]	623	1			T13	27		T118	1		T53	12
values[6]	2519	1			T1	8		T2	22		T10	1
values[7]	787	1			T7	11		T12	1		T14	13
values[8]	751	1			T7	6		T12	1		T13	1
values[9]	232	1			T1	15		T18	12		T130	27
minimum	16437	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T132	5		T147	1		T238	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T1	12		T8	10		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T116	15		T199	1		T212	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	1		T132	14		T53	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T120	1		T214	1		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	1		T19	12		T16	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T124	10		T120	16		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T19	9		T158	1		T64	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T13	1		T17	5		T115	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	2		T122	1		T117	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	13		T118	1		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T53	1		T229	6		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T1	8		T2	22		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T117	13		T124	3		T127	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	1		T14	1		T121	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	1		T144	1		T174	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T7	3		T29	6		T115	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	1		T13	1		T29	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T248	15		T250	1		T187	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T1	15		T18	4		T130	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16132	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T10	1		T211	12		T53	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T132	2		T238	3		T128	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T122	7		T108	15		T25	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T116	13		T212	13		T67	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T15	1		T132	9		T53	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T214	7		T234	4		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T14	12		T19	8		T16	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T124	5		T120	17		T158	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T19	2		T158	8		T68	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T17	2		T207	14		T231	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T122	3		T25	13		T124	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	14		T242	3		T207	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	11		T229	1		T234	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	961	1			T11	2		T58	16		T81	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T124	2		T127	9		T221	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	12		T51	1		T66	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	10		T144	11		T119	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	3		T29	4		T128	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T29	4		T65	7		T202	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T250	11		T187	7		T154	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T18	8		T130	14		T251	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T211	1		T53	3		T188	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T130	12		T270	1		T250	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T13	1		T18	4		T29	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T122	1		T171	1		T269	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T12	1		T132	5		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	12		T10	1		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T116	15		T199	1		T212	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T8	10		T15	1		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T120	1		T56	1		T67	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T19	12		T132	14		T22	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T124	10		T120	16		T214	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T14	1		T19	9		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	1		T17	5		T115	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	2		T122	1		T117	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T242	1		T200	1		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T123	1		T124	9		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	8		T10	1		T13	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T124	3		T127	5		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T2	22		T11	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T117	13		T174	4		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T7	3		T29	6		T115	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T1	15		T7	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T130	15		T250	11		T187	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T18	8		T29	4		T130	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T122	7		T171	14		T269	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T132	2		T238	3		T128	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T108	15		T25	14		T211	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T116	13		T212	13		T226	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T15	1		T53	13		T128	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T67	2		T27	1		T131	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T19	8		T132	9		T22	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T124	5		T120	17		T214	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	12		T19	2		T16	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T17	2		T158	15		T207	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T122	3		T25	13		T158	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T242	3		T207	15		T198	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T124	9		T53	11		T229	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	14		T189	2		T246	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T124	2		T127	9		T27	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T11	2		T14	12		T58	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T119	12		T59	2		T129	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T7	3		T29	4		T128	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	10		T144	11		T120	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T132	3		T147	1		T238	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T1	1		T8	1		T122	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T116	14		T199	1		T212	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	2		T132	10		T53	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T120	1		T214	8		T56	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T14	13		T19	9		T16	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T124	6		T120	18		T158	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T19	3		T158	9		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	1		T17	6		T115	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	2		T122	4		T117	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	15		T118	1		T242	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T53	12		T229	5		T234	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T1	1		T2	2		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T117	1		T124	3		T127	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	1		T14	13		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	11		T144	12		T174	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T7	4		T29	6		T115	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T12	1		T13	1		T29	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T248	1		T250	12		T187	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T1	1		T18	9		T130	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16264	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T10	1		T211	2		T53	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T132	4		T238	4		T257	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	11		T8	9		T129	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T116	14		T212	14		T67	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T132	13		T128	2		T215	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T219	7		T247	7		T266	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	11		T16	5		T52	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T124	9		T120	15		T64	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T19	8		T64	11		T68	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T17	1		T115	15		T206	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T117	11		T124	8		T49	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	12		T38	1		T253	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T229	2		T129	2		T255	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	924	1			T1	7		T2	20		T20	27
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T117	12		T124	2		T127	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T121	5		T66	2		T219	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T174	3		T119	9		T120	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	2		T29	4		T115	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	2		T65	3		T70	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T248	14		T187	6		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T1	14		T18	3		T130	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T38	12		T190	11		T183	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T211	11		T225	4		T271	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T130	16		T270	1		T250	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T13	1		T18	9		T29	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T122	8		T171	15		T269	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	1		T132	3		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T10	1		T108	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T116	14		T199	1		T212	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T8	1		T15	2		T53	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T120	1		T56	1		T67	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T19	9		T132	10		T22	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T124	6		T120	18		T214	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T14	13		T19	3		T16	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	1		T17	6		T115	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	2		T122	4		T117	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T242	4		T200	1		T207	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T123	1		T124	10		T53	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T10	1		T13	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T124	3		T127	10		T27	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T2	2		T11	3		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T117	1		T174	1		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T7	4		T29	6		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T1	1		T7	11		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T130	11		T187	6		T244	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T18	3		T29	2		T130	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T252	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T132	4		T238	4		T257	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	11		T211	11		T129	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T116	14		T212	14		T226	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T8	9		T128	2		T215	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T67	11		T226	2		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T19	11		T132	13		T52	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T124	9		T120	15		T27	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T19	8		T16	5		T64	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T17	1		T115	15		T64	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T117	11		T49	6		T205	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T38	1		T180	10		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T124	8		T229	2		T129	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	7		T13	12		T189	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T124	2		T127	4		T221	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T2	20		T20	27		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T117	12		T174	3		T119	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	2		T29	4		T115	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	14		T120	10		T65	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2