Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21227

1

T1

20

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3301

1

T1

15

T7

13

T8

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18676

1

T1

20

T3

160

T5

55

auto[1]

5852

1

T1

15

T2

22

T3

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	426	1			T3	1		T18	12		T24	1
values[0]	50	1			T207	10		T203	1		T272	1
values[1]	682	1			T13	27		T116	28		T22	2
values[2]	2570	1			T2	22		T11	3		T58	19
values[3]	430	1			T12	1		T13	1		T25	14
values[4]	815	1			T1	15		T16	15		T29	12
values[5]	667	1			T1	12		T19	20		T144	12
values[6]	581	1			T7	6		T10	1		T12	2
values[7]	608	1			T14	13		T108	16		T117	12
values[8]	548	1			T7	1		T8	10		T132	30
values[9]	1356	1			T1	8		T7	12		T10	1
minimum	15795	1			T3	160		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	846	1			T13	27		T17	7		T116	28
values[1]	2585	1			T2	22		T11	3		T58	19
values[2]	564	1			T1	15		T12	1		T16	15
values[3]	724	1			T13	1		T29	12		T144	12
values[4]	593	1			T1	12		T19	20		T119	22
values[5]	576	1			T7	6		T10	1		T12	2
values[6]	621	1			T108	16		T117	12		T53	12
values[7]	553	1			T7	1		T8	10		T14	13
values[8]	980	1			T1	8		T7	11		T10	1
values[9]	255	1			T7	1		T18	12		T115	16
minimum	16231	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T116	15		T124	10		T52	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	13		T17	5		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T2	22		T11	1		T58	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T122	1		T53	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T16	6		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T1	15		T212	15		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	1		T29	8		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T211	12		T120	16		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	12		T49	7		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T19	12		T119	10		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	3		T12	2		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	1		T120	11		T126	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T117	12		T238	5		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T108	1		T53	1		T165	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	1		T19	9		T117	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	1		T8	10		T132	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T1	8		T29	6		T124	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	1		T10	1		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T18	4		T115	16		T124	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T7	1		T118	1		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T273	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T116	13		T124	5		T52	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	14		T17	2		T22	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T11	2		T58	16		T81	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T122	3		T53	13		T67	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T16	9		T128	5		T207	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T212	13		T129	2		T189	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T29	4		T144	11		T226	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T211	1		T120	17		T128	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T49	2		T206	14		T274	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T19	8		T119	12		T158	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	3		T15	1		T214	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T120	3		T126	14		T229	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T238	3		T130	15		T220	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T108	15		T53	11		T131	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T14	12		T19	2		T130	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T132	11		T59	2		T66	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T29	4		T124	2		T158	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	10		T14	12		T122	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T18	8		T124	9		T275	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T246	5		T222	13		T239	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T273	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T3	1		T18	4		T24	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T200	1		T276	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T203	1		T204	15		T232	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T207	1		T272	1		T277	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T116	15		T124	10		T52	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	13		T22	1		T25	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T2	22		T11	1		T58	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T122	1		T17	5		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	1		T13	1		T25	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T64	15		T67	12		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T16	6		T29	8		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T1	15		T211	12		T120	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	12		T144	1		T174	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T19	12		T119	10		T120	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	3		T12	2		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	1		T158	1		T53	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	1		T117	12		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T108	1		T165	5		T126	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T56	1		T215	13		T220	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T8	10		T132	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T1	8		T19	9		T29	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T7	2		T10	1		T14	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15662	1			T3	160		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T18	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T276	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T204	12		T232	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T207	9		T277	1		T278	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T116	13		T124	5		T52	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	14		T22	1		T25	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	978	1			T11	2		T58	16		T81	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T122	3		T17	2		T27	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T25	13		T128	5		T209	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T67	2		T129	2		T152	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T16	9		T29	4		T226	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T211	1		T120	17		T212	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T144	11		T206	14		T180	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T19	8		T119	12		T120	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	3		T15	1		T49	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T158	8		T53	11		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T14	12		T214	7		T238	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T108	15		T126	14		T229	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T220	7		T209	6		T250	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T132	11		T66	6		T27	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T19	2		T29	4		T124	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T7	10		T14	12		T122	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T116	14		T124	6		T52	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	15		T17	6		T22	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T2	2		T11	3		T58	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T122	4		T53	14		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T12	1		T16	10		T234	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T1	1		T212	14		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T29	10		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T211	2		T120	18		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T1	1		T49	3		T56	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T19	9		T119	13		T158	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	4		T12	2		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	1		T120	4		T126	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T117	1		T238	4		T200	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T108	16		T53	12		T165	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T14	13		T19	3		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	1		T8	1		T132	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T1	1		T29	6		T124	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T7	11		T10	1		T14	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T18	9		T115	1		T124	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T7	1		T118	1		T200	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T273	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T116	14		T124	9		T52	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	12		T17	1		T64	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T2	20		T20	27		T141	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T64	14		T67	11		T27	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T16	5		T128	1		T215	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	14		T212	14		T129	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T29	2		T226	14		T248	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T211	11		T120	15		T128	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	11		T49	6		T206	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T19	11		T119	9		T65	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	2		T115	4		T174	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T120	10		T126	12		T229	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T117	11		T238	4		T130	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T165	1		T279	6		T280	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T19	8		T117	12		T215	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	9		T132	17		T121	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T1	7		T29	4		T124	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T64	11		T226	2		T129	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T18	3		T115	15		T124	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T246	2		T222	10		T239	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T273	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	419	1			T3	1		T18	9		T24	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T200	1		T276	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T203	1		T204	13		T232	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T207	10		T272	1		T277	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T116	14		T124	6		T52	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	15		T22	2		T25	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T2	2		T11	3		T58	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T122	4		T17	6		T123	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T13	1		T25	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T64	1		T67	3		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	10		T29	10		T234	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T1	1		T211	2		T120	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T144	12		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T19	9		T119	13		T120	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	4		T12	2		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	1		T158	9		T53	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	13		T117	1		T214	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T108	16		T165	4		T126	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T56	1		T215	1		T220	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	1		T8	1		T132	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	428	1			T1	1		T19	3		T29	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T7	12		T10	1		T14	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15795	1			T3	160		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T18	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T204	14		T232	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T116	14		T124	9		T52	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	12		T64	8		T65	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	915	1			T2	20		T20	27		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T17	1		T27	7		T129	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T128	1		T159	4		T38	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T64	14		T67	11		T129	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T16	5		T29	2		T226	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	14		T211	11		T120	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	11		T174	3		T206	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T19	11		T119	9		T120	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	2		T115	4		T49	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T205	2		T125	14		T179	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T117	11		T238	4		T130	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T165	1		T126	12		T229	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T215	12		T220	9		T237	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	9		T132	17		T121	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T1	7		T19	8		T29	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T64	11		T226	2		T129	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2