Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21406

1

T1

15

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3122

1

T1

20

T7

8

T12

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19131

1

T3

161

T5

55

T6

12

auto[1]

5397

1

T1

35

T2

22

T7

7

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	170	1			T123	1		T53	4		T65	11
values[0]	15	1			T159	5		T265	10		-	-
values[1]	713	1			T7	6		T12	1		T14	13
values[2]	626	1			T13	27		T16	15		T117	12
values[3]	659	1			T13	1		T15	2		T19	11
values[4]	2921	1			T1	20		T2	22		T11	3
values[5]	503	1			T7	1		T12	1		T17	7
values[6]	681	1			T115	16		T108	16		T214	8
values[7]	627	1			T1	15		T117	13		T121	6
values[8]	618	1			T7	1		T10	2		T13	1
values[9]	790	1			T7	11		T8	10		T12	1
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	712	1			T7	6		T117	12		T22	2
values[1]	555	1			T13	28		T16	15		T25	14
values[2]	751	1			T15	2		T18	12		T19	11
values[3]	2866	1			T1	20		T2	22		T11	3
values[4]	444	1			T7	1		T12	1		T132	23
values[5]	777	1			T1	15		T115	16		T214	8
values[6]	571	1			T7	1		T29	10		T117	13
values[7]	632	1			T10	2		T13	1		T19	20
values[8]	664	1			T7	11		T8	10		T12	1
values[9]	162	1			T14	13		T260	1		T65	11
minimum	16394	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T56	1		T126	13		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	3		T117	12		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T13	14		T25	1		T49	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T16	6		T119	10		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T15	1		T18	4		T116	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T19	9		T174	4		T120	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T2	22		T11	1		T58	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	20		T17	5		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T120	11		T149	1		T220	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T7	1		T12	1		T132	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	15		T115	16		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T214	1		T238	1		T130	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T124	3		T121	6		T234	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T29	6		T117	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	2		T13	1		T124	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T19	12		T132	5		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	1		T8	10		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T123	1		T52	13		T53	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T14	1		T260	1		T261	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T65	4		T219	8		T224	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16112	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T12	1		T14	1		T253	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T126	14		T231	10		T38	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	3		T22	1		T65	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T13	14		T25	13		T49	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T16	9		T119	12		T212	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	1		T18	8		T116	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T19	2		T120	17		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1101	1			T11	2		T58	16		T122	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T17	2		T144	11		T25	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T120	3		T220	5		T171	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T132	9		T108	15		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T158	15		T229	1		T188	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T214	7		T130	15		T217	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T124	2		T234	3		T128	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T29	4		T242	3		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T124	9		T67	2		T128	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T19	8		T132	2		T165	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	10		T122	7		T129	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T52	2		T53	3		T131	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T14	12		T261	10		T193	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T65	7		T219	8		T259	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	2		T15	1		T29	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T14	12		T253	5		T152	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T129	3		T200	1		T261	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T123	1		T53	1		T65	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T159	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T265	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T29	8		T56	1		T126	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T7	3		T12	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	13		T25	1		T49	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T16	6		T117	12		T119	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T15	1		T116	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T19	9		T174	4		T120	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1427	1			T2	22		T11	1		T58	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	20		T144	1		T25	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T120	11		T149	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T12	1		T17	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T115	16		T158	1		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T108	1		T214	1		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	15		T121	6		T188	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T117	13		T165	5		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T10	2		T13	1		T124	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	1		T29	6		T132	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	1		T8	10		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T19	12		T52	13		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T129	2		T261	10		T281	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T53	3		T65	7		T219	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T29	4		T126	14		T231	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	3		T14	12		T22	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	14		T25	13		T49	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T16	9		T119	12		T198	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T15	1		T116	13		T124	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T19	2		T120	17		T158	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1133	1			T11	2		T58	16		T122	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T144	11		T25	14		T211	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T120	3		T27	1		T220	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T17	2		T132	9		T187	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T158	15		T229	1		T218	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T108	15		T214	7		T130	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T188	2		T234	3		T128	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T242	3		T59	2		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T124	11		T67	2		T128	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T29	4		T132	2		T207	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	10		T14	12		T122	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T19	8		T52	2		T165	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T56	1		T126	15		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T7	4		T117	1		T22	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T13	16		T25	14		T49	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T16	10		T119	13		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T15	2		T18	9		T116	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T19	3		T174	1		T120	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1431	1			T2	2		T11	3		T58	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	2		T17	6		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T120	4		T149	1		T220	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	1		T12	1		T132	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	1		T115	1		T158	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T214	8		T238	1		T130	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T124	3		T121	1		T234	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	1		T29	6		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	2		T13	1		T124	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T19	9		T132	3		T165	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T7	11		T8	1		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T123	1		T52	3		T53	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T14	13		T260	1		T261	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T65	8		T219	9		T224	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16245	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T12	1		T14	13		T253	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T126	12		T159	4		T219	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	2		T117	11		T65	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T13	12		T49	6		T238	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T16	5		T119	9		T212	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T18	3		T116	14		T124	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T19	8		T174	3		T120	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1058	1			T2	20		T20	27		T115	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T1	18		T17	1		T211	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T120	10		T220	2		T267	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T132	13		T268	5		T187	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	14		T115	15		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T130	11		T161	10		T134	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T124	2		T121	5		T128	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	4		T117	12		T165	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T124	8		T67	11		T128	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T19	11		T132	4		T27	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	9		T129	2		T206	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T52	12		T220	9		T282	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T261	12		T193	9		T262	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T65	3		T219	7		T224	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T29	2		T248	14		T180	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T253	5		T152	12		T182	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T129	3		T200	1		T261	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T123	1		T53	4		T65	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T159	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T265	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	10		T56	1		T126	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	4		T12	1		T14	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	15		T25	14		T49	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T16	10		T117	1		T119	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	1		T15	2		T116	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T19	3		T174	1		T120	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1466	1			T2	2		T11	3		T58	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	2		T144	12		T25	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T120	4		T149	1		T27	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	1		T12	1		T17	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T115	1		T158	16		T56	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T108	16		T214	8		T238	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T121	1		T188	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T117	1		T165	4		T242	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	2		T13	1		T124	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	1		T29	6		T132	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T7	11		T8	1		T12	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T19	9		T52	3		T165	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T129	2		T261	12		T271	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T65	3		T219	7		T282	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T159	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T265	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T29	2		T126	12		T248	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	2		T212	14		T65	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	12		T49	6		T238	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T16	5		T117	11		T119	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T116	14		T124	9		T130	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T19	8		T174	3		T120	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1094	1			T2	20		T18	3		T20	27
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T1	18		T211	11		T125	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T120	10		T220	2		T267	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T17	1		T132	13		T268	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T115	15		T229	2		T248	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T130	11		T161	10		T134	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T1	14		T121	5		T128	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T117	12		T165	1		T64	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T124	10		T67	11		T128	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T29	4		T132	4		T159	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	9		T206	9		T179	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T19	11		T52	12		T27	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2