Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21394

1

T1

20

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3134

1

T1

15

T12

1

T13

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19119

1

T1

20

T3

161

T5

55

auto[1]

5409

1

T1

15

T2

22

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T199	1		T64	12		T283	13
values[0]	113	1			T127	14		T200	1		T284	11
values[1]	719	1			T10	1		T13	2		T108	16
values[2]	682	1			T14	13		T132	7		T119	22
values[3]	544	1			T1	15		T7	12		T15	2
values[4]	554	1			T7	6		T18	12		T19	11
values[5]	2527	1			T1	12		T2	22		T7	1
values[6]	662	1			T10	1		T13	27		T17	7
values[7]	540	1			T1	8		T122	4		T115	5
values[8]	725	1			T8	10		T12	1		T16	15
values[9]	1231	1			T12	1		T14	13		T19	20
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	998	1			T10	1		T13	2		T132	7
values[1]	722	1			T1	15		T7	11		T14	13
values[2]	495	1			T7	6		T19	11		T22	2
values[3]	2491	1			T1	12		T2	22		T7	1
values[4]	604	1			T7	1		T10	1		T122	8
values[5]	596	1			T13	27		T53	26		T260	1
values[6]	716	1			T1	8		T8	10		T122	4
values[7]	469	1			T12	1		T144	12		T117	13
values[8]	995	1			T12	1		T14	13		T19	20
values[9]	219	1			T211	13		T52	15		T270	1
minimum	16223	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T10	1		T13	1		T108	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	1		T132	5		T214	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	1		T15	1		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T1	15		T14	1		T119	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	3		T22	1		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T19	9		T53	1		T64	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	12		T2	22		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T132	14		T226	15		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	1		T10	1		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T122	1		T65	4		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	13		T53	1		T65	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T53	1		T260	1		T179	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	8		T8	10		T122	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T115	16		T120	1		T59	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T144	1		T117	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T158	1		T165	5		T128	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	1		T19	12		T29	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T12	1		T29	6		T117	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T211	12		T271	8		T193	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T52	13		T270	1		T210	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T199	1		T220	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T108	15		T120	17		T127	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T132	2		T214	7		T125	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	10		T15	1		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	12		T119	12		T165	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T7	3		T22	1		T285	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T19	2		T53	3		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T11	2		T58	16		T81	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T132	9		T226	14		T27	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T17	2		T67	2		T219	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T122	7		T65	7		T234	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	14		T53	11		T65	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T53	13		T253	6		T172	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T122	3		T16	9		T49	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T231	10		T209	4		T235	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T144	11		T25	13		T242	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T158	8		T128	1		T231	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	12		T19	8		T29	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T29	4		T25	14		T130	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T211	1		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T52	2		T210	17		T250	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T220	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T283	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T199	1		T64	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T127	5		T200	1		T284	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T286	10		T287	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T10	1		T13	1		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	1		T214	1		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T129	12		T201	1		T288	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T14	1		T132	5		T119	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	2		T15	1		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	15		T165	1		T64	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	3		T18	4		T174	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T19	9		T53	1		T65	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T1	12		T2	22		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T122	1		T132	14		T226	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	1		T13	13		T17	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T53	1		T234	1		T205	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	8		T122	1		T115	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T120	1		T260	1		T231	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	10		T12	1		T16	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T115	16		T158	1		T165	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T14	1		T19	12		T29	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T12	1		T29	6		T117	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T283	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T127	9		T284	10		T266	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T286	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T108	15		T120	17		T289	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T214	7		T220	7		T198	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T129	12		T261	10		T60	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T14	12		T132	2		T119	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T7	10		T15	1		T27	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T165	1		T66	6		T27	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	3		T18	8		T22	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T19	2		T53	3		T65	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T11	2		T58	16		T81	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T122	7		T132	9		T226	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	14		T17	2		T53	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T53	13		T234	3		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T122	3		T49	2		T65	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T231	10		T209	4		T266	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T16	9		T144	11		T25	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T158	8		T231	10		T280	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T14	12		T19	8		T29	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T29	4		T25	14		T52	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T10	1		T13	1		T108	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	1		T132	3		T214	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	11		T15	2		T123	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	1		T14	13		T119	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T7	4		T22	2		T133	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T19	3		T53	4		T64	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T1	1		T2	2		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T132	10		T226	15		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	1		T10	1		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T122	8		T65	8		T234	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	15		T53	12		T65	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T53	14		T260	1		T179	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T1	1		T8	1		T122	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T115	1		T120	1		T59	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	1		T144	12		T117	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T158	9		T165	4		T128	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T14	13		T19	9		T29	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T12	1		T29	6		T117	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T211	2		T271	1		T193	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T52	3		T270	1		T210	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T199	1		T220	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T120	15		T127	4		T206	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T132	4		T125	14		T248	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T129	11		T261	12		T224	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	14		T119	9		T66	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T7	2		T285	13		T290	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T19	8		T64	8		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T1	11		T2	20		T18	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T132	13		T226	14		T206	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T17	1		T121	5		T67	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T65	3		T205	2		T215	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	12		T65	6		T128	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T179	2		T253	2		T172	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	7		T8	9		T16	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T115	15		T59	1		T64	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T117	12		T68	2		T258	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T165	1		T128	2		T159	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T19	11		T29	2		T124	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T29	4		T117	11		T64	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T211	11		T271	7		T193	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T52	12		T134	12		T291	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T220	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T283	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T199	1		T64	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T127	10		T200	1		T284	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T286	12		T287	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T10	1		T13	1		T108	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	1		T214	8		T199	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T129	13		T201	1		T288	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T14	13		T132	3		T119	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	12		T15	2		T56	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T165	2		T64	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	4		T18	9		T174	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T19	3		T53	4		T65	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1294	1			T1	1		T2	2		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T122	8		T132	10		T226	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T10	1		T13	15		T17	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T53	14		T234	4		T205	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T122	4		T115	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T120	1		T260	1		T231	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T8	1		T12	1		T16	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T115	1		T158	9		T165	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T14	13		T19	9		T29	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	409	1			T12	1		T29	6		T117	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T283	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T64	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T127	4		T266	6		T204	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T286	9		T287	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T120	15		T179	11		T267	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T215	12		T220	9		T292	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T129	11		T206	2		T261	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T132	4		T119	9		T125	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T293	5		T294	9		T139	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T1	14		T64	8		T66	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	2		T18	3		T174	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T19	8		T65	3		T229	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	979	1			T1	11		T2	20		T20	27
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T132	13		T226	14		T215	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T13	12		T17	1		T128	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T205	2		T179	2		T246	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T1	7		T115	4		T49	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T179	10		T282	5		T266	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	9		T16	5		T117	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T115	15		T165	1		T59	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T19	11		T29	2		T124	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T29	4		T117	11		T52	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2