Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24528

1

T1

35

T2

22

T3

161

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21076

1

T1

8

T2

22

T3

161

auto[ADC_CTRL_FILTER_COND_OUT]

3452

1

T1

27

T7

2

T8

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19085

1

T1

35

T3

161

T5

55

auto[1]

5443

1

T2

22

T8

10

T10

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20608

1

T1

35

T2

22

T3

161

auto[1]

3920

1

T5

2

T7

13

T11

2

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T119	22		T192	9		-	-
values[0]	64	1			T165	5		T242	4		T209	7
values[1]	630	1			T1	8		T132	23		T144	12
values[2]	633	1			T12	2		T14	13		T115	16
values[3]	645	1			T7	6		T14	13		T16	15
values[4]	479	1			T19	20		T123	1		T51	2
values[5]	2601	1			T2	22		T7	1		T11	3
values[6]	734	1			T7	11		T13	1		T18	12
values[7]	536	1			T12	1		T13	1		T15	2
values[8]	826	1			T8	10		T10	1		T29	10
values[9]	1144	1			T1	27		T7	1		T10	1
minimum	16205	1			T3	161		T5	55		T6	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	851	1			T1	8		T115	16		T132	23
values[1]	584	1			T12	2		T14	13		T132	7
values[2]	598	1			T7	6		T14	13		T16	15
values[3]	2576	1			T2	22		T7	1		T11	3
values[4]	647	1			T13	1		T17	7		T29	12
values[5]	644	1			T7	11		T12	1		T18	12
values[6]	610	1			T8	10		T15	2		T115	5
values[7]	780	1			T7	1		T10	1		T13	1
values[8]	805	1			T1	27		T10	1		T13	27
values[9]	217	1			T119	22		T120	33		T200	1
minimum	16216	1			T3	161		T5	55		T6	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

3519

1

T1

32

T2

20

T7

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	8		T144	1		T211	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T115	16		T132	14		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T132	5		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T12	1		T14	1		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	3		T16	6		T117	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	1		T214	1		T215	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T2	22		T11	1		T58	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	1		T122	1		T19	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T17	5		T147	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T29	8		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	1		T18	4		T49	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	1		T19	9		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T115	5		T25	1		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	10		T15	1		T126	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	1		T13	1		T116	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	1		T29	6		T124	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	1		T13	13		T124	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	27		T188	4		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T119	10		T120	16		T179	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T200	1		T182	13		T239	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T295	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T144	11		T211	1		T218	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T132	9		T22	1		T124	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T132	2		T108	15		T158	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T14	12		T27	12		T128	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	3		T16	9		T51	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	12		T214	7		T296	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1050	1			T11	2		T58	16		T122	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T122	3		T19	8		T221	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T17	2		T129	2		T161	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	4		T158	15		T65	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	10		T18	8		T49	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T19	2		T25	13		T208	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T25	14		T53	3		T261	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	1		T126	14		T212	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T116	13		T205	2		T219	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	4		T124	9		T67	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T13	14		T124	5		T52	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T188	2		T27	1		T206	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T119	12		T120	17		T291	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T239	4		T297	13		T298	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T119	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T192	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T165	5		T280	11		T272	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T242	1		T209	1		T253	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	8		T144	1		T211	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T132	14		T22	1		T120	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T132	5		T59	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	1		T14	1		T115	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	3		T16	6		T108	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	1		T214	1		T221	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T123	1		T51	1		T53	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T19	12		T200	1		T215	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T2	22		T11	1		T58	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	1		T122	1		T29	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	1		T18	4		T65	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	1		T118	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	1		T115	5		T49	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	1		T15	1		T19	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	1		T116	15		T25	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T8	10		T29	6		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	1		T13	13		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T1	27		T7	1		T124	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16072	1			T3	161		T5	53		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T119	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T192	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T280	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T242	3		T209	6		T253	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T144	11		T211	1		T218	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T132	9		T22	1		T120	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T132	2		T59	2		T189	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T14	12		T124	2		T27	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	3		T16	9		T108	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T14	12		T214	7		T221	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T51	1		T53	13		T229	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T19	8		T296	8		T210	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T11	2		T58	16		T122	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T122	3		T29	4		T158	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	10		T18	8		T65	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T207	15		T208	4		T180	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T49	2		T53	3		T128	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T15	1		T19	2		T25	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T116	13		T25	14		T205	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T29	4		T128	1		T130	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	14		T124	5		T120	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T124	9		T67	2		T188	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T5	2		T15	1		T108	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T144	12		T211	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T115	1		T132	10		T22	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T132	3		T108	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	1		T14	13		T27	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T7	4		T16	10		T117	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	13		T214	8		T215	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T2	2		T11	3		T58	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	1		T122	4		T19	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T17	6		T147	1		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	1		T29	10		T158	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	11		T18	9		T49	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	1		T19	3		T118	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T115	1		T25	15		T53	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	1		T15	2		T126	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T10	1		T13	1		T116	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	1		T29	6		T124	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	1		T13	15		T124	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	2		T188	6		T27	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T119	13		T120	18		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T200	1		T182	1		T239	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	7		T211	11		T121	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T115	15		T132	13		T124	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T132	4		T174	3		T189	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T128	1		T130	10		T159	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	2		T16	5		T117	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T215	12		T152	10		T223	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T2	20		T20	27		T141	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T19	11		T117	11		T70	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T17	1		T129	2		T159	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	2		T64	8		T65	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T18	3		T49	6		T65	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T19	8		T219	8		T208	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T115	4		T59	1		T261	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	9		T126	12		T212	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T116	14		T205	2		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T29	4		T124	8		T67	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	12		T124	9		T52	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	25		T206	7		T253	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T119	9		T120	15		T179	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T182	12		T239	11		T297	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T295	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T119	13		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T192	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T165	4		T280	11		T272	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T242	4		T209	7		T253	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T1	1		T144	12		T211	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T132	10		T22	2		T120	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T12	1		T132	3		T59	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T12	1		T14	13		T115	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T7	4		T16	10		T108	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T14	13		T214	8		T221	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T123	1		T51	2		T53	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T19	9		T200	1		T215	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T2	2		T11	3		T58	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T122	4		T29	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	11		T18	9		T65	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	1		T118	1		T56	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	1		T115	1		T49	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T15	2		T19	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T10	1		T116	14		T25	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	1		T29	6		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T10	1		T13	15		T123	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T1	2		T7	1		T124	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16205	1			T3	161		T5	55		T6	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T119	9		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T192	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T165	1		T280	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T253	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T1	7		T211	11		T121	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T132	13		T120	10		T226	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T132	4		T64	11		T189	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T115	15		T124	2		T64	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	2		T16	5		T117	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T221	7		T159	11		T257	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T229	2		T181	14		T239	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T19	11		T215	12		T159	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T2	20		T20	27		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T29	2		T117	11		T64	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T18	3		T65	3		T253	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T226	2		T129	12		T219	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T115	4		T49	6		T59	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T19	8		T126	12		T212	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T116	14		T205	2		T219	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T8	9		T29	4		T128	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	12		T124	9		T120	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T1	25		T124	8		T67	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21009

1

T1

3

T2

2

T3

161

auto[1]

auto[0]

3519

1

T1

32

T2

20

T7

2