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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.63 98.98 95.69 100.00 100.00 98.18 98.64 91.92


Total test records in report: 914
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T73 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.955342503 Mar 05 12:38:19 PM PST 24 Mar 05 12:38:21 PM PST 24 470042046 ps
T102 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4043007001 Mar 05 12:38:15 PM PST 24 Mar 05 12:38:18 PM PST 24 963096490 ps
T82 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.941194203 Mar 05 12:38:39 PM PST 24 Mar 05 12:38:41 PM PST 24 461097357 ps
T796 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2540303442 Mar 05 12:38:28 PM PST 24 Mar 05 12:38:29 PM PST 24 614748156 ps
T97 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2401141287 Mar 05 12:38:12 PM PST 24 Mar 05 12:38:14 PM PST 24 568421358 ps
T83 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1627683284 Mar 05 12:38:22 PM PST 24 Mar 05 12:38:24 PM PST 24 467842942 ps
T98 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3325238461 Mar 05 12:38:20 PM PST 24 Mar 05 12:38:21 PM PST 24 347894435 ps
T797 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2225645377 Mar 05 12:38:21 PM PST 24 Mar 05 12:38:23 PM PST 24 485708324 ps
T35 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2727594594 Mar 05 12:38:46 PM PST 24 Mar 05 12:38:58 PM PST 24 4147232136 ps
T103 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3910600125 Mar 05 12:38:03 PM PST 24 Mar 05 12:38:04 PM PST 24 781822564 ps
T36 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3367748115 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:39 PM PST 24 8334784426 ps
T798 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1085004774 Mar 05 12:38:12 PM PST 24 Mar 05 12:38:14 PM PST 24 299168451 ps
T37 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.76347086 Mar 05 12:38:07 PM PST 24 Mar 05 12:38:10 PM PST 24 1019834018 ps
T63 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3999302416 Mar 05 12:39:31 PM PST 24 Mar 05 12:39:34 PM PST 24 478033732 ps
T32 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1939086541 Mar 05 12:38:12 PM PST 24 Mar 05 12:38:19 PM PST 24 4345322494 ps
T799 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3941126539 Mar 05 12:38:05 PM PST 24 Mar 05 12:38:07 PM PST 24 446284652 ps
T800 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1356423404 Mar 05 12:38:39 PM PST 24 Mar 05 12:38:41 PM PST 24 351402073 ps
T801 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.420161625 Mar 05 12:38:18 PM PST 24 Mar 05 12:38:20 PM PST 24 312324895 ps
T104 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3805683449 Mar 05 12:38:22 PM PST 24 Mar 05 12:38:30 PM PST 24 9107381677 ps
T76 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3719925779 Mar 05 12:38:21 PM PST 24 Mar 05 12:38:22 PM PST 24 434947893 ps
T802 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2882108853 Mar 05 12:38:19 PM PST 24 Mar 05 12:38:22 PM PST 24 506623852 ps
T33 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1590894570 Mar 05 12:38:18 PM PST 24 Mar 05 12:38:27 PM PST 24 4856657266 ps
T803 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.4209909854 Mar 05 12:38:20 PM PST 24 Mar 05 12:38:21 PM PST 24 422916521 ps
T34 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1055835715 Mar 05 12:38:17 PM PST 24 Mar 05 12:38:24 PM PST 24 2294847570 ps
T804 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1278400494 Mar 05 12:38:28 PM PST 24 Mar 05 12:38:30 PM PST 24 294817550 ps
T99 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1114694283 Mar 05 12:38:32 PM PST 24 Mar 05 12:38:34 PM PST 24 516488351 ps
T100 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2345731907 Mar 05 12:38:16 PM PST 24 Mar 05 12:38:27 PM PST 24 5838962015 ps
T77 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1271806204 Mar 05 12:38:18 PM PST 24 Mar 05 12:38:20 PM PST 24 535863311 ps
T78 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.251082023 Mar 05 12:38:23 PM PST 24 Mar 05 12:38:25 PM PST 24 473001031 ps
T805 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2779324073 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:38 PM PST 24 485351519 ps
T110 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4071928942 Mar 05 12:38:22 PM PST 24 Mar 05 12:38:44 PM PST 24 8025726771 ps
T84 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1047567449 Mar 05 12:38:34 PM PST 24 Mar 05 12:38:35 PM PST 24 495699178 ps
T806 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.345569396 Mar 05 12:38:17 PM PST 24 Mar 05 12:38:20 PM PST 24 481814157 ps
T85 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4093862541 Mar 05 12:38:06 PM PST 24 Mar 05 12:38:35 PM PST 24 24528743211 ps
T101 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4033317049 Mar 05 12:38:14 PM PST 24 Mar 05 12:38:16 PM PST 24 400142010 ps
T807 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.966464302 Mar 05 12:38:06 PM PST 24 Mar 05 12:38:07 PM PST 24 320756454 ps
T86 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1401186228 Mar 05 12:38:21 PM PST 24 Mar 05 12:39:01 PM PST 24 50205885647 ps
T87 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4007136864 Mar 05 12:38:11 PM PST 24 Mar 05 12:38:15 PM PST 24 2386786799 ps
T808 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1120747309 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:44 PM PST 24 1919075727 ps
T106 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1226102243 Mar 05 12:38:21 PM PST 24 Mar 05 12:38:24 PM PST 24 504873721 ps
T809 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1811795999 Mar 05 12:38:24 PM PST 24 Mar 05 12:38:26 PM PST 24 283014281 ps
T810 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.609653101 Mar 05 12:38:31 PM PST 24 Mar 05 12:38:36 PM PST 24 4867900851 ps
T105 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3396561195 Mar 05 12:38:08 PM PST 24 Mar 05 12:38:11 PM PST 24 383187039 ps
T811 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1207847441 Mar 05 12:38:49 PM PST 24 Mar 05 12:38:51 PM PST 24 2091143474 ps
T109 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.165326850 Mar 05 12:38:09 PM PST 24 Mar 05 12:38:11 PM PST 24 392230693 ps
T812 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1071174929 Mar 05 12:38:16 PM PST 24 Mar 05 12:38:19 PM PST 24 404685598 ps
T325 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1967099422 Mar 05 12:38:27 PM PST 24 Mar 05 12:38:34 PM PST 24 8215876095 ps
T813 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1183518984 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:47 PM PST 24 4138684577 ps
T814 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3576977501 Mar 05 12:38:27 PM PST 24 Mar 05 12:38:28 PM PST 24 402603113 ps
T815 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3466458314 Mar 05 12:38:14 PM PST 24 Mar 05 12:38:20 PM PST 24 357728916 ps
T816 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1932304624 Mar 05 12:38:26 PM PST 24 Mar 05 12:38:27 PM PST 24 411470231 ps
T107 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4206509115 Mar 05 12:38:17 PM PST 24 Mar 05 12:38:20 PM PST 24 435349205 ps
T817 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2188155227 Mar 05 12:38:20 PM PST 24 Mar 05 12:38:22 PM PST 24 383093936 ps
T818 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3398619658 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:43 PM PST 24 493531631 ps
T819 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.169691089 Mar 05 12:38:23 PM PST 24 Mar 05 12:38:24 PM PST 24 456156741 ps
T820 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.820102820 Mar 05 12:38:34 PM PST 24 Mar 05 12:38:35 PM PST 24 409809374 ps
T821 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1927532057 Mar 05 12:38:12 PM PST 24 Mar 05 12:38:14 PM PST 24 373355089 ps
T326 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2300661012 Mar 05 12:38:05 PM PST 24 Mar 05 12:38:11 PM PST 24 8613414796 ps
T822 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.425648418 Mar 05 12:38:24 PM PST 24 Mar 05 12:38:25 PM PST 24 366746122 ps
T88 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1865640588 Mar 05 12:39:38 PM PST 24 Mar 05 12:39:41 PM PST 24 494147507 ps
T823 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2065953739 Mar 05 12:39:33 PM PST 24 Mar 05 12:39:35 PM PST 24 729854378 ps
T824 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.935557461 Mar 05 12:38:26 PM PST 24 Mar 05 12:38:33 PM PST 24 2789623504 ps
T89 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.937605473 Mar 05 12:38:12 PM PST 24 Mar 05 12:38:14 PM PST 24 486714942 ps
T825 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3041031002 Mar 05 12:39:26 PM PST 24 Mar 05 12:39:29 PM PST 24 597981994 ps
T329 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1658959775 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:41 PM PST 24 8692159492 ps
T826 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3385001354 Mar 05 12:38:38 PM PST 24 Mar 05 12:38:39 PM PST 24 509399377 ps
T827 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1510956759 Mar 05 12:38:29 PM PST 24 Mar 05 12:38:32 PM PST 24 551945244 ps
T828 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.815648922 Mar 05 12:38:33 PM PST 24 Mar 05 12:38:36 PM PST 24 359234426 ps
T327 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1271287477 Mar 05 12:38:24 PM PST 24 Mar 05 12:38:29 PM PST 24 8649695828 ps
T829 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.470405414 Mar 05 12:38:31 PM PST 24 Mar 05 12:38:33 PM PST 24 519994857 ps
T830 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1505805053 Mar 05 12:38:44 PM PST 24 Mar 05 12:38:47 PM PST 24 3650669099 ps
T831 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3661720846 Mar 05 12:38:20 PM PST 24 Mar 05 12:38:21 PM PST 24 489848244 ps
T832 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3861412214 Mar 05 12:38:32 PM PST 24 Mar 05 12:38:33 PM PST 24 303160293 ps
T833 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1147654633 Mar 05 12:38:25 PM PST 24 Mar 05 12:38:27 PM PST 24 527937283 ps
T834 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2247799615 Mar 05 12:38:11 PM PST 24 Mar 05 12:38:15 PM PST 24 546407360 ps
T90 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3090467457 Mar 05 12:38:09 PM PST 24 Mar 05 12:38:13 PM PST 24 875131930 ps
T835 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1846873047 Mar 05 12:38:14 PM PST 24 Mar 05 12:38:16 PM PST 24 642465702 ps
T836 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.626104465 Mar 05 12:38:14 PM PST 24 Mar 05 12:38:16 PM PST 24 486581237 ps
T330 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3256751869 Mar 05 12:38:05 PM PST 24 Mar 05 12:38:28 PM PST 24 7857891274 ps
T91 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1058005028 Mar 05 12:38:12 PM PST 24 Mar 05 12:38:14 PM PST 24 536039759 ps
T837 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2827015638 Mar 05 12:38:40 PM PST 24 Mar 05 12:38:42 PM PST 24 805661470 ps
T838 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2392912193 Mar 05 12:38:09 PM PST 24 Mar 05 12:38:12 PM PST 24 600222081 ps
T839 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.158623861 Mar 05 12:38:55 PM PST 24 Mar 05 12:38:56 PM PST 24 374151943 ps
T92 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3592680309 Mar 05 12:38:20 PM PST 24 Mar 05 12:38:21 PM PST 24 529260496 ps
T840 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4072517109 Mar 05 12:39:05 PM PST 24 Mar 05 12:39:07 PM PST 24 325037688 ps
T328 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2567402758 Mar 05 12:38:24 PM PST 24 Mar 05 12:38:41 PM PST 24 8631449453 ps
T841 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.864340958 Mar 05 12:38:31 PM PST 24 Mar 05 12:38:36 PM PST 24 4361831332 ps
T842 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4117543661 Mar 05 12:38:23 PM PST 24 Mar 05 12:38:25 PM PST 24 1384076795 ps
T843 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.686381540 Mar 05 12:38:07 PM PST 24 Mar 05 12:38:10 PM PST 24 4265816663 ps
T844 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2133438360 Mar 05 12:38:23 PM PST 24 Mar 05 12:38:25 PM PST 24 468351707 ps
T845 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3541928346 Mar 05 12:38:06 PM PST 24 Mar 05 12:38:09 PM PST 24 978190829 ps
T846 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3360516897 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:43 PM PST 24 525406960 ps
T847 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3454763695 Mar 05 12:38:11 PM PST 24 Mar 05 12:38:13 PM PST 24 1113981755 ps
T848 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.906608223 Mar 05 12:38:24 PM PST 24 Mar 05 12:38:29 PM PST 24 8701988400 ps
T849 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3552484870 Mar 05 12:38:08 PM PST 24 Mar 05 12:38:12 PM PST 24 4980887820 ps
T850 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3737482834 Mar 05 12:38:07 PM PST 24 Mar 05 12:38:08 PM PST 24 551708314 ps
T851 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.696350275 Mar 05 12:38:31 PM PST 24 Mar 05 12:38:33 PM PST 24 545125968 ps
T852 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1585646078 Mar 05 12:38:20 PM PST 24 Mar 05 12:38:21 PM PST 24 399509167 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1294044099 Mar 05 12:38:19 PM PST 24 Mar 05 12:38:23 PM PST 24 770809592 ps
T854 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3329968856 Mar 05 12:38:47 PM PST 24 Mar 05 12:38:48 PM PST 24 515125804 ps
T93 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4161820838 Mar 05 12:38:06 PM PST 24 Mar 05 12:38:09 PM PST 24 821203243 ps
T94 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.716252197 Mar 05 12:38:25 PM PST 24 Mar 05 12:38:27 PM PST 24 344412640 ps
T855 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1892770428 Mar 05 12:38:20 PM PST 24 Mar 05 12:38:21 PM PST 24 390891113 ps
T856 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2678182368 Mar 05 12:38:20 PM PST 24 Mar 05 12:38:23 PM PST 24 533764351 ps
T857 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3178635008 Mar 05 12:38:11 PM PST 24 Mar 05 12:38:13 PM PST 24 492598929 ps
T858 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2514280393 Mar 05 12:38:19 PM PST 24 Mar 05 12:38:24 PM PST 24 4188940363 ps
T859 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3907224282 Mar 05 12:38:28 PM PST 24 Mar 05 12:38:38 PM PST 24 2567821028 ps
T95 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.201885186 Mar 05 12:38:18 PM PST 24 Mar 05 12:38:22 PM PST 24 621816768 ps
T860 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1938547745 Mar 05 12:38:16 PM PST 24 Mar 05 12:38:35 PM PST 24 4492947572 ps
T861 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4254357516 Mar 05 12:38:17 PM PST 24 Mar 05 12:38:19 PM PST 24 407648717 ps
T862 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1658476092 Mar 05 12:38:10 PM PST 24 Mar 05 12:38:12 PM PST 24 452436498 ps
T863 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2378770963 Mar 05 12:38:19 PM PST 24 Mar 05 12:38:28 PM PST 24 2409286469 ps
T864 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1692599730 Mar 05 12:38:06 PM PST 24 Mar 05 12:38:09 PM PST 24 463482627 ps
T865 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1347663432 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:37 PM PST 24 374503873 ps
T866 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.291474526 Mar 05 12:38:23 PM PST 24 Mar 05 12:38:28 PM PST 24 4159237678 ps
T867 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.670638899 Mar 05 12:38:23 PM PST 24 Mar 05 12:38:24 PM PST 24 548594944 ps
T868 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1322548746 Mar 05 12:38:14 PM PST 24 Mar 05 12:38:17 PM PST 24 551654049 ps
T869 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4187302089 Mar 05 12:38:03 PM PST 24 Mar 05 12:38:05 PM PST 24 446339833 ps
T870 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3146352665 Mar 05 12:38:12 PM PST 24 Mar 05 12:38:14 PM PST 24 480557774 ps
T96 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2467825338 Mar 05 12:38:34 PM PST 24 Mar 05 12:38:35 PM PST 24 394262994 ps
T871 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3200712119 Mar 05 12:38:22 PM PST 24 Mar 05 12:38:24 PM PST 24 461272248 ps
T872 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2023108955 Mar 05 12:38:16 PM PST 24 Mar 05 12:38:19 PM PST 24 333206266 ps
T873 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3666184671 Mar 05 12:38:46 PM PST 24 Mar 05 12:38:48 PM PST 24 353117026 ps
T874 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3935156350 Mar 05 12:38:08 PM PST 24 Mar 05 12:38:10 PM PST 24 536653079 ps
T875 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.407835431 Mar 05 12:38:29 PM PST 24 Mar 05 12:38:30 PM PST 24 348979534 ps
T876 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3017849073 Mar 05 12:39:00 PM PST 24 Mar 05 12:39:02 PM PST 24 4344713545 ps
T877 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1911270325 Mar 05 12:38:33 PM PST 24 Mar 05 12:38:35 PM PST 24 367905227 ps
T878 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3769523790 Mar 05 12:38:36 PM PST 24 Mar 05 12:38:38 PM PST 24 673918568 ps
T879 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2687161093 Mar 05 12:38:05 PM PST 24 Mar 05 12:38:27 PM PST 24 8217290047 ps
T880 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3554796750 Mar 05 12:38:30 PM PST 24 Mar 05 12:38:35 PM PST 24 8805610196 ps
T881 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.89330838 Mar 05 12:38:33 PM PST 24 Mar 05 12:38:35 PM PST 24 393022274 ps
T882 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3117115303 Mar 05 12:38:38 PM PST 24 Mar 05 12:38:39 PM PST 24 401034121 ps
T883 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1423973099 Mar 05 12:38:25 PM PST 24 Mar 05 12:38:47 PM PST 24 8223743192 ps
T884 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1754555492 Mar 05 12:38:21 PM PST 24 Mar 05 12:38:23 PM PST 24 390027911 ps
T885 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3323435607 Mar 05 12:38:35 PM PST 24 Mar 05 12:38:37 PM PST 24 572240774 ps
T886 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2771331628 Mar 05 12:38:39 PM PST 24 Mar 05 12:38:40 PM PST 24 503009358 ps
T887 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1405400463 Mar 05 12:38:04 PM PST 24 Mar 05 12:38:29 PM PST 24 21894366606 ps
T888 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3995679176 Mar 05 12:38:31 PM PST 24 Mar 05 12:38:33 PM PST 24 622267638 ps
T889 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3304102062 Mar 05 12:38:14 PM PST 24 Mar 05 12:38:16 PM PST 24 362270707 ps
T890 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.20347599 Mar 05 12:38:28 PM PST 24 Mar 05 12:38:30 PM PST 24 305383701 ps
T891 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1429544785 Mar 05 12:38:08 PM PST 24 Mar 05 12:38:10 PM PST 24 460522320 ps
T892 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2774402771 Mar 05 12:38:16 PM PST 24 Mar 05 12:38:19 PM PST 24 359768815 ps
T893 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3765141970 Mar 05 12:38:17 PM PST 24 Mar 05 12:38:19 PM PST 24 431223523 ps
T894 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.187864832 Mar 05 12:38:37 PM PST 24 Mar 05 12:38:38 PM PST 24 349887104 ps
T895 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1038640508 Mar 05 12:38:07 PM PST 24 Mar 05 12:38:08 PM PST 24 455000879 ps
T896 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3018072126 Mar 05 12:38:28 PM PST 24 Mar 05 12:38:30 PM PST 24 344603753 ps
T897 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3109798690 Mar 05 12:38:32 PM PST 24 Mar 05 12:38:34 PM PST 24 517557395 ps
T898 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2367083615 Mar 05 12:38:08 PM PST 24 Mar 05 12:38:09 PM PST 24 388236012 ps
T899 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2299775774 Mar 05 12:38:07 PM PST 24 Mar 05 12:38:08 PM PST 24 420803169 ps
T900 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2967255114 Mar 05 12:38:39 PM PST 24 Mar 05 12:38:42 PM PST 24 615309043 ps
T901 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.301898777 Mar 05 12:38:32 PM PST 24 Mar 05 12:38:39 PM PST 24 2263400264 ps
T902 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2604083222 Mar 05 12:39:06 PM PST 24 Mar 05 12:41:47 PM PST 24 53122160517 ps
T903 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.623635344 Mar 05 12:38:41 PM PST 24 Mar 05 12:38:44 PM PST 24 613799943 ps
T904 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1330896719 Mar 05 12:38:38 PM PST 24 Mar 05 12:38:40 PM PST 24 583550216 ps
T905 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.320989439 Mar 05 12:38:32 PM PST 24 Mar 05 12:38:33 PM PST 24 371424532 ps
T906 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2331680829 Mar 05 12:38:17 PM PST 24 Mar 05 12:38:22 PM PST 24 4136891503 ps
T907 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.913280592 Mar 05 12:38:22 PM PST 24 Mar 05 12:38:25 PM PST 24 3746647613 ps
T908 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4176438296 Mar 05 12:38:29 PM PST 24 Mar 05 12:38:33 PM PST 24 4677084903 ps
T909 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2768688266 Mar 05 12:38:35 PM PST 24 Mar 05 12:38:37 PM PST 24 368715770 ps
T910 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.347364012 Mar 05 12:38:09 PM PST 24 Mar 05 12:38:33 PM PST 24 8122477409 ps
T911 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2057713470 Mar 05 12:38:31 PM PST 24 Mar 05 12:38:33 PM PST 24 477770744 ps
T912 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2062504462 Mar 05 12:38:08 PM PST 24 Mar 05 12:38:12 PM PST 24 1160351844 ps
T913 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3854160947 Mar 05 12:38:34 PM PST 24 Mar 05 12:38:36 PM PST 24 2265630084 ps
T914 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2311694812 Mar 05 12:38:08 PM PST 24 Mar 05 12:38:15 PM PST 24 8353404714 ps

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1106781900
Short name T7
Test name
Test status
Simulation time 685233478913 ps
CPU time 377.67 seconds
Started Mar 05 12:45:31 PM PST 24
Finished Mar 05 12:51:49 PM PST 24
Peak memory 201112 kb
Host smart-86cbc4f6-c5f3-4483-975f-232e9009942c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106781900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1106781900
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3073909844
Short name T3
Test name
Test status
Simulation time 108272480886 ps
CPU time 363.63 seconds
Started Mar 05 12:45:08 PM PST 24
Finished Mar 05 12:51:12 PM PST 24
Peak memory 201568 kb
Host smart-6fb629aa-1ac2-461d-981c-5a01f6cc612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073909844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3073909844
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3466958390
Short name T128
Test name
Test status
Simulation time 594072522585 ps
CPU time 475.96 seconds
Started Mar 05 12:45:47 PM PST 24
Finished Mar 05 12:53:44 PM PST 24
Peak memory 209796 kb
Host smart-ffacbab6-582e-4ac5-b6a9-44b8b6f59405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466958390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3466958390
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.53066127
Short name T15
Test name
Test status
Simulation time 9698454483 ps
CPU time 22.12 seconds
Started Mar 05 12:45:26 PM PST 24
Finished Mar 05 12:45:48 PM PST 24
Peak memory 201272 kb
Host smart-5fa448b5-b9d6-471a-96ab-ddb4cbe840d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53066127 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.53066127
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2803262435
Short name T13
Test name
Test status
Simulation time 492648406972 ps
CPU time 207.03 seconds
Started Mar 05 12:47:06 PM PST 24
Finished Mar 05 12:50:33 PM PST 24
Peak memory 201012 kb
Host smart-dfc25c66-7fd3-46d7-9024-06ab5d21973b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803262435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2803262435
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3326595093
Short name T27
Test name
Test status
Simulation time 627670556232 ps
CPU time 1351.88 seconds
Started Mar 05 12:46:11 PM PST 24
Finished Mar 05 01:08:43 PM PST 24
Peak memory 209708 kb
Host smart-c920c848-4d82-471a-a8fb-37a212955060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326595093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3326595093
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1004640627
Short name T130
Test name
Test status
Simulation time 486992294987 ps
CPU time 193.54 seconds
Started Mar 05 12:45:59 PM PST 24
Finished Mar 05 12:49:13 PM PST 24
Peak memory 201204 kb
Host smart-f69e4593-b347-49f8-9176-9082bb778ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004640627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1004640627
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.230762022
Short name T206
Test name
Test status
Simulation time 484297048283 ps
CPU time 528.75 seconds
Started Mar 05 12:46:41 PM PST 24
Finished Mar 05 12:55:30 PM PST 24
Peak memory 201200 kb
Host smart-ce18cc70-053b-404c-bcc8-7204adeb8fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230762022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.230762022
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2151737792
Short name T38
Test name
Test status
Simulation time 528156566750 ps
CPU time 422.06 seconds
Started Mar 05 12:45:32 PM PST 24
Finished Mar 05 12:52:34 PM PST 24
Peak memory 209660 kb
Host smart-7bc66414-246c-4517-a6d3-c48b5e4ec8a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151737792 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2151737792
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3522724470
Short name T53
Test name
Test status
Simulation time 491201168525 ps
CPU time 133.29 seconds
Started Mar 05 12:45:17 PM PST 24
Finished Mar 05 12:47:31 PM PST 24
Peak memory 201200 kb
Host smart-4b3e09c4-bd5e-4a9d-a17a-be72338a90d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522724470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3522724470
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1277113598
Short name T1
Test name
Test status
Simulation time 501978939222 ps
CPU time 1184.17 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 01:04:43 PM PST 24
Peak memory 201228 kb
Host smart-5aa6246c-9358-4386-ad8d-ee066a5ae9ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277113598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1277113598
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.229696718
Short name T19
Test name
Test status
Simulation time 330587229021 ps
CPU time 583.37 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:55:24 PM PST 24
Peak memory 201096 kb
Host smart-bfff0d16-dae5-41da-bd37-69ba027a88c5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229696718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.229696718
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.4257968365
Short name T46
Test name
Test status
Simulation time 3996697325 ps
CPU time 8.8 seconds
Started Mar 05 12:44:48 PM PST 24
Finished Mar 05 12:44:57 PM PST 24
Peak memory 216440 kb
Host smart-c321e1de-3673-4e2d-9441-7cf79c9d2505
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257968365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.4257968365
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2655514113
Short name T132
Test name
Test status
Simulation time 332131280159 ps
CPU time 727.74 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:57:17 PM PST 24
Peak memory 200996 kb
Host smart-b914fc5f-18b9-4287-9709-04d8f40ed3a1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655514113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2655514113
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2301428661
Short name T159
Test name
Test status
Simulation time 489211807330 ps
CPU time 283.51 seconds
Started Mar 05 12:45:29 PM PST 24
Finished Mar 05 12:50:13 PM PST 24
Peak memory 201196 kb
Host smart-53143682-e95b-4378-9114-3ec4859fd6b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301428661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2301428661
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3054088509
Short name T81
Test name
Test status
Simulation time 324573049758 ps
CPU time 641.61 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:56:22 PM PST 24
Peak memory 201180 kb
Host smart-0cea96aa-bbac-4e5b-aab0-3d513598fba6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054088509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3054088509
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.370169774
Short name T129
Test name
Test status
Simulation time 492935923397 ps
CPU time 299.17 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:50:46 PM PST 24
Peak memory 201204 kb
Host smart-086b4ecc-616d-4dda-bf96-6982e3494334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370169774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.370169774
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.1452334236
Short name T239
Test name
Test status
Simulation time 491465024851 ps
CPU time 325.17 seconds
Started Mar 05 12:45:59 PM PST 24
Finished Mar 05 12:51:24 PM PST 24
Peak memory 201108 kb
Host smart-80a0d483-878d-4a2a-b391-975d8ade7663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452334236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.1452334236
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4093862541
Short name T85
Test name
Test status
Simulation time 24528743211 ps
CPU time 29.2 seconds
Started Mar 05 12:38:06 PM PST 24
Finished Mar 05 12:38:35 PM PST 24
Peak memory 200776 kb
Host smart-91a7eb00-3e97-4d15-9441-cf4083a0641d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093862541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4093862541
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1052921683
Short name T253
Test name
Test status
Simulation time 484523908899 ps
CPU time 954.79 seconds
Started Mar 05 12:45:16 PM PST 24
Finished Mar 05 01:01:11 PM PST 24
Peak memory 201116 kb
Host smart-15cbbc14-4f92-41d3-8a1d-ec6190bdd29a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052921683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1052921683
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.76347086
Short name T37
Test name
Test status
Simulation time 1019834018 ps
CPU time 2.2 seconds
Started Mar 05 12:38:07 PM PST 24
Finished Mar 05 12:38:10 PM PST 24
Peak memory 200828 kb
Host smart-4ae1f0ff-840a-444d-9bf3-7932dd479d81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76347086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.76347086
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1665085045
Short name T187
Test name
Test status
Simulation time 888035214297 ps
CPU time 1735.1 seconds
Started Mar 05 12:46:38 PM PST 24
Finished Mar 05 01:15:34 PM PST 24
Peak memory 209892 kb
Host smart-e336b3b2-f63e-4615-9308-e9283b762875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665085045 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1665085045
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4211925464
Short name T171
Test name
Test status
Simulation time 496830818910 ps
CPU time 275.78 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:49:37 PM PST 24
Peak memory 201200 kb
Host smart-5a4555ed-4f66-4a43-9f76-6cd0e66f5d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211925464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4211925464
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1847554963
Short name T203
Test name
Test status
Simulation time 333336457875 ps
CPU time 799.88 seconds
Started Mar 05 12:45:15 PM PST 24
Finished Mar 05 12:58:35 PM PST 24
Peak memory 201196 kb
Host smart-83ec5536-7f3c-43e1-a6e4-a2f172dc1ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847554963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1847554963
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3664229135
Short name T266
Test name
Test status
Simulation time 491679987695 ps
CPU time 1215.2 seconds
Started Mar 05 12:45:02 PM PST 24
Finished Mar 05 01:05:17 PM PST 24
Peak memory 201128 kb
Host smart-0735fb9d-bdd7-4904-b59f-cc705251fdf5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664229135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3664229135
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1150046802
Short name T162
Test name
Test status
Simulation time 494581070706 ps
CPU time 328.69 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:50:50 PM PST 24
Peak memory 201196 kb
Host smart-02883740-e1dc-4a67-95b8-07e4f6ca79c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150046802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1150046802
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3973312945
Short name T124
Test name
Test status
Simulation time 493334968879 ps
CPU time 246.99 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:49:41 PM PST 24
Peak memory 201116 kb
Host smart-17eec9a2-cbf6-4830-899f-ba64a4d39d51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973312945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3973312945
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2203038905
Short name T181
Test name
Test status
Simulation time 325577328213 ps
CPU time 199.83 seconds
Started Mar 05 12:45:08 PM PST 24
Finished Mar 05 12:48:28 PM PST 24
Peak memory 201144 kb
Host smart-636ab233-0aa5-4c71-b9ba-fe53360650c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203038905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2203038905
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1770877556
Short name T215
Test name
Test status
Simulation time 489740075321 ps
CPU time 1131.46 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 01:03:51 PM PST 24
Peak memory 201256 kb
Host smart-1698b48f-bb3d-4612-b87d-08820688c280
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770877556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1770877556
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.239407676
Short name T146
Test name
Test status
Simulation time 164681768228 ps
CPU time 346.45 seconds
Started Mar 05 12:45:23 PM PST 24
Finished Mar 05 12:51:09 PM PST 24
Peak memory 201120 kb
Host smart-3da47385-da63-4f1a-83fc-e44071923bcb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239407676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.239407676
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2832678237
Short name T207
Test name
Test status
Simulation time 487247550061 ps
CPU time 579 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:55:19 PM PST 24
Peak memory 201200 kb
Host smart-c7f8abb9-9f06-4cd8-97a4-3c7bffe2d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832678237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2832678237
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1833253499
Short name T43
Test name
Test status
Simulation time 371217979 ps
CPU time 0.79 seconds
Started Mar 05 12:45:16 PM PST 24
Finished Mar 05 12:45:20 PM PST 24
Peak memory 200876 kb
Host smart-e6fd3455-52d9-466e-8c3e-4a2b7a512e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833253499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1833253499
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3958324161
Short name T39
Test name
Test status
Simulation time 275727741861 ps
CPU time 174.92 seconds
Started Mar 05 12:47:26 PM PST 24
Finished Mar 05 12:50:21 PM PST 24
Peak memory 209872 kb
Host smart-902c93d4-4bbc-45de-928e-40dcb56541eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958324161 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3958324161
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3178794753
Short name T262
Test name
Test status
Simulation time 485361797568 ps
CPU time 276.36 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:50:04 PM PST 24
Peak memory 201072 kb
Host smart-6bfe02b9-1ae9-4723-9727-5a90aa749031
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178794753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3178794753
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3207164876
Short name T280
Test name
Test status
Simulation time 220334383090 ps
CPU time 153.65 seconds
Started Mar 05 12:46:14 PM PST 24
Finished Mar 05 12:48:48 PM PST 24
Peak memory 201120 kb
Host smart-5f8f320e-50fc-4704-b40c-334b04328819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207164876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3207164876
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3904639494
Short name T259
Test name
Test status
Simulation time 527654115842 ps
CPU time 312.21 seconds
Started Mar 05 12:45:50 PM PST 24
Finished Mar 05 12:51:03 PM PST 24
Peak memory 201204 kb
Host smart-cec77c99-7eb5-4740-860d-807d732e362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904639494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3904639494
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1271287477
Short name T327
Test name
Test status
Simulation time 8649695828 ps
CPU time 4.86 seconds
Started Mar 05 12:38:24 PM PST 24
Finished Mar 05 12:38:29 PM PST 24
Peak memory 200848 kb
Host smart-831d414a-bc30-4cbb-99b2-54c080f1f984
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271287477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1271287477
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.4271586790
Short name T119
Test name
Test status
Simulation time 163309590182 ps
CPU time 381.37 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 12:51:57 PM PST 24
Peak memory 201204 kb
Host smart-5accd3b8-1d81-406c-88d4-b80ed4831f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271586790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4271586790
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1412408868
Short name T29
Test name
Test status
Simulation time 240075501109 ps
CPU time 133.48 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:47:34 PM PST 24
Peak memory 209464 kb
Host smart-34fe6fb7-3473-41eb-a163-ddd9af7c8693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412408868 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1412408868
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.1055835715
Short name T34
Test name
Test status
Simulation time 2294847570 ps
CPU time 5.74 seconds
Started Mar 05 12:38:17 PM PST 24
Finished Mar 05 12:38:24 PM PST 24
Peak memory 199884 kb
Host smart-65a6f135-1bba-4f3b-923d-acbcd6f15b0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055835715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.1055835715
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1811328645
Short name T232
Test name
Test status
Simulation time 327699980401 ps
CPU time 822.67 seconds
Started Mar 05 12:44:38 PM PST 24
Finished Mar 05 12:58:21 PM PST 24
Peak memory 201196 kb
Host smart-0deaf8aa-227c-43f6-96c5-b735027b0b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811328645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1811328645
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.1557815931
Short name T115
Test name
Test status
Simulation time 354123820207 ps
CPU time 802.58 seconds
Started Mar 05 12:46:01 PM PST 24
Finished Mar 05 12:59:25 PM PST 24
Peak memory 201116 kb
Host smart-1b4c1e86-fdbb-4b2f-8a09-2129134b1b57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557815931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.1557815931
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.4206509115
Short name T107
Test name
Test status
Simulation time 435349205 ps
CPU time 1.84 seconds
Started Mar 05 12:38:17 PM PST 24
Finished Mar 05 12:38:20 PM PST 24
Peak memory 200808 kb
Host smart-d5f5b2e6-4b6e-4f7b-adce-2b6da6ce8a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206509115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.4206509115
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1252445540
Short name T300
Test name
Test status
Simulation time 326850211243 ps
CPU time 767.17 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:58:20 PM PST 24
Peak memory 201184 kb
Host smart-5c7a09bc-e9fe-4457-8dd6-1819a394a5c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252445540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1252445540
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1050177451
Short name T18
Test name
Test status
Simulation time 166247444660 ps
CPU time 204.98 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:49:12 PM PST 24
Peak memory 201096 kb
Host smart-18d299f4-534b-4954-af35-215b00396d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050177451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1050177451
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.3833268209
Short name T220
Test name
Test status
Simulation time 356732918951 ps
CPU time 837.93 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:59:01 PM PST 24
Peak memory 201200 kb
Host smart-27f1ec30-7b3c-4773-b067-bee95855c3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833268209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.3833268209
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2807389244
Short name T225
Test name
Test status
Simulation time 328301576836 ps
CPU time 569.87 seconds
Started Mar 05 12:45:18 PM PST 24
Finished Mar 05 12:54:48 PM PST 24
Peak memory 201124 kb
Host smart-44041d94-12d7-45ff-a51f-0737ea855f95
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807389244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2807389244
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4153696042
Short name T265
Test name
Test status
Simulation time 502378243784 ps
CPU time 1150.12 seconds
Started Mar 05 12:45:13 PM PST 24
Finished Mar 05 01:04:23 PM PST 24
Peak memory 201060 kb
Host smart-3fef022f-937f-4acc-be64-3bbcc7f1bfa5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153696042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4153696042
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2130378127
Short name T211
Test name
Test status
Simulation time 167375209624 ps
CPU time 373.26 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:51:42 PM PST 24
Peak memory 201200 kb
Host smart-0b1621c0-da63-4f8a-8102-d36082c69005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130378127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2130378127
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1079672481
Short name T231
Test name
Test status
Simulation time 329970631574 ps
CPU time 382.33 seconds
Started Mar 05 12:45:34 PM PST 24
Finished Mar 05 12:51:57 PM PST 24
Peak memory 201316 kb
Host smart-dae620fc-3d4c-4617-8a1e-745183119634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079672481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1079672481
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3361700083
Short name T286
Test name
Test status
Simulation time 330217603132 ps
CPU time 548.93 seconds
Started Mar 05 12:45:49 PM PST 24
Finished Mar 05 12:54:58 PM PST 24
Peak memory 201092 kb
Host smart-e5999a59-f2e2-405e-8634-48db22a99dd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361700083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3361700083
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3423571955
Short name T25
Test name
Test status
Simulation time 443789328310 ps
CPU time 1317.14 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 01:07:06 PM PST 24
Peak memory 209708 kb
Host smart-b86a5ac1-a303-4d21-afd8-41da0283acf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423571955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3423571955
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1912182435
Short name T192
Test name
Test status
Simulation time 70436270302 ps
CPU time 96.07 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:46:45 PM PST 24
Peak memory 217388 kb
Host smart-b337c84e-482b-4a51-bd74-ad87293a1f88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912182435 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1912182435
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.795941470
Short name T263
Test name
Test status
Simulation time 498961707785 ps
CPU time 1138.2 seconds
Started Mar 05 12:45:04 PM PST 24
Finished Mar 05 01:04:02 PM PST 24
Peak memory 201204 kb
Host smart-ee7bfddc-0644-4aac-9751-54ae9c988a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795941470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.795941470
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1743794993
Short name T137
Test name
Test status
Simulation time 117960438002 ps
CPU time 74.07 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:46:23 PM PST 24
Peak memory 201180 kb
Host smart-b13e0f74-1cd7-4dc4-b83e-287e9e5efbd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743794993 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1743794993
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1462368982
Short name T283
Test name
Test status
Simulation time 324656732822 ps
CPU time 751.59 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:57:53 PM PST 24
Peak memory 201144 kb
Host smart-78dc727d-eded-48e4-aa0f-9224e3608541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462368982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1462368982
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1021815171
Short name T310
Test name
Test status
Simulation time 318989022895 ps
CPU time 223.81 seconds
Started Mar 05 12:45:31 PM PST 24
Finished Mar 05 12:49:15 PM PST 24
Peak memory 201040 kb
Host smart-14b6b334-5c0f-4e01-9888-f369f433e31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021815171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1021815171
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.720668175
Short name T216
Test name
Test status
Simulation time 331503878339 ps
CPU time 200.09 seconds
Started Mar 05 12:46:30 PM PST 24
Finished Mar 05 12:49:50 PM PST 24
Peak memory 201080 kb
Host smart-99128f14-0edd-4255-8961-8c60e211f616
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720668175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.720668175
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1125177079
Short name T301
Test name
Test status
Simulation time 511038452083 ps
CPU time 315.27 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:50:35 PM PST 24
Peak memory 201060 kb
Host smart-082f4aec-cef3-4c0f-9658-856bc5da96c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125177079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1125177079
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2853543576
Short name T210
Test name
Test status
Simulation time 499342100801 ps
CPU time 1130.01 seconds
Started Mar 05 12:45:26 PM PST 24
Finished Mar 05 01:04:16 PM PST 24
Peak memory 201112 kb
Host smart-f1faf91e-005e-4819-9071-c839daa3f987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853543576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2853543576
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3903851743
Short name T273
Test name
Test status
Simulation time 170580767212 ps
CPU time 395.27 seconds
Started Mar 05 12:45:34 PM PST 24
Finished Mar 05 12:52:09 PM PST 24
Peak memory 201156 kb
Host smart-ca8d0827-c93e-4020-bcbf-cb0a57995df3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903851743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3903851743
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.721450540
Short name T335
Test name
Test status
Simulation time 118419404762 ps
CPU time 663.97 seconds
Started Mar 05 12:44:53 PM PST 24
Finished Mar 05 12:56:02 PM PST 24
Peak memory 201568 kb
Host smart-b2c5d379-7b07-4ac2-9ae8-2614c58ad484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721450540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.721450540
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1387954322
Short name T312
Test name
Test status
Simulation time 334755502846 ps
CPU time 162.56 seconds
Started Mar 05 12:45:53 PM PST 24
Finished Mar 05 12:48:36 PM PST 24
Peak memory 201180 kb
Host smart-c77f75b5-c5ed-4ebe-bdbe-958b60685d0f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387954322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1387954322
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.747195750
Short name T14
Test name
Test status
Simulation time 328651357797 ps
CPU time 350.41 seconds
Started Mar 05 12:45:53 PM PST 24
Finished Mar 05 12:51:44 PM PST 24
Peak memory 201136 kb
Host smart-f2a30040-e813-4ef7-9efb-47df4805a20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747195750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.747195750
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.761819285
Short name T64
Test name
Test status
Simulation time 501229497509 ps
CPU time 795.87 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:58:17 PM PST 24
Peak memory 201140 kb
Host smart-320a34d8-e429-4fd7-8452-89175feb71ba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761819285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.761819285
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.36400750
Short name T295
Test name
Test status
Simulation time 336762380886 ps
CPU time 649.52 seconds
Started Mar 05 12:45:47 PM PST 24
Finished Mar 05 12:56:37 PM PST 24
Peak memory 201128 kb
Host smart-eb82b527-fb38-430c-b379-c235c89d6f51
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36400750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_w
akeup.36400750
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2429436536
Short name T276
Test name
Test status
Simulation time 492625199444 ps
CPU time 1116.47 seconds
Started Mar 05 12:44:54 PM PST 24
Finished Mar 05 01:03:31 PM PST 24
Peak memory 201196 kb
Host smart-e5f2e3f0-2057-462b-ad68-74ae0985958b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429436536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2429436536
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.187075338
Short name T249
Test name
Test status
Simulation time 163702074263 ps
CPU time 100.24 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 12:46:40 PM PST 24
Peak memory 201068 kb
Host smart-20612ce4-b5e7-49e8-98d7-a969e7bb4a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187075338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.187075338
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2005559452
Short name T552
Test name
Test status
Simulation time 96303687267 ps
CPU time 352.7 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:51:02 PM PST 24
Peak memory 201512 kb
Host smart-3a8a5043-e811-4f78-bc8d-7b164abba44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005559452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2005559452
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2558361507
Short name T302
Test name
Test status
Simulation time 484135163802 ps
CPU time 856.06 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:59:31 PM PST 24
Peak memory 201180 kb
Host smart-ee410b22-3dfd-40ef-be16-e6f1e890a1b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558361507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2558361507
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.976854965
Short name T252
Test name
Test status
Simulation time 22357500204 ps
CPU time 106.8 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:46:57 PM PST 24
Peak memory 209724 kb
Host smart-c2b49649-6bec-461e-9336-fc5cb8f4c7e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976854965 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.976854965
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.344406655
Short name T339
Test name
Test status
Simulation time 93673248414 ps
CPU time 371.04 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:51:25 PM PST 24
Peak memory 201568 kb
Host smart-3a2a3f22-ee3b-44e3-a628-8d3c69f4992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344406655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.344406655
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2885050093
Short name T308
Test name
Test status
Simulation time 170265713206 ps
CPU time 214.56 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:48:55 PM PST 24
Peak memory 201200 kb
Host smart-2c682f59-c810-4f23-8ce3-30811d4b3d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885050093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2885050093
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.69895661
Short name T299
Test name
Test status
Simulation time 293831410801 ps
CPU time 551.82 seconds
Started Mar 05 12:45:48 PM PST 24
Finished Mar 05 12:55:00 PM PST 24
Peak memory 209660 kb
Host smart-1713d67f-14d4-4ee4-a4fd-dcaf3d84a983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69895661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.69895661
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3897980359
Short name T316
Test name
Test status
Simulation time 50560940715 ps
CPU time 33.4 seconds
Started Mar 05 12:44:54 PM PST 24
Finished Mar 05 12:45:28 PM PST 24
Peak memory 201324 kb
Host smart-5e0feb2b-a9e6-4ccb-ba1b-5841ca040d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897980359 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3897980359
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1658959775
Short name T329
Test name
Test status
Simulation time 8692159492 ps
CPU time 5.3 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:41 PM PST 24
Peak memory 200776 kb
Host smart-59585c3e-ebbd-459c-bb5b-5ad760fec7e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658959775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1658959775
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1652952322
Short name T28
Test name
Test status
Simulation time 132207996377 ps
CPU time 682.94 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 12:56:28 PM PST 24
Peak memory 201572 kb
Host smart-ce16b081-d65f-4594-89a6-49524b63be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652952322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1652952322
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2026861644
Short name T282
Test name
Test status
Simulation time 181833563523 ps
CPU time 65.21 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:46:15 PM PST 24
Peak memory 201052 kb
Host smart-35c0bf5a-d100-45bd-9a3a-b81918d20995
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026861644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2026861644
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.4034522142
Short name T174
Test name
Test status
Simulation time 179391485574 ps
CPU time 118.52 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:47:19 PM PST 24
Peak memory 201144 kb
Host smart-a7595c29-33a6-4f0c-9471-83e12148d393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034522142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.4034522142
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3568627845
Short name T338
Test name
Test status
Simulation time 92572983328 ps
CPU time 408.96 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:52:09 PM PST 24
Peak memory 201508 kb
Host smart-b3dc8a6e-468d-4610-872a-50349bfc6386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568627845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3568627845
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4053633488
Short name T320
Test name
Test status
Simulation time 166951061675 ps
CPU time 385.17 seconds
Started Mar 05 12:45:45 PM PST 24
Finished Mar 05 12:52:11 PM PST 24
Peak memory 201028 kb
Host smart-f877984c-a9ab-48f0-8c9d-be508185c3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053633488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4053633488
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3837455101
Short name T26
Test name
Test status
Simulation time 140137470077 ps
CPU time 542.71 seconds
Started Mar 05 12:45:22 PM PST 24
Finished Mar 05 12:54:25 PM PST 24
Peak memory 201512 kb
Host smart-329a0b55-0c76-4347-8141-2f90fe72b153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837455101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3837455101
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1057651297
Short name T139
Test name
Test status
Simulation time 497505974999 ps
CPU time 190.3 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 12:48:46 PM PST 24
Peak memory 201096 kb
Host smart-604c4aa0-0cce-4515-9bcc-99bf7906f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057651297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1057651297
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2889396156
Short name T75
Test name
Test status
Simulation time 179713794636 ps
CPU time 204.35 seconds
Started Mar 05 12:45:41 PM PST 24
Finished Mar 05 12:49:05 PM PST 24
Peak memory 209432 kb
Host smart-f9d69350-2c97-4e10-8623-34210b35bb36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889396156 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2889396156
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.211985737
Short name T344
Test name
Test status
Simulation time 436256323298 ps
CPU time 1218.42 seconds
Started Mar 05 12:45:56 PM PST 24
Finished Mar 05 01:06:15 PM PST 24
Peak memory 211260 kb
Host smart-893307dd-eb7a-45e2-a13a-7cf6c897be3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211985737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
211985737
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1923322083
Short name T227
Test name
Test status
Simulation time 332606205389 ps
CPU time 775.77 seconds
Started Mar 05 12:45:48 PM PST 24
Finished Mar 05 12:58:44 PM PST 24
Peak memory 201136 kb
Host smart-13af3ff9-cad7-414d-a80c-f57482395352
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923322083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1923322083
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.670389725
Short name T577
Test name
Test status
Simulation time 501887073222 ps
CPU time 320.43 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 12:51:05 PM PST 24
Peak memory 201104 kb
Host smart-c5bd15c6-0ab2-4bfb-bda6-f1d818163b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670389725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
670389725
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2371336525
Short name T337
Test name
Test status
Simulation time 87735254998 ps
CPU time 291.79 seconds
Started Mar 05 12:47:25 PM PST 24
Finished Mar 05 12:52:17 PM PST 24
Peak memory 201516 kb
Host smart-bd29c3f6-5a6a-4726-8f97-cb2b64ce2262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371336525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2371336525
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1207979605
Short name T278
Test name
Test status
Simulation time 41121759727 ps
CPU time 81.95 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:46:23 PM PST 24
Peak memory 209820 kb
Host smart-66574696-5968-4817-9f1a-e864134ac17b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207979605 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1207979605
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1294044099
Short name T853
Test name
Test status
Simulation time 770809592 ps
CPU time 3.07 seconds
Started Mar 05 12:38:19 PM PST 24
Finished Mar 05 12:38:23 PM PST 24
Peak memory 200704 kb
Host smart-f4672679-df5a-48fb-9e06-e6ad917251f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294044099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1294044099
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1405400463
Short name T887
Test name
Test status
Simulation time 21894366606 ps
CPU time 24.4 seconds
Started Mar 05 12:38:04 PM PST 24
Finished Mar 05 12:38:29 PM PST 24
Peak memory 200772 kb
Host smart-93d21129-3a38-455b-b69f-be7627b38839
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405400463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1405400463
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.4161820838
Short name T93
Test name
Test status
Simulation time 821203243 ps
CPU time 2.81 seconds
Started Mar 05 12:38:06 PM PST 24
Finished Mar 05 12:38:09 PM PST 24
Peak memory 200564 kb
Host smart-20599c86-56e8-48f9-b6e7-ab8efe1e4725
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161820838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.4161820838
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3935156350
Short name T874
Test name
Test status
Simulation time 536653079 ps
CPU time 1.94 seconds
Started Mar 05 12:38:08 PM PST 24
Finished Mar 05 12:38:10 PM PST 24
Peak memory 200688 kb
Host smart-b8c70184-9d44-4fec-8b0d-3f96ba3e0aaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935156350 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3935156350
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4033317049
Short name T101
Test name
Test status
Simulation time 400142010 ps
CPU time 0.83 seconds
Started Mar 05 12:38:14 PM PST 24
Finished Mar 05 12:38:16 PM PST 24
Peak memory 200516 kb
Host smart-a562e98a-dd9c-44b4-b127-2fbc5e390b3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033317049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4033317049
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1927532057
Short name T821
Test name
Test status
Simulation time 373355089 ps
CPU time 1.06 seconds
Started Mar 05 12:38:12 PM PST 24
Finished Mar 05 12:38:14 PM PST 24
Peak memory 200500 kb
Host smart-d291648c-6fe6-4b3d-9ac5-0663f65ce4dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927532057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1927532057
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2378770963
Short name T863
Test name
Test status
Simulation time 2409286469 ps
CPU time 8.3 seconds
Started Mar 05 12:38:19 PM PST 24
Finished Mar 05 12:38:28 PM PST 24
Peak memory 200492 kb
Host smart-1f43cb32-60d9-4402-8dc5-4420ab8c501f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378770963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2378770963
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1322548746
Short name T868
Test name
Test status
Simulation time 551654049 ps
CPU time 2.59 seconds
Started Mar 05 12:38:14 PM PST 24
Finished Mar 05 12:38:17 PM PST 24
Peak memory 200844 kb
Host smart-d6eac354-d7d3-4209-bb71-a68a54866ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322548746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1322548746
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2300661012
Short name T326
Test name
Test status
Simulation time 8613414796 ps
CPU time 6.39 seconds
Started Mar 05 12:38:05 PM PST 24
Finished Mar 05 12:38:11 PM PST 24
Peak memory 200724 kb
Host smart-38e36023-bd3d-4efa-a779-2706c9fb5479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300661012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2300661012
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3910600125
Short name T103
Test name
Test status
Simulation time 781822564 ps
CPU time 1.62 seconds
Started Mar 05 12:38:03 PM PST 24
Finished Mar 05 12:38:04 PM PST 24
Peak memory 200628 kb
Host smart-2f49a3a3-2b4f-4e37-92bb-7dd60ec61339
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910600125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3910600125
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3090467457
Short name T90
Test name
Test status
Simulation time 875131930 ps
CPU time 2.69 seconds
Started Mar 05 12:38:09 PM PST 24
Finished Mar 05 12:38:13 PM PST 24
Peak memory 200652 kb
Host smart-3e170a3b-d7d5-4145-ae90-32e42c51c4d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090467457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3090467457
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2133438360
Short name T844
Test name
Test status
Simulation time 468351707 ps
CPU time 1.3 seconds
Started Mar 05 12:38:23 PM PST 24
Finished Mar 05 12:38:25 PM PST 24
Peak memory 200708 kb
Host smart-cce57231-7e94-4a64-88b5-530282c3d540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133438360 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2133438360
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3304102062
Short name T889
Test name
Test status
Simulation time 362270707 ps
CPU time 1.58 seconds
Started Mar 05 12:38:14 PM PST 24
Finished Mar 05 12:38:16 PM PST 24
Peak memory 200516 kb
Host smart-6f15d3d3-faee-4e84-87da-4f7a30fb85f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304102062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3304102062
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3941126539
Short name T799
Test name
Test status
Simulation time 446284652 ps
CPU time 1.07 seconds
Started Mar 05 12:38:05 PM PST 24
Finished Mar 05 12:38:07 PM PST 24
Peak memory 200336 kb
Host smart-d3555617-ac73-417c-a273-af3455bb6874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941126539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3941126539
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.935557461
Short name T824
Test name
Test status
Simulation time 2789623504 ps
CPU time 6.53 seconds
Started Mar 05 12:38:26 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200548 kb
Host smart-b1a63d89-f26f-4937-8f19-4f5ab1c74716
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935557461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.935557461
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1226102243
Short name T106
Test name
Test status
Simulation time 504873721 ps
CPU time 2.16 seconds
Started Mar 05 12:38:21 PM PST 24
Finished Mar 05 12:38:24 PM PST 24
Peak memory 200748 kb
Host smart-7bacd2b5-0da1-4930-9292-028bf49f7b2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226102243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1226102243
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3554796750
Short name T880
Test name
Test status
Simulation time 8805610196 ps
CPU time 5.17 seconds
Started Mar 05 12:38:30 PM PST 24
Finished Mar 05 12:38:35 PM PST 24
Peak memory 200780 kb
Host smart-ca66f1d8-1ac1-4bf5-89ed-49b9278ffcf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554796750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3554796750
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3719925779
Short name T76
Test name
Test status
Simulation time 434947893 ps
CPU time 1.04 seconds
Started Mar 05 12:38:21 PM PST 24
Finished Mar 05 12:38:22 PM PST 24
Peak memory 200488 kb
Host smart-083e44ce-88ed-44cf-82b5-e66941bc141b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719925779 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3719925779
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.937605473
Short name T89
Test name
Test status
Simulation time 486714942 ps
CPU time 1.89 seconds
Started Mar 05 12:38:12 PM PST 24
Finished Mar 05 12:38:14 PM PST 24
Peak memory 200512 kb
Host smart-7db63daf-7130-4bcc-9594-2f7b6972463b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937605473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.937605473
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1754555492
Short name T884
Test name
Test status
Simulation time 390027911 ps
CPU time 1.14 seconds
Started Mar 05 12:38:21 PM PST 24
Finished Mar 05 12:38:23 PM PST 24
Peak memory 200476 kb
Host smart-1fc21e6f-6cbb-4825-9abd-c7050c9e5997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754555492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1754555492
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.686381540
Short name T843
Test name
Test status
Simulation time 4265816663 ps
CPU time 2.26 seconds
Started Mar 05 12:38:07 PM PST 24
Finished Mar 05 12:38:10 PM PST 24
Peak memory 200664 kb
Host smart-5293ceb6-0a45-4e71-85ed-e86dfb04b18a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686381540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.686381540
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.165326850
Short name T109
Test name
Test status
Simulation time 392230693 ps
CPU time 1.57 seconds
Started Mar 05 12:38:09 PM PST 24
Finished Mar 05 12:38:11 PM PST 24
Peak memory 200812 kb
Host smart-39a11ad6-36b5-4632-b6ad-d4ffef78c6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165326850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.165326850
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.955342503
Short name T73
Test name
Test status
Simulation time 470042046 ps
CPU time 1.36 seconds
Started Mar 05 12:38:19 PM PST 24
Finished Mar 05 12:38:21 PM PST 24
Peak memory 200708 kb
Host smart-c268bf48-832f-4d59-bc11-9377ad7d752d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955342503 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.955342503
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1058005028
Short name T91
Test name
Test status
Simulation time 536039759 ps
CPU time 1.34 seconds
Started Mar 05 12:38:12 PM PST 24
Finished Mar 05 12:38:14 PM PST 24
Peak memory 200496 kb
Host smart-64b41f3f-f36a-4064-8445-fcbb643c12ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058005028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1058005028
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3466458314
Short name T815
Test name
Test status
Simulation time 357728916 ps
CPU time 1.02 seconds
Started Mar 05 12:38:14 PM PST 24
Finished Mar 05 12:38:20 PM PST 24
Peak memory 200352 kb
Host smart-17edc974-9132-4745-84a7-33b4ab3cd7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466458314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3466458314
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.864340958
Short name T841
Test name
Test status
Simulation time 4361831332 ps
CPU time 4.35 seconds
Started Mar 05 12:38:31 PM PST 24
Finished Mar 05 12:38:36 PM PST 24
Peak memory 200804 kb
Host smart-397c8d4a-3d4b-4ca2-9748-033b1a7a3398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864340958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.864340958
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2678182368
Short name T856
Test name
Test status
Simulation time 533764351 ps
CPU time 2.19 seconds
Started Mar 05 12:38:20 PM PST 24
Finished Mar 05 12:38:23 PM PST 24
Peak memory 200484 kb
Host smart-5425637a-157c-47a6-95e8-3a042bdec9b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678182368 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2678182368
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.670638899
Short name T867
Test name
Test status
Simulation time 548594944 ps
CPU time 1.08 seconds
Started Mar 05 12:38:23 PM PST 24
Finished Mar 05 12:38:24 PM PST 24
Peak memory 198808 kb
Host smart-ff62ed08-036c-42ca-a93a-1d94e34d084a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670638899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.670638899
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1658476092
Short name T862
Test name
Test status
Simulation time 452436498 ps
CPU time 1.62 seconds
Started Mar 05 12:38:10 PM PST 24
Finished Mar 05 12:38:12 PM PST 24
Peak memory 200412 kb
Host smart-3587c877-750b-4a5b-be6c-a72010b465c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658476092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1658476092
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3178635008
Short name T857
Test name
Test status
Simulation time 492598929 ps
CPU time 1.52 seconds
Started Mar 05 12:38:11 PM PST 24
Finished Mar 05 12:38:13 PM PST 24
Peak memory 200828 kb
Host smart-24b24560-b521-4543-aad0-331548b22638
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178635008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3178635008
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.347364012
Short name T910
Test name
Test status
Simulation time 8122477409 ps
CPU time 23.08 seconds
Started Mar 05 12:38:09 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200812 kb
Host smart-e7a41625-9239-4b53-9558-4e10a90fef5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347364012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.347364012
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1846873047
Short name T835
Test name
Test status
Simulation time 642465702 ps
CPU time 1.19 seconds
Started Mar 05 12:38:14 PM PST 24
Finished Mar 05 12:38:16 PM PST 24
Peak memory 200692 kb
Host smart-907ea14c-e4a3-42b5-8c63-25d11fb1c7e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846873047 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1846873047
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.716252197
Short name T94
Test name
Test status
Simulation time 344412640 ps
CPU time 1.54 seconds
Started Mar 05 12:38:25 PM PST 24
Finished Mar 05 12:38:27 PM PST 24
Peak memory 200448 kb
Host smart-31703538-01f8-4903-8bd1-20b2251ec73e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716252197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.716252197
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1085004774
Short name T798
Test name
Test status
Simulation time 299168451 ps
CPU time 0.99 seconds
Started Mar 05 12:38:12 PM PST 24
Finished Mar 05 12:38:14 PM PST 24
Peak memory 200348 kb
Host smart-5a8fb4ac-8cc8-439a-9068-c624fb18bfa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085004774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1085004774
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.609653101
Short name T810
Test name
Test status
Simulation time 4867900851 ps
CPU time 4.51 seconds
Started Mar 05 12:38:31 PM PST 24
Finished Mar 05 12:38:36 PM PST 24
Peak memory 200784 kb
Host smart-466f260b-39ec-4f8f-9aa4-f254beaba3b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609653101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.609653101
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2065953739
Short name T823
Test name
Test status
Simulation time 729854378 ps
CPU time 2.27 seconds
Started Mar 05 12:39:33 PM PST 24
Finished Mar 05 12:39:35 PM PST 24
Peak memory 216936 kb
Host smart-5fb77814-bfeb-4497-93f3-f44fccbf7de1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065953739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2065953739
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4176438296
Short name T908
Test name
Test status
Simulation time 4677084903 ps
CPU time 4.14 seconds
Started Mar 05 12:38:29 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200856 kb
Host smart-efa8bbee-0af1-43a5-bcfc-1c93325004b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176438296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.4176438296
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3041031002
Short name T825
Test name
Test status
Simulation time 597981994 ps
CPU time 2.15 seconds
Started Mar 05 12:39:26 PM PST 24
Finished Mar 05 12:39:29 PM PST 24
Peak memory 200460 kb
Host smart-6e0fcd84-1554-40e8-9676-e691b688a675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041031002 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3041031002
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3200712119
Short name T871
Test name
Test status
Simulation time 461272248 ps
CPU time 1.88 seconds
Started Mar 05 12:38:22 PM PST 24
Finished Mar 05 12:38:24 PM PST 24
Peak memory 200512 kb
Host smart-42e5947b-93cc-4a38-a207-bc36dcddfd45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200712119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3200712119
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2225645377
Short name T797
Test name
Test status
Simulation time 485708324 ps
CPU time 0.98 seconds
Started Mar 05 12:38:21 PM PST 24
Finished Mar 05 12:38:23 PM PST 24
Peak memory 200488 kb
Host smart-51afef51-d02a-4838-88d4-0a81fcbcf70a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225645377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2225645377
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.301898777
Short name T901
Test name
Test status
Simulation time 2263400264 ps
CPU time 7.5 seconds
Started Mar 05 12:38:32 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 200640 kb
Host smart-28fb7b4b-416d-4724-af1c-60cd81b47f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301898777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.301898777
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.251082023
Short name T78
Test name
Test status
Simulation time 473001031 ps
CPU time 1.98 seconds
Started Mar 05 12:38:23 PM PST 24
Finished Mar 05 12:38:25 PM PST 24
Peak memory 199604 kb
Host smart-eb61e416-5268-4698-8d55-0826a6174961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251082023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.251082023
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2567402758
Short name T328
Test name
Test status
Simulation time 8631449453 ps
CPU time 16.62 seconds
Started Mar 05 12:38:24 PM PST 24
Finished Mar 05 12:38:41 PM PST 24
Peak memory 200748 kb
Host smart-14d59f35-cfee-4fd8-83eb-45c04f87ecc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567402758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2567402758
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1911270325
Short name T877
Test name
Test status
Simulation time 367905227 ps
CPU time 1.67 seconds
Started Mar 05 12:38:33 PM PST 24
Finished Mar 05 12:38:35 PM PST 24
Peak memory 200928 kb
Host smart-90a143b8-00bc-4d1a-89a0-c01c4da2284b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911270325 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1911270325
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1038640508
Short name T895
Test name
Test status
Simulation time 455000879 ps
CPU time 0.93 seconds
Started Mar 05 12:38:07 PM PST 24
Finished Mar 05 12:38:08 PM PST 24
Peak memory 200504 kb
Host smart-9486d664-fbc7-4ee8-8364-3cf0ea714891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038640508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1038640508
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2299775774
Short name T899
Test name
Test status
Simulation time 420803169 ps
CPU time 1.17 seconds
Started Mar 05 12:38:07 PM PST 24
Finished Mar 05 12:38:08 PM PST 24
Peak memory 200380 kb
Host smart-7293eff0-8c3a-4052-88d8-a6f3e49b0ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299775774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2299775774
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1120747309
Short name T808
Test name
Test status
Simulation time 1919075727 ps
CPU time 2.86 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:44 PM PST 24
Peak memory 200568 kb
Host smart-5046cf8b-e571-423f-96f6-b77c9884d7fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120747309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1120747309
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4117543661
Short name T842
Test name
Test status
Simulation time 1384076795 ps
CPU time 1.74 seconds
Started Mar 05 12:38:23 PM PST 24
Finished Mar 05 12:38:25 PM PST 24
Peak memory 199096 kb
Host smart-d21bddf7-a59c-4e7c-bb38-9c090e833c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117543661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4117543661
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.906608223
Short name T848
Test name
Test status
Simulation time 8701988400 ps
CPU time 5.32 seconds
Started Mar 05 12:38:24 PM PST 24
Finished Mar 05 12:38:29 PM PST 24
Peak memory 200672 kb
Host smart-41de7b80-e508-460f-a834-4f786799e908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906608223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.906608223
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3323435607
Short name T885
Test name
Test status
Simulation time 572240774 ps
CPU time 1.12 seconds
Started Mar 05 12:38:35 PM PST 24
Finished Mar 05 12:38:37 PM PST 24
Peak memory 200652 kb
Host smart-bdfe8fe1-43d2-416b-b972-330b46d1338f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323435607 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3323435607
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3325238461
Short name T98
Test name
Test status
Simulation time 347894435 ps
CPU time 0.87 seconds
Started Mar 05 12:38:20 PM PST 24
Finished Mar 05 12:38:21 PM PST 24
Peak memory 200516 kb
Host smart-f04b1123-a6ec-4336-9e94-2bae2a8af535
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325238461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3325238461
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.820102820
Short name T820
Test name
Test status
Simulation time 409809374 ps
CPU time 0.79 seconds
Started Mar 05 12:38:34 PM PST 24
Finished Mar 05 12:38:35 PM PST 24
Peak memory 200360 kb
Host smart-63255e91-e020-45be-a82f-d91679acfd67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820102820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.820102820
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.3017849073
Short name T876
Test name
Test status
Simulation time 4344713545 ps
CPU time 2.62 seconds
Started Mar 05 12:39:00 PM PST 24
Finished Mar 05 12:39:02 PM PST 24
Peak memory 200996 kb
Host smart-2205197d-c140-42db-addc-b71a9414cd1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017849073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.3017849073
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3769523790
Short name T878
Test name
Test status
Simulation time 673918568 ps
CPU time 2.34 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:38 PM PST 24
Peak memory 209056 kb
Host smart-1ed7b9b2-e8ae-4768-89b4-523a836a18e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769523790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3769523790
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1967099422
Short name T325
Test name
Test status
Simulation time 8215876095 ps
CPU time 7.16 seconds
Started Mar 05 12:38:27 PM PST 24
Finished Mar 05 12:38:34 PM PST 24
Peak memory 200476 kb
Host smart-f730c986-a6ee-4541-a740-fe02e6cb4844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967099422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1967099422
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1147654633
Short name T833
Test name
Test status
Simulation time 527937283 ps
CPU time 1.3 seconds
Started Mar 05 12:38:25 PM PST 24
Finished Mar 05 12:38:27 PM PST 24
Peak memory 200928 kb
Host smart-84221827-307f-49ed-a084-cafa8aa1807e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147654633 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1147654633
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2467825338
Short name T96
Test name
Test status
Simulation time 394262994 ps
CPU time 0.88 seconds
Started Mar 05 12:38:34 PM PST 24
Finished Mar 05 12:38:35 PM PST 24
Peak memory 200488 kb
Host smart-7d887f4b-550d-4166-9316-fbf86973b82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467825338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2467825338
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3576977501
Short name T814
Test name
Test status
Simulation time 402603113 ps
CPU time 0.86 seconds
Started Mar 05 12:38:27 PM PST 24
Finished Mar 05 12:38:28 PM PST 24
Peak memory 200340 kb
Host smart-89040c57-3623-4c8c-b417-761fc013bb0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576977501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3576977501
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1207847441
Short name T811
Test name
Test status
Simulation time 2091143474 ps
CPU time 1.95 seconds
Started Mar 05 12:38:49 PM PST 24
Finished Mar 05 12:38:51 PM PST 24
Peak memory 200576 kb
Host smart-5eb7146c-fd14-45da-9730-aa504d516264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207847441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1207847441
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2392912193
Short name T838
Test name
Test status
Simulation time 600222081 ps
CPU time 2.87 seconds
Started Mar 05 12:38:09 PM PST 24
Finished Mar 05 12:38:12 PM PST 24
Peak memory 209972 kb
Host smart-28b35aaf-a57a-4006-a72d-3d590f6e0a60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392912193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2392912193
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3552484870
Short name T849
Test name
Test status
Simulation time 4980887820 ps
CPU time 3.42 seconds
Started Mar 05 12:38:08 PM PST 24
Finished Mar 05 12:38:12 PM PST 24
Peak memory 200812 kb
Host smart-074931ee-7112-4862-9e86-fed90ae900e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552484870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3552484870
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3666184671
Short name T873
Test name
Test status
Simulation time 353117026 ps
CPU time 1.57 seconds
Started Mar 05 12:38:46 PM PST 24
Finished Mar 05 12:38:48 PM PST 24
Peak memory 200712 kb
Host smart-cac19c92-ec16-42dd-a2fa-9a37deb1c2ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666184671 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3666184671
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2057713470
Short name T911
Test name
Test status
Simulation time 477770744 ps
CPU time 0.98 seconds
Started Mar 05 12:38:31 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200488 kb
Host smart-1989dad1-677a-404d-89ae-88868be7395b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057713470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2057713470
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2540303442
Short name T796
Test name
Test status
Simulation time 614748156 ps
CPU time 0.75 seconds
Started Mar 05 12:38:28 PM PST 24
Finished Mar 05 12:38:29 PM PST 24
Peak memory 200356 kb
Host smart-cacfd478-fabb-48f2-a75b-684f3360fb6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540303442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2540303442
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.291474526
Short name T866
Test name
Test status
Simulation time 4159237678 ps
CPU time 5.74 seconds
Started Mar 05 12:38:23 PM PST 24
Finished Mar 05 12:38:28 PM PST 24
Peak memory 200688 kb
Host smart-751457f0-a4f9-4174-8390-be0bafd782e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291474526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.291474526
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2967255114
Short name T900
Test name
Test status
Simulation time 615309043 ps
CPU time 2.68 seconds
Started Mar 05 12:38:39 PM PST 24
Finished Mar 05 12:38:42 PM PST 24
Peak memory 200824 kb
Host smart-d15511eb-0dfa-4b35-ad99-085ffb43261d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967255114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2967255114
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2727594594
Short name T35
Test name
Test status
Simulation time 4147232136 ps
CPU time 10.94 seconds
Started Mar 05 12:38:46 PM PST 24
Finished Mar 05 12:38:58 PM PST 24
Peak memory 200820 kb
Host smart-ff43be58-0d06-4647-971b-4998955f88b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727594594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2727594594
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.623635344
Short name T903
Test name
Test status
Simulation time 613799943 ps
CPU time 2.29 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:44 PM PST 24
Peak memory 200704 kb
Host smart-3617c04c-af34-4161-ba7b-447c033c4ae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623635344 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.623635344
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.941194203
Short name T82
Test name
Test status
Simulation time 461097357 ps
CPU time 1.25 seconds
Started Mar 05 12:38:39 PM PST 24
Finished Mar 05 12:38:41 PM PST 24
Peak memory 200492 kb
Host smart-3d4f88be-1ba8-4c4f-bacf-f787f9a1283d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941194203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.941194203
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3398619658
Short name T818
Test name
Test status
Simulation time 493531631 ps
CPU time 1.16 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:43 PM PST 24
Peak memory 200492 kb
Host smart-2f7dc9eb-d9e9-4660-939b-ad42f0615fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398619658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3398619658
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1590894570
Short name T33
Test name
Test status
Simulation time 4856657266 ps
CPU time 4.04 seconds
Started Mar 05 12:38:18 PM PST 24
Finished Mar 05 12:38:27 PM PST 24
Peak memory 200484 kb
Host smart-5d6115de-709d-4718-948a-e8ea1b0d711b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590894570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1590894570
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3109798690
Short name T897
Test name
Test status
Simulation time 517557395 ps
CPU time 2.57 seconds
Started Mar 05 12:38:32 PM PST 24
Finished Mar 05 12:38:34 PM PST 24
Peak memory 200736 kb
Host smart-11ff64d1-299a-4121-b1eb-e12a13c907ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109798690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3109798690
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3367748115
Short name T36
Test name
Test status
Simulation time 8334784426 ps
CPU time 3.36 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 200848 kb
Host smart-2c464af7-be80-498d-9d0a-0a1a4b28f134
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367748115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3367748115
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.201885186
Short name T95
Test name
Test status
Simulation time 621816768 ps
CPU time 3.01 seconds
Started Mar 05 12:38:18 PM PST 24
Finished Mar 05 12:38:22 PM PST 24
Peak memory 200424 kb
Host smart-51ac7650-548b-484d-8de3-03490c92b4a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201885186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.201885186
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.4007136864
Short name T87
Test name
Test status
Simulation time 2386786799 ps
CPU time 3.77 seconds
Started Mar 05 12:38:11 PM PST 24
Finished Mar 05 12:38:15 PM PST 24
Peak memory 200792 kb
Host smart-68bfb96f-b04b-4743-a037-23b58bb29ca4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007136864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.4007136864
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2062504462
Short name T912
Test name
Test status
Simulation time 1160351844 ps
CPU time 3.51 seconds
Started Mar 05 12:38:08 PM PST 24
Finished Mar 05 12:38:12 PM PST 24
Peak memory 200576 kb
Host smart-74c066ac-6cc2-4be1-9dd0-f6266863ce69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062504462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2062504462
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2827015638
Short name T837
Test name
Test status
Simulation time 805661470 ps
CPU time 0.91 seconds
Started Mar 05 12:38:40 PM PST 24
Finished Mar 05 12:38:42 PM PST 24
Peak memory 200704 kb
Host smart-ffb748cc-92e6-4b09-80d1-c9b32fccaefa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827015638 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2827015638
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2401141287
Short name T97
Test name
Test status
Simulation time 568421358 ps
CPU time 1.12 seconds
Started Mar 05 12:38:12 PM PST 24
Finished Mar 05 12:38:14 PM PST 24
Peak memory 199680 kb
Host smart-6e0812fd-89af-4716-b8a0-d1a6af43b2c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401141287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2401141287
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1811795999
Short name T809
Test name
Test status
Simulation time 283014281 ps
CPU time 1.3 seconds
Started Mar 05 12:38:24 PM PST 24
Finished Mar 05 12:38:26 PM PST 24
Peak memory 200296 kb
Host smart-d70273aa-3505-4004-99c3-008b24a11106
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811795999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1811795999
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3907224282
Short name T859
Test name
Test status
Simulation time 2567821028 ps
CPU time 9.37 seconds
Started Mar 05 12:38:28 PM PST 24
Finished Mar 05 12:38:38 PM PST 24
Peak memory 200640 kb
Host smart-d09dfe3b-55dc-4c3e-96b8-b4221bb5ea44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907224282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3907224282
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2023108955
Short name T872
Test name
Test status
Simulation time 333206266 ps
CPU time 1.96 seconds
Started Mar 05 12:38:16 PM PST 24
Finished Mar 05 12:38:19 PM PST 24
Peak memory 200908 kb
Host smart-2a851a3a-728e-4a22-8d68-8a9dd88eda39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023108955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2023108955
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2311694812
Short name T914
Test name
Test status
Simulation time 8353404714 ps
CPU time 7.06 seconds
Started Mar 05 12:38:08 PM PST 24
Finished Mar 05 12:38:15 PM PST 24
Peak memory 200716 kb
Host smart-a76b907b-4e66-4958-92f8-41c4c20fd9e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311694812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2311694812
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.420161625
Short name T801
Test name
Test status
Simulation time 312324895 ps
CPU time 1.39 seconds
Started Mar 05 12:38:18 PM PST 24
Finished Mar 05 12:38:20 PM PST 24
Peak memory 200448 kb
Host smart-8a564494-6002-4468-acea-d8e74d050b47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420161625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.420161625
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.696350275
Short name T851
Test name
Test status
Simulation time 545125968 ps
CPU time 0.92 seconds
Started Mar 05 12:38:31 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200512 kb
Host smart-857052b5-2ba1-403f-853a-30f7f076f21f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696350275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.696350275
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.169691089
Short name T819
Test name
Test status
Simulation time 456156741 ps
CPU time 0.9 seconds
Started Mar 05 12:38:23 PM PST 24
Finished Mar 05 12:38:24 PM PST 24
Peak memory 200428 kb
Host smart-1d646119-3e75-48b2-b7d0-465543431940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169691089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.169691089
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3385001354
Short name T826
Test name
Test status
Simulation time 509399377 ps
CPU time 0.95 seconds
Started Mar 05 12:38:38 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 200496 kb
Host smart-3aeed96d-6c56-4755-8054-025f9f174876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385001354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3385001354
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.320989439
Short name T905
Test name
Test status
Simulation time 371424532 ps
CPU time 0.72 seconds
Started Mar 05 12:38:32 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200084 kb
Host smart-e11f09dc-f097-4ebd-9e3b-44b44f70b6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320989439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.320989439
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.412302651
Short name T795
Test name
Test status
Simulation time 293837553 ps
CPU time 1.01 seconds
Started Mar 05 12:38:34 PM PST 24
Finished Mar 05 12:38:35 PM PST 24
Peak memory 200724 kb
Host smart-6ffc546f-b096-4db4-991c-2c23e824cf65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412302651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.412302651
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3360516897
Short name T846
Test name
Test status
Simulation time 525406960 ps
CPU time 1.23 seconds
Started Mar 05 12:38:41 PM PST 24
Finished Mar 05 12:38:43 PM PST 24
Peak memory 200328 kb
Host smart-a9876568-ba39-43cf-8e8f-4a931325b07a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360516897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3360516897
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3018072126
Short name T896
Test name
Test status
Simulation time 344603753 ps
CPU time 1.38 seconds
Started Mar 05 12:38:28 PM PST 24
Finished Mar 05 12:38:30 PM PST 24
Peak memory 200508 kb
Host smart-99503a45-6d05-4e00-a9cb-68becb842578
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018072126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3018072126
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3329968856
Short name T854
Test name
Test status
Simulation time 515125804 ps
CPU time 0.7 seconds
Started Mar 05 12:38:47 PM PST 24
Finished Mar 05 12:38:48 PM PST 24
Peak memory 200592 kb
Host smart-fa6423e8-9573-407d-8140-f9df1c2c7f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329968856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3329968856
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3661720846
Short name T831
Test name
Test status
Simulation time 489848244 ps
CPU time 0.99 seconds
Started Mar 05 12:38:20 PM PST 24
Finished Mar 05 12:38:21 PM PST 24
Peak memory 200108 kb
Host smart-cc33c9b5-518f-4931-bb52-b99c3053cf74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661720846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3661720846
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3541928346
Short name T845
Test name
Test status
Simulation time 978190829 ps
CPU time 1.87 seconds
Started Mar 05 12:38:06 PM PST 24
Finished Mar 05 12:38:09 PM PST 24
Peak memory 200920 kb
Host smart-2fd9a2b3-36b9-4ee5-ac3a-0a44c26e4d56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541928346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3541928346
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2604083222
Short name T902
Test name
Test status
Simulation time 53122160517 ps
CPU time 160.41 seconds
Started Mar 05 12:39:06 PM PST 24
Finished Mar 05 12:41:47 PM PST 24
Peak memory 200024 kb
Host smart-c6c63cd0-b591-49a3-b242-aac4df0f8649
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604083222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2604083222
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3454763695
Short name T847
Test name
Test status
Simulation time 1113981755 ps
CPU time 1.38 seconds
Started Mar 05 12:38:11 PM PST 24
Finished Mar 05 12:38:13 PM PST 24
Peak memory 200580 kb
Host smart-6f040122-4f13-4b87-a6b4-c15befc14509
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454763695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3454763695
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1330896719
Short name T904
Test name
Test status
Simulation time 583550216 ps
CPU time 0.96 seconds
Started Mar 05 12:38:38 PM PST 24
Finished Mar 05 12:38:40 PM PST 24
Peak memory 200612 kb
Host smart-42dd0de7-8543-4b9f-9c1c-edbe1e63735f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330896719 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1330896719
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1429544785
Short name T891
Test name
Test status
Simulation time 460522320 ps
CPU time 1.28 seconds
Started Mar 05 12:38:08 PM PST 24
Finished Mar 05 12:38:10 PM PST 24
Peak memory 200508 kb
Host smart-b9110c21-6e32-45d3-83dc-60bc09f01555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429544785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1429544785
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.345569396
Short name T806
Test name
Test status
Simulation time 481814157 ps
CPU time 1.25 seconds
Started Mar 05 12:38:17 PM PST 24
Finished Mar 05 12:38:20 PM PST 24
Peak memory 200032 kb
Host smart-2a1ef72b-bca9-439d-97f9-2bfd4a7e53b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345569396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.345569396
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.1938547745
Short name T860
Test name
Test status
Simulation time 4492947572 ps
CPU time 16.83 seconds
Started Mar 05 12:38:16 PM PST 24
Finished Mar 05 12:38:35 PM PST 24
Peak memory 200000 kb
Host smart-0d9d72ad-5d73-4bc7-8630-6cf9cdec24ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938547745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.1938547745
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3396561195
Short name T105
Test name
Test status
Simulation time 383187039 ps
CPU time 2.56 seconds
Started Mar 05 12:38:08 PM PST 24
Finished Mar 05 12:38:11 PM PST 24
Peak memory 217116 kb
Host smart-a5c20fb8-e271-4645-8f0d-54a231dddbb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396561195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3396561195
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2514280393
Short name T858
Test name
Test status
Simulation time 4188940363 ps
CPU time 3.95 seconds
Started Mar 05 12:38:19 PM PST 24
Finished Mar 05 12:38:24 PM PST 24
Peak memory 200796 kb
Host smart-2b5a0d02-447e-46b6-a2aa-94e88074bbe6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514280393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2514280393
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1585646078
Short name T852
Test name
Test status
Simulation time 399509167 ps
CPU time 0.78 seconds
Started Mar 05 12:38:20 PM PST 24
Finished Mar 05 12:38:21 PM PST 24
Peak memory 200232 kb
Host smart-9b64882b-8666-456d-a456-9046d915e469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585646078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1585646078
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.4209909854
Short name T803
Test name
Test status
Simulation time 422916521 ps
CPU time 0.83 seconds
Started Mar 05 12:38:20 PM PST 24
Finished Mar 05 12:38:21 PM PST 24
Peak memory 200436 kb
Host smart-1064e95c-af3c-4b59-9e4d-8a628f6b5891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209909854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.4209909854
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2771331628
Short name T886
Test name
Test status
Simulation time 503009358 ps
CPU time 0.93 seconds
Started Mar 05 12:38:39 PM PST 24
Finished Mar 05 12:38:40 PM PST 24
Peak memory 200484 kb
Host smart-efd71498-bf6f-496f-8b17-306a43b5a2aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771331628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2771331628
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.425648418
Short name T822
Test name
Test status
Simulation time 366746122 ps
CPU time 0.85 seconds
Started Mar 05 12:38:24 PM PST 24
Finished Mar 05 12:38:25 PM PST 24
Peak memory 200284 kb
Host smart-f3150b2b-f297-4950-b477-3ae5718efcd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425648418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.425648418
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.158623861
Short name T839
Test name
Test status
Simulation time 374151943 ps
CPU time 1.49 seconds
Started Mar 05 12:38:55 PM PST 24
Finished Mar 05 12:38:56 PM PST 24
Peak memory 200496 kb
Host smart-c56e7e92-74e0-4e5d-9a7f-f7932d3d7644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158623861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.158623861
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.470405414
Short name T829
Test name
Test status
Simulation time 519994857 ps
CPU time 1.93 seconds
Started Mar 05 12:38:31 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200484 kb
Host smart-6a63e2f6-3f9f-44fd-8e8f-b5404d1b5a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470405414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.470405414
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3117115303
Short name T882
Test name
Test status
Simulation time 401034121 ps
CPU time 1 seconds
Started Mar 05 12:38:38 PM PST 24
Finished Mar 05 12:38:39 PM PST 24
Peak memory 200732 kb
Host smart-6b4fc668-5d15-49bf-9312-244a1ad86a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117115303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3117115303
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.89330838
Short name T881
Test name
Test status
Simulation time 393022274 ps
CPU time 1.54 seconds
Started Mar 05 12:38:33 PM PST 24
Finished Mar 05 12:38:35 PM PST 24
Peak memory 200328 kb
Host smart-277ecda4-b90a-44f7-9873-8578d8af7f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89330838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.89330838
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1892770428
Short name T855
Test name
Test status
Simulation time 390891113 ps
CPU time 0.84 seconds
Started Mar 05 12:38:20 PM PST 24
Finished Mar 05 12:38:21 PM PST 24
Peak memory 200416 kb
Host smart-a8fcffa8-3b92-4e29-a171-dfb56aa5b63b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892770428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1892770428
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1932304624
Short name T816
Test name
Test status
Simulation time 411470231 ps
CPU time 0.88 seconds
Started Mar 05 12:38:26 PM PST 24
Finished Mar 05 12:38:27 PM PST 24
Peak memory 200284 kb
Host smart-f7a35dec-f43a-43df-a4c0-e6832cb660f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932304624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1932304624
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1865640588
Short name T88
Test name
Test status
Simulation time 494147507 ps
CPU time 2.52 seconds
Started Mar 05 12:39:38 PM PST 24
Finished Mar 05 12:39:41 PM PST 24
Peak memory 200724 kb
Host smart-d685c80a-e5c5-48d6-9297-a4733bf4fd0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865640588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1865640588
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1401186228
Short name T86
Test name
Test status
Simulation time 50205885647 ps
CPU time 40.67 seconds
Started Mar 05 12:38:21 PM PST 24
Finished Mar 05 12:39:01 PM PST 24
Peak memory 200796 kb
Host smart-959ae1bc-d23c-47a8-b447-8d46faa26cfc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401186228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1401186228
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.4043007001
Short name T102
Test name
Test status
Simulation time 963096490 ps
CPU time 1.35 seconds
Started Mar 05 12:38:15 PM PST 24
Finished Mar 05 12:38:18 PM PST 24
Peak memory 200544 kb
Host smart-695e32c7-01b1-4782-863f-05fcfad162b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043007001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.4043007001
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3737482834
Short name T850
Test name
Test status
Simulation time 551708314 ps
CPU time 1.71 seconds
Started Mar 05 12:38:07 PM PST 24
Finished Mar 05 12:38:08 PM PST 24
Peak memory 200708 kb
Host smart-643712ed-8369-45fd-a5d3-b84ccec6ae8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737482834 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3737482834
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3592680309
Short name T92
Test name
Test status
Simulation time 529260496 ps
CPU time 1.03 seconds
Started Mar 05 12:38:20 PM PST 24
Finished Mar 05 12:38:21 PM PST 24
Peak memory 200488 kb
Host smart-d5f41af0-f1b2-4458-a535-80ec108aa222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592680309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3592680309
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.187864832
Short name T894
Test name
Test status
Simulation time 349887104 ps
CPU time 0.83 seconds
Started Mar 05 12:38:37 PM PST 24
Finished Mar 05 12:38:38 PM PST 24
Peak memory 200488 kb
Host smart-c8a54835-ff61-4eb3-a72b-0e1c6e9abb56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187864832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.187864832
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1505805053
Short name T830
Test name
Test status
Simulation time 3650669099 ps
CPU time 2.41 seconds
Started Mar 05 12:38:44 PM PST 24
Finished Mar 05 12:38:47 PM PST 24
Peak memory 200760 kb
Host smart-43fbe4e3-ed84-401e-9a52-7bf86aaf1cd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505805053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1505805053
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.1183518984
Short name T813
Test name
Test status
Simulation time 4138684577 ps
CPU time 11.29 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:47 PM PST 24
Peak memory 200760 kb
Host smart-37249d39-3f73-43ee-b522-1be2c3f3fbc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183518984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.1183518984
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3765141970
Short name T893
Test name
Test status
Simulation time 431223523 ps
CPU time 0.76 seconds
Started Mar 05 12:38:17 PM PST 24
Finished Mar 05 12:38:19 PM PST 24
Peak memory 199752 kb
Host smart-76974013-d3a1-4334-a39e-e47fd2e30e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765141970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3765141970
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1278400494
Short name T804
Test name
Test status
Simulation time 294817550 ps
CPU time 0.99 seconds
Started Mar 05 12:38:28 PM PST 24
Finished Mar 05 12:38:30 PM PST 24
Peak memory 200448 kb
Host smart-2206a3a7-542d-441f-93e7-c61dd069add5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278400494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1278400494
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.4072517109
Short name T840
Test name
Test status
Simulation time 325037688 ps
CPU time 0.75 seconds
Started Mar 05 12:39:05 PM PST 24
Finished Mar 05 12:39:07 PM PST 24
Peak memory 200360 kb
Host smart-7a4585a3-c501-46ba-9a47-35953bbe58fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072517109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.4072517109
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1347663432
Short name T865
Test name
Test status
Simulation time 374503873 ps
CPU time 0.88 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:37 PM PST 24
Peak memory 200580 kb
Host smart-88f66df4-7f30-498f-ab83-6eda02970686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347663432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1347663432
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.626104465
Short name T836
Test name
Test status
Simulation time 486581237 ps
CPU time 0.9 seconds
Started Mar 05 12:38:14 PM PST 24
Finished Mar 05 12:38:16 PM PST 24
Peak memory 200192 kb
Host smart-e0020ea8-d067-454f-83e5-7dd66b6b80ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626104465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.626104465
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2779324073
Short name T805
Test name
Test status
Simulation time 485351519 ps
CPU time 1.2 seconds
Started Mar 05 12:38:36 PM PST 24
Finished Mar 05 12:38:38 PM PST 24
Peak memory 200316 kb
Host smart-48a1c8e4-c071-4100-9a38-98172b1427e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779324073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2779324073
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3861412214
Short name T832
Test name
Test status
Simulation time 303160293 ps
CPU time 1.04 seconds
Started Mar 05 12:38:32 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200320 kb
Host smart-4041c1d2-badd-40b7-8667-cd093fb6913a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861412214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3861412214
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2188155227
Short name T817
Test name
Test status
Simulation time 383093936 ps
CPU time 1.59 seconds
Started Mar 05 12:38:20 PM PST 24
Finished Mar 05 12:38:22 PM PST 24
Peak memory 200252 kb
Host smart-6967cce3-de3c-4c50-9638-7f28fb353e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188155227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2188155227
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1356423404
Short name T800
Test name
Test status
Simulation time 351402073 ps
CPU time 0.81 seconds
Started Mar 05 12:38:39 PM PST 24
Finished Mar 05 12:38:41 PM PST 24
Peak memory 200344 kb
Host smart-5165435d-7c57-4e49-aa3b-1a12042e1b49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356423404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1356423404
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.4254357516
Short name T861
Test name
Test status
Simulation time 407648717 ps
CPU time 0.86 seconds
Started Mar 05 12:38:17 PM PST 24
Finished Mar 05 12:38:19 PM PST 24
Peak memory 200456 kb
Host smart-7bdbb35c-64ad-4ff0-918d-4e6f31776445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254357516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.4254357516
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2774402771
Short name T892
Test name
Test status
Simulation time 359768815 ps
CPU time 1 seconds
Started Mar 05 12:38:16 PM PST 24
Finished Mar 05 12:38:19 PM PST 24
Peak memory 200700 kb
Host smart-95c6010f-094e-4936-8e42-f95aa5f5c7e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774402771 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2774402771
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2367083615
Short name T898
Test name
Test status
Simulation time 388236012 ps
CPU time 1.17 seconds
Started Mar 05 12:38:08 PM PST 24
Finished Mar 05 12:38:09 PM PST 24
Peak memory 200512 kb
Host smart-19135600-b349-43f2-87d2-46ffe054d989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367083615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2367083615
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2882108853
Short name T802
Test name
Test status
Simulation time 506623852 ps
CPU time 1.77 seconds
Started Mar 05 12:38:19 PM PST 24
Finished Mar 05 12:38:22 PM PST 24
Peak memory 200348 kb
Host smart-6924fac9-ee29-4abe-bb20-a561eee7cae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882108853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2882108853
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1939086541
Short name T32
Test name
Test status
Simulation time 4345322494 ps
CPU time 7.12 seconds
Started Mar 05 12:38:12 PM PST 24
Finished Mar 05 12:38:19 PM PST 24
Peak memory 200932 kb
Host smart-00ccac59-1265-4afa-bf47-12523e8de245
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939086541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1939086541
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4187302089
Short name T869
Test name
Test status
Simulation time 446339833 ps
CPU time 1.41 seconds
Started Mar 05 12:38:03 PM PST 24
Finished Mar 05 12:38:05 PM PST 24
Peak memory 200768 kb
Host smart-d5bcdd16-244d-4287-ad82-20e901c8a012
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187302089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4187302089
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3256751869
Short name T330
Test name
Test status
Simulation time 7857891274 ps
CPU time 22.05 seconds
Started Mar 05 12:38:05 PM PST 24
Finished Mar 05 12:38:28 PM PST 24
Peak memory 200868 kb
Host smart-d5e89975-a612-40d3-963e-92673d2fd652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256751869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3256751869
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2768688266
Short name T909
Test name
Test status
Simulation time 368715770 ps
CPU time 1.84 seconds
Started Mar 05 12:38:35 PM PST 24
Finished Mar 05 12:38:37 PM PST 24
Peak memory 200708 kb
Host smart-50eabcd1-a421-44b3-bb97-12a8621e8caa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768688266 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2768688266
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1047567449
Short name T84
Test name
Test status
Simulation time 495699178 ps
CPU time 1.5 seconds
Started Mar 05 12:38:34 PM PST 24
Finished Mar 05 12:38:35 PM PST 24
Peak memory 200484 kb
Host smart-1565ea47-62d9-4ce6-8ece-8e1afe3c640e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047567449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1047567449
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.20347599
Short name T890
Test name
Test status
Simulation time 305383701 ps
CPU time 1.29 seconds
Started Mar 05 12:38:28 PM PST 24
Finished Mar 05 12:38:30 PM PST 24
Peak memory 200360 kb
Host smart-140e13a9-1ccd-4601-ad5d-56af50c8b452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20347599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.20347599
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2345731907
Short name T100
Test name
Test status
Simulation time 5838962015 ps
CPU time 9.23 seconds
Started Mar 05 12:38:16 PM PST 24
Finished Mar 05 12:38:27 PM PST 24
Peak memory 200824 kb
Host smart-66b02d45-26c3-4e1c-847a-eed07794d697
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345731907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2345731907
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.815648922
Short name T828
Test name
Test status
Simulation time 359234426 ps
CPU time 3.14 seconds
Started Mar 05 12:38:33 PM PST 24
Finished Mar 05 12:38:36 PM PST 24
Peak memory 200860 kb
Host smart-a1bfadad-aa94-4154-b39c-8bb2b5ace6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815648922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.815648922
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3805683449
Short name T104
Test name
Test status
Simulation time 9107381677 ps
CPU time 7.49 seconds
Started Mar 05 12:38:22 PM PST 24
Finished Mar 05 12:38:30 PM PST 24
Peak memory 200860 kb
Host smart-cfcd169b-2a35-45ba-8e8a-f80e535bbf5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805683449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3805683449
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1510956759
Short name T827
Test name
Test status
Simulation time 551945244 ps
CPU time 2.11 seconds
Started Mar 05 12:38:29 PM PST 24
Finished Mar 05 12:38:32 PM PST 24
Peak memory 200616 kb
Host smart-a2c770b6-11ea-4268-aa7e-cfcf74028984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510956759 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1510956759
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1627683284
Short name T83
Test name
Test status
Simulation time 467842942 ps
CPU time 1.43 seconds
Started Mar 05 12:38:22 PM PST 24
Finished Mar 05 12:38:24 PM PST 24
Peak memory 199176 kb
Host smart-861cf04e-5e59-4e78-ac9b-d28ba9282aa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627683284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1627683284
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.407835431
Short name T875
Test name
Test status
Simulation time 348979534 ps
CPU time 1.01 seconds
Started Mar 05 12:38:29 PM PST 24
Finished Mar 05 12:38:30 PM PST 24
Peak memory 200420 kb
Host smart-0260e8a8-1b85-4900-8d5c-d35a069c7b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407835431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.407835431
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2331680829
Short name T906
Test name
Test status
Simulation time 4136891503 ps
CPU time 4.08 seconds
Started Mar 05 12:38:17 PM PST 24
Finished Mar 05 12:38:22 PM PST 24
Peak memory 200240 kb
Host smart-cde8f050-9c7a-4ec4-8fff-c1176107db67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331680829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2331680829
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1692599730
Short name T864
Test name
Test status
Simulation time 463482627 ps
CPU time 3.11 seconds
Started Mar 05 12:38:06 PM PST 24
Finished Mar 05 12:38:09 PM PST 24
Peak memory 216668 kb
Host smart-f196338d-429f-4961-b48d-123b7563c1d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692599730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1692599730
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4071928942
Short name T110
Test name
Test status
Simulation time 8025726771 ps
CPU time 21.2 seconds
Started Mar 05 12:38:22 PM PST 24
Finished Mar 05 12:38:44 PM PST 24
Peak memory 199432 kb
Host smart-948a3356-5e8e-4cdc-80cd-0bc34f0498e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071928942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.4071928942
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1271806204
Short name T77
Test name
Test status
Simulation time 535863311 ps
CPU time 1.4 seconds
Started Mar 05 12:38:18 PM PST 24
Finished Mar 05 12:38:20 PM PST 24
Peak memory 200672 kb
Host smart-9c1c0fed-0541-46bb-8990-4033817bc4f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271806204 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1271806204
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3146352665
Short name T870
Test name
Test status
Simulation time 480557774 ps
CPU time 0.97 seconds
Started Mar 05 12:38:12 PM PST 24
Finished Mar 05 12:38:14 PM PST 24
Peak memory 200444 kb
Host smart-45a35bbd-cc3a-4f2d-8d7b-04e7556249a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146352665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3146352665
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1071174929
Short name T812
Test name
Test status
Simulation time 404685598 ps
CPU time 1.08 seconds
Started Mar 05 12:38:16 PM PST 24
Finished Mar 05 12:38:19 PM PST 24
Peak memory 200568 kb
Host smart-2ea162c6-aa6d-435c-a6c5-1032ea6e7092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071174929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1071174929
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.913280592
Short name T907
Test name
Test status
Simulation time 3746647613 ps
CPU time 2.85 seconds
Started Mar 05 12:38:22 PM PST 24
Finished Mar 05 12:38:25 PM PST 24
Peak memory 200788 kb
Host smart-6227490a-0e75-4d8f-99d0-58a738e8e784
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913280592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.913280592
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3999302416
Short name T63
Test name
Test status
Simulation time 478033732 ps
CPU time 2.05 seconds
Started Mar 05 12:39:31 PM PST 24
Finished Mar 05 12:39:34 PM PST 24
Peak memory 217148 kb
Host smart-979a559d-44a6-4981-8c2c-1d26d9735a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999302416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3999302416
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2687161093
Short name T879
Test name
Test status
Simulation time 8217290047 ps
CPU time 20.9 seconds
Started Mar 05 12:38:05 PM PST 24
Finished Mar 05 12:38:27 PM PST 24
Peak memory 200796 kb
Host smart-a2257628-3e3f-4837-ae46-77026072fd94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687161093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2687161093
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3995679176
Short name T888
Test name
Test status
Simulation time 622267638 ps
CPU time 1.65 seconds
Started Mar 05 12:38:31 PM PST 24
Finished Mar 05 12:38:33 PM PST 24
Peak memory 200636 kb
Host smart-3caac0e6-8bac-484b-affd-b47569522e12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995679176 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3995679176
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1114694283
Short name T99
Test name
Test status
Simulation time 516488351 ps
CPU time 1.91 seconds
Started Mar 05 12:38:32 PM PST 24
Finished Mar 05 12:38:34 PM PST 24
Peak memory 200448 kb
Host smart-5f5b9eb8-9815-4329-8585-4b18ccbbb9a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114694283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1114694283
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.966464302
Short name T807
Test name
Test status
Simulation time 320756454 ps
CPU time 1.03 seconds
Started Mar 05 12:38:06 PM PST 24
Finished Mar 05 12:38:07 PM PST 24
Peak memory 200296 kb
Host smart-e540dad0-1129-4c1c-9442-ede1ed9e4a57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966464302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.966464302
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3854160947
Short name T913
Test name
Test status
Simulation time 2265630084 ps
CPU time 2.22 seconds
Started Mar 05 12:38:34 PM PST 24
Finished Mar 05 12:38:36 PM PST 24
Peak memory 200616 kb
Host smart-0c9c97f0-a233-492e-a89a-bfa9803098e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854160947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3854160947
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2247799615
Short name T834
Test name
Test status
Simulation time 546407360 ps
CPU time 3.18 seconds
Started Mar 05 12:38:11 PM PST 24
Finished Mar 05 12:38:15 PM PST 24
Peak memory 200760 kb
Host smart-4bfab0ef-f11c-4bb5-a31c-2ae446686115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247799615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2247799615
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1423973099
Short name T883
Test name
Test status
Simulation time 8223743192 ps
CPU time 21.65 seconds
Started Mar 05 12:38:25 PM PST 24
Finished Mar 05 12:38:47 PM PST 24
Peak memory 200792 kb
Host smart-f2a8856a-eeb9-4f7d-8ee8-a5561725d508
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423973099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1423973099
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2052492260
Short name T780
Test name
Test status
Simulation time 403659554 ps
CPU time 0.98 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 12:45:07 PM PST 24
Peak memory 200872 kb
Host smart-724e27d0-725a-4008-a182-cb8bfbd3d9fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052492260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2052492260
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2581911769
Short name T240
Test name
Test status
Simulation time 483647884977 ps
CPU time 690.95 seconds
Started Mar 05 12:44:57 PM PST 24
Finished Mar 05 12:56:28 PM PST 24
Peak memory 201076 kb
Host smart-9fc76219-9813-4979-8f11-bfc2a68ea81c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581911769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2581911769
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3310839335
Short name T131
Test name
Test status
Simulation time 167826158026 ps
CPU time 384.56 seconds
Started Mar 05 12:44:49 PM PST 24
Finished Mar 05 12:51:13 PM PST 24
Peak memory 201136 kb
Host smart-969261e2-430f-4c60-bc6f-b78d1e4e1a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310839335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3310839335
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2761492314
Short name T758
Test name
Test status
Simulation time 163225554190 ps
CPU time 186.07 seconds
Started Mar 05 12:44:58 PM PST 24
Finished Mar 05 12:48:04 PM PST 24
Peak memory 201184 kb
Host smart-db0680a0-b897-4407-bc2e-180a60f3f8f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761492314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2761492314
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2083159586
Short name T270
Test name
Test status
Simulation time 166688918573 ps
CPU time 178.59 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:48:00 PM PST 24
Peak memory 201080 kb
Host smart-3fac4f83-dc8d-44b4-b252-7bf0e2df7559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083159586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2083159586
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3794901545
Short name T425
Test name
Test status
Simulation time 325231134988 ps
CPU time 194.73 seconds
Started Mar 05 12:45:02 PM PST 24
Finished Mar 05 12:48:17 PM PST 24
Peak memory 201180 kb
Host smart-f99c87c5-6d73-46c0-b0fb-3b51a44ce375
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794901545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3794901545
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2323613614
Short name T268
Test name
Test status
Simulation time 169419347182 ps
CPU time 75.1 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:46:21 PM PST 24
Peak memory 201120 kb
Host smart-1f2b31cd-d80f-4b8e-b279-e997527656c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323613614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2323613614
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.1469859092
Short name T476
Test name
Test status
Simulation time 492572290008 ps
CPU time 568.62 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 12:54:34 PM PST 24
Peak memory 201128 kb
Host smart-42571221-4797-4293-9f4f-2b59687a808b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469859092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.1469859092
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.34493500
Short name T465
Test name
Test status
Simulation time 107465297895 ps
CPU time 563.48 seconds
Started Mar 05 12:45:04 PM PST 24
Finished Mar 05 12:54:28 PM PST 24
Peak memory 201512 kb
Host smart-5bf36903-144a-4565-8133-eb067bc5be6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34493500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.34493500
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1784555667
Short name T348
Test name
Test status
Simulation time 44659739659 ps
CPU time 52.06 seconds
Started Mar 05 12:45:07 PM PST 24
Finished Mar 05 12:45:59 PM PST 24
Peak memory 200992 kb
Host smart-14d3cbdc-b31e-46c5-87ba-087a3fe68c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784555667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1784555667
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1387595308
Short name T645
Test name
Test status
Simulation time 4497774612 ps
CPU time 3.27 seconds
Started Mar 05 12:44:52 PM PST 24
Finished Mar 05 12:44:55 PM PST 24
Peak memory 200960 kb
Host smart-78ebea7e-5783-4665-a50d-c80c5b50ae94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387595308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1387595308
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2940598247
Short name T408
Test name
Test status
Simulation time 5852401204 ps
CPU time 4.03 seconds
Started Mar 05 12:44:35 PM PST 24
Finished Mar 05 12:44:39 PM PST 24
Peak memory 201004 kb
Host smart-14ff30a3-34c5-4ff4-a2ce-2422c9de2899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940598247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2940598247
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.937976675
Short name T40
Test name
Test status
Simulation time 172860550621 ps
CPU time 51.85 seconds
Started Mar 05 12:44:49 PM PST 24
Finished Mar 05 12:45:41 PM PST 24
Peak memory 209532 kb
Host smart-f0d7eb73-8680-4304-861e-32b7a461b5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937976675 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.937976675
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.1161400565
Short name T779
Test name
Test status
Simulation time 473442287 ps
CPU time 1.14 seconds
Started Mar 05 12:44:49 PM PST 24
Finished Mar 05 12:44:51 PM PST 24
Peak memory 200916 kb
Host smart-0220f0cf-e2ca-478f-841c-e167df695631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161400565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.1161400565
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.1654062659
Short name T586
Test name
Test status
Simulation time 164784421093 ps
CPU time 53.42 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 12:45:49 PM PST 24
Peak memory 201180 kb
Host smart-8cd38b69-48e2-4276-8d6d-a4a308ebb572
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654062659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.1654062659
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3187849826
Short name T213
Test name
Test status
Simulation time 327116578374 ps
CPU time 99.61 seconds
Started Mar 05 12:44:52 PM PST 24
Finished Mar 05 12:46:32 PM PST 24
Peak memory 201196 kb
Host smart-b388052f-73c9-4ad8-8e6a-e652a00721f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187849826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3187849826
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1672420730
Short name T565
Test name
Test status
Simulation time 490587433268 ps
CPU time 1153.18 seconds
Started Mar 05 12:45:00 PM PST 24
Finished Mar 05 01:04:13 PM PST 24
Peak memory 201120 kb
Host smart-0cf447bc-3e36-4da9-a590-378264aa1eb2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672420730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1672420730
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.525241573
Short name T757
Test name
Test status
Simulation time 162507073105 ps
CPU time 193.24 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 12:48:18 PM PST 24
Peak memory 201132 kb
Host smart-99de945b-7523-4047-b2cd-a2244f20a6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525241573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.525241573
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1091255524
Short name T656
Test name
Test status
Simulation time 330604953532 ps
CPU time 749.96 seconds
Started Mar 05 12:44:46 PM PST 24
Finished Mar 05 12:57:17 PM PST 24
Peak memory 201064 kb
Host smart-056ac075-07e9-43b5-bb08-486054cd8065
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091255524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1091255524
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.781721481
Short name T639
Test name
Test status
Simulation time 328337784625 ps
CPU time 370.75 seconds
Started Mar 05 12:44:51 PM PST 24
Finished Mar 05 12:51:02 PM PST 24
Peak memory 201184 kb
Host smart-4eff4eba-627f-48ca-848c-fd268cb062d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781721481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.781721481
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.213392234
Short name T596
Test name
Test status
Simulation time 36144996636 ps
CPU time 21.65 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:45:23 PM PST 24
Peak memory 200920 kb
Host smart-4e295514-8400-42dd-afb1-a1d6a9ef3e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213392234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.213392234
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1597567017
Short name T178
Test name
Test status
Simulation time 5435589615 ps
CPU time 4.02 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 12:45:04 PM PST 24
Peak memory 201060 kb
Host smart-bd2a0c6b-7765-4341-9fbf-80c880a624c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597567017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1597567017
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2975517598
Short name T48
Test name
Test status
Simulation time 8467830559 ps
CPU time 2.16 seconds
Started Mar 05 12:44:52 PM PST 24
Finished Mar 05 12:44:55 PM PST 24
Peak memory 217588 kb
Host smart-fe8e5aea-0b1a-4fb1-b7bc-1aaa0dfcdd97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975517598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2975517598
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1733941851
Short name T390
Test name
Test status
Simulation time 5960545242 ps
CPU time 7.26 seconds
Started Mar 05 12:44:56 PM PST 24
Finished Mar 05 12:45:03 PM PST 24
Peak memory 201000 kb
Host smart-49586d99-2167-4e1b-a2d4-8771b1410017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733941851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1733941851
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.3884340639
Short name T277
Test name
Test status
Simulation time 532889778407 ps
CPU time 959.54 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 01:00:55 PM PST 24
Peak memory 201168 kb
Host smart-bdfb4d3a-97a8-48c0-9e49-fc8c0ae9bd49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884340639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
3884340639
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.165254913
Short name T202
Test name
Test status
Simulation time 48963796485 ps
CPU time 114.43 seconds
Started Mar 05 12:44:50 PM PST 24
Finished Mar 05 12:46:44 PM PST 24
Peak memory 201208 kb
Host smart-a13f0fb5-920d-4006-810e-4807e87ce1aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165254913 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.165254913
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.4207680984
Short name T591
Test name
Test status
Simulation time 384888571 ps
CPU time 1.05 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:45:14 PM PST 24
Peak memory 200924 kb
Host smart-8fa1d278-0343-4cdf-8f13-39c7d8c5291c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207680984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.4207680984
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1633584123
Short name T766
Test name
Test status
Simulation time 493248389574 ps
CPU time 1212.27 seconds
Started Mar 05 12:45:08 PM PST 24
Finished Mar 05 01:05:20 PM PST 24
Peak memory 201120 kb
Host smart-071fdc43-021c-4fca-b7ba-6b006ae11e40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633584123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1633584123
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.36241034
Short name T144
Test name
Test status
Simulation time 162308597398 ps
CPU time 99.22 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:46:41 PM PST 24
Peak memory 201116 kb
Host smart-18579b6c-2333-489a-aa26-df1c897f6969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36241034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.36241034
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.247372896
Short name T402
Test name
Test status
Simulation time 329347837719 ps
CPU time 194.71 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 12:48:14 PM PST 24
Peak memory 201024 kb
Host smart-035edbe6-f4fc-4d5e-8fef-5aece4243de7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=247372896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.247372896
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3277193961
Short name T519
Test name
Test status
Simulation time 337020715771 ps
CPU time 355.12 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 12:51:01 PM PST 24
Peak memory 201144 kb
Host smart-2307e9c0-ffe2-4e62-86cb-db34d27d3b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277193961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3277193961
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3508943047
Short name T446
Test name
Test status
Simulation time 325247042674 ps
CPU time 749.64 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:57:40 PM PST 24
Peak memory 201124 kb
Host smart-5b481c3e-47b3-4c18-abc5-a31545b02236
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508943047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3508943047
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1999266060
Short name T675
Test name
Test status
Simulation time 157805366952 ps
CPU time 387.33 seconds
Started Mar 05 12:45:13 PM PST 24
Finished Mar 05 12:51:40 PM PST 24
Peak memory 201128 kb
Host smart-40963634-3529-48c9-b6fc-616b1e8bf499
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999266060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1999266060
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.2802310663
Short name T451
Test name
Test status
Simulation time 129333544884 ps
CPU time 441.57 seconds
Started Mar 05 12:44:53 PM PST 24
Finished Mar 05 12:52:15 PM PST 24
Peak memory 201392 kb
Host smart-1f668e0c-20d0-4041-93b2-1f12392a45f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802310663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.2802310663
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1274517641
Short name T533
Test name
Test status
Simulation time 41058221889 ps
CPU time 93.18 seconds
Started Mar 05 12:44:54 PM PST 24
Finished Mar 05 12:46:27 PM PST 24
Peak memory 200992 kb
Host smart-ed6d40dc-2af1-4f00-9c26-f82ea1eb8d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274517641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1274517641
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2420366051
Short name T561
Test name
Test status
Simulation time 3480097422 ps
CPU time 3.62 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:45:23 PM PST 24
Peak memory 201064 kb
Host smart-512523e0-bc0c-46cb-ac9d-22a8d81a4a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420366051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2420366051
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2632863644
Short name T786
Test name
Test status
Simulation time 5768079338 ps
CPU time 16.05 seconds
Started Mar 05 12:45:15 PM PST 24
Finished Mar 05 12:45:35 PM PST 24
Peak memory 200916 kb
Host smart-f6573c7d-bdfa-4d16-9ace-ad7a1f598ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632863644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2632863644
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3857218243
Short name T431
Test name
Test status
Simulation time 206661682906 ps
CPU time 122.8 seconds
Started Mar 05 12:45:15 PM PST 24
Finished Mar 05 12:47:18 PM PST 24
Peak memory 201116 kb
Host smart-44f74419-5daa-43bb-ae69-6de4ebfb109a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857218243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3857218243
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1018027671
Short name T41
Test name
Test status
Simulation time 203946640454 ps
CPU time 178.59 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 12:47:54 PM PST 24
Peak memory 209832 kb
Host smart-b1674b2d-b183-4830-b7fb-f4f351359721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018027671 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1018027671
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.701753534
Short name T428
Test name
Test status
Simulation time 420678630 ps
CPU time 1.18 seconds
Started Mar 05 12:45:24 PM PST 24
Finished Mar 05 12:45:26 PM PST 24
Peak memory 200932 kb
Host smart-ecea8bc3-fa91-4547-99cf-860996a67e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701753534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.701753534
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3036482481
Short name T599
Test name
Test status
Simulation time 485471086003 ps
CPU time 79.1 seconds
Started Mar 05 12:45:16 PM PST 24
Finished Mar 05 12:46:35 PM PST 24
Peak memory 201124 kb
Host smart-75a51183-4c76-4e28-9ec5-0cef8aeff635
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036482481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3036482481
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3540803435
Short name T134
Test name
Test status
Simulation time 327933983720 ps
CPU time 205.75 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:48:36 PM PST 24
Peak memory 201172 kb
Host smart-821ae60b-9178-406e-8c66-df323018b445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540803435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3540803435
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1507038216
Short name T710
Test name
Test status
Simulation time 492788392656 ps
CPU time 211.71 seconds
Started Mar 05 12:45:08 PM PST 24
Finished Mar 05 12:48:40 PM PST 24
Peak memory 201140 kb
Host smart-e53da494-6324-4e65-bbb9-cfc7e221b40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507038216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1507038216
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.4193232779
Short name T663
Test name
Test status
Simulation time 325903895955 ps
CPU time 812.51 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:58:43 PM PST 24
Peak memory 201076 kb
Host smart-25d4a6b6-a6ac-4ad1-bf23-384ac290437f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193232779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.4193232779
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.4082413798
Short name T56
Test name
Test status
Simulation time 322516923569 ps
CPU time 205 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:48:34 PM PST 24
Peak memory 201116 kb
Host smart-a9d610c3-db3d-4211-bb2f-d09119b81f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082413798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.4082413798
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.4240704490
Short name T615
Test name
Test status
Simulation time 166407610726 ps
CPU time 204.65 seconds
Started Mar 05 12:45:13 PM PST 24
Finished Mar 05 12:48:37 PM PST 24
Peak memory 201160 kb
Host smart-004eb828-2f2f-4720-92b8-a4c8ae26786e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240704490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.4240704490
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2889291253
Short name T690
Test name
Test status
Simulation time 334605505934 ps
CPU time 765.5 seconds
Started Mar 05 12:45:22 PM PST 24
Finished Mar 05 12:58:07 PM PST 24
Peak memory 201084 kb
Host smart-9b084af6-02d1-4a6d-9ca0-413e36d47a3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889291253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2889291253
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2887404538
Short name T704
Test name
Test status
Simulation time 168126536634 ps
CPU time 91.99 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:46:46 PM PST 24
Peak memory 201184 kb
Host smart-980ed2ed-c5fb-4f4a-a847-c56fd927e201
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887404538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2887404538
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3007090875
Short name T511
Test name
Test status
Simulation time 41998750260 ps
CPU time 90.09 seconds
Started Mar 05 12:45:19 PM PST 24
Finished Mar 05 12:46:49 PM PST 24
Peak memory 201148 kb
Host smart-6669257c-0810-4883-a69b-504ba3bfffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007090875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3007090875
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2457993258
Short name T752
Test name
Test status
Simulation time 4434028104 ps
CPU time 7.11 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 12:45:17 PM PST 24
Peak memory 201060 kb
Host smart-42088f50-f045-41e6-8f0c-53c7610ef515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457993258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2457993258
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.576150290
Short name T393
Test name
Test status
Simulation time 5581822586 ps
CPU time 14.02 seconds
Started Mar 05 12:45:30 PM PST 24
Finished Mar 05 12:45:47 PM PST 24
Peak memory 201056 kb
Host smart-8e4ca8ed-216a-4fed-9303-0814ac086724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576150290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.576150290
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2117531467
Short name T667
Test name
Test status
Simulation time 345950115016 ps
CPU time 180.28 seconds
Started Mar 05 12:45:29 PM PST 24
Finished Mar 05 12:48:30 PM PST 24
Peak memory 209464 kb
Host smart-f05a38f8-8871-4ccf-88c9-48844e107184
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117531467 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2117531467
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.4039594924
Short name T693
Test name
Test status
Simulation time 302819444 ps
CPU time 0.97 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:45:13 PM PST 24
Peak memory 200864 kb
Host smart-19cb5230-d329-4411-820a-bacf56d6d7ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039594924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.4039594924
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1033288150
Short name T743
Test name
Test status
Simulation time 496758744818 ps
CPU time 1168.93 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 01:04:34 PM PST 24
Peak memory 201200 kb
Host smart-7b1a329a-cca5-4230-aa01-05a15251d7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033288150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1033288150
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2218798368
Short name T289
Test name
Test status
Simulation time 161573618226 ps
CPU time 89.14 seconds
Started Mar 05 12:45:22 PM PST 24
Finished Mar 05 12:46:51 PM PST 24
Peak memory 201080 kb
Host smart-d9601433-7e74-49ee-a961-542aeb3edab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218798368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2218798368
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3125650869
Short name T406
Test name
Test status
Simulation time 325256211555 ps
CPU time 309.87 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 12:50:05 PM PST 24
Peak memory 201020 kb
Host smart-51116684-0d94-416d-8508-b4f191e25a75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125650869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3125650869
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.440712362
Short name T504
Test name
Test status
Simulation time 323773426569 ps
CPU time 189.88 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:48:20 PM PST 24
Peak memory 201216 kb
Host smart-0dbb59bb-77e9-4674-b8b2-e291a446b25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440712362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.440712362
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1680527363
Short name T482
Test name
Test status
Simulation time 494227360405 ps
CPU time 564.67 seconds
Started Mar 05 12:45:17 PM PST 24
Finished Mar 05 12:54:42 PM PST 24
Peak memory 201120 kb
Host smart-7ab94c28-255e-4bf8-8077-90d54a92a494
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680527363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1680527363
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2119758061
Short name T230
Test name
Test status
Simulation time 500060810251 ps
CPU time 309.26 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:50:18 PM PST 24
Peak memory 201136 kb
Host smart-ae7d9e5c-748d-46eb-8c5e-4ae6a721ad75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119758061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2119758061
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1616292309
Short name T414
Test name
Test status
Simulation time 503582402099 ps
CPU time 343.83 seconds
Started Mar 05 12:45:27 PM PST 24
Finished Mar 05 12:51:11 PM PST 24
Peak memory 201124 kb
Host smart-2c5c74b3-8694-4173-b570-58b701da7060
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616292309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1616292309
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3941002042
Short name T556
Test name
Test status
Simulation time 87637557879 ps
CPU time 470.22 seconds
Started Mar 05 12:45:25 PM PST 24
Finished Mar 05 12:53:15 PM PST 24
Peak memory 201572 kb
Host smart-a769a92f-1e11-4cee-8d13-050e7167f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941002042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3941002042
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2191279967
Short name T409
Test name
Test status
Simulation time 45499295945 ps
CPU time 28.21 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 12:45:34 PM PST 24
Peak memory 201044 kb
Host smart-5f2d0fb5-4bc6-42aa-98ad-8b55273b241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191279967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2191279967
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3618555080
Short name T143
Test name
Test status
Simulation time 3627318565 ps
CPU time 4.95 seconds
Started Mar 05 12:45:07 PM PST 24
Finished Mar 05 12:45:12 PM PST 24
Peak memory 201060 kb
Host smart-a3cddcc7-a48b-4e38-bec2-813f776294da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618555080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3618555080
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3733131148
Short name T114
Test name
Test status
Simulation time 6049243269 ps
CPU time 4.34 seconds
Started Mar 05 12:45:19 PM PST 24
Finished Mar 05 12:45:23 PM PST 24
Peak memory 201052 kb
Host smart-aa43076b-097c-41ae-a150-e5c9da153c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733131148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3733131148
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2084617104
Short name T197
Test name
Test status
Simulation time 417914088943 ps
CPU time 1084.99 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 01:03:17 PM PST 24
Peak memory 211812 kb
Host smart-e493fea1-4856-4520-a065-d07ce8d1d57d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084617104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2084617104
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.406298103
Short name T725
Test name
Test status
Simulation time 326938163610 ps
CPU time 193.6 seconds
Started Mar 05 12:44:58 PM PST 24
Finished Mar 05 12:48:12 PM PST 24
Peak memory 201012 kb
Host smart-b0521d8f-2250-483b-a2f6-5951328506b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406298103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.406298103
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.1844505299
Short name T514
Test name
Test status
Simulation time 320386270221 ps
CPU time 737.93 seconds
Started Mar 05 12:45:04 PM PST 24
Finished Mar 05 12:57:22 PM PST 24
Peak memory 201092 kb
Host smart-63f78ce0-bfb4-4842-953d-6dfec2593f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844505299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.1844505299
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.2203639045
Short name T314
Test name
Test status
Simulation time 332980647565 ps
CPU time 143.95 seconds
Started Mar 05 12:45:17 PM PST 24
Finished Mar 05 12:47:41 PM PST 24
Peak memory 201136 kb
Host smart-f4596fb9-bd0a-4d47-8ae9-e9f6c3d6595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203639045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.2203639045
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1574596996
Short name T542
Test name
Test status
Simulation time 161797226731 ps
CPU time 341.16 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:51:03 PM PST 24
Peak memory 201124 kb
Host smart-d2b60e34-1e18-436b-98b2-0010c429c359
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574596996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1574596996
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3013671352
Short name T442
Test name
Test status
Simulation time 321048594425 ps
CPU time 346.63 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:50:57 PM PST 24
Peak memory 201176 kb
Host smart-14716864-e44c-4b60-a33d-2baf696eb507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013671352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3013671352
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1993475218
Short name T728
Test name
Test status
Simulation time 323399903242 ps
CPU time 202.87 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:48:33 PM PST 24
Peak memory 201120 kb
Host smart-aa72917c-5aed-4a56-84da-2f2a2aca7e21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993475218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1993475218
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3067020277
Short name T641
Test name
Test status
Simulation time 332420923473 ps
CPU time 324.02 seconds
Started Mar 05 12:45:25 PM PST 24
Finished Mar 05 12:50:49 PM PST 24
Peak memory 201180 kb
Host smart-a094f9ab-460a-4c64-af90-360bda41f3a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067020277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3067020277
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3214146029
Short name T793
Test name
Test status
Simulation time 94526277844 ps
CPU time 333.88 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:50:54 PM PST 24
Peak memory 201456 kb
Host smart-7b574694-f0f7-4c5b-852e-4d567303b49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214146029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3214146029
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3538542248
Short name T688
Test name
Test status
Simulation time 27416047039 ps
CPU time 16.79 seconds
Started Mar 05 12:45:15 PM PST 24
Finished Mar 05 12:45:32 PM PST 24
Peak memory 201044 kb
Host smart-e9da2358-22f0-4a51-a454-276407707a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538542248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3538542248
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1517281936
Short name T563
Test name
Test status
Simulation time 5153833583 ps
CPU time 12.19 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:45:22 PM PST 24
Peak memory 201064 kb
Host smart-a702db98-a9c9-4a54-bd26-6777c925f1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517281936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1517281936
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.511503909
Short name T775
Test name
Test status
Simulation time 6148466585 ps
CPU time 8.31 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:45:19 PM PST 24
Peak memory 201008 kb
Host smart-1c4b89d5-79f1-452e-bac0-7a4426733148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511503909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.511503909
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2959704719
Short name T17
Test name
Test status
Simulation time 55662171161 ps
CPU time 12.44 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:45:25 PM PST 24
Peak memory 209588 kb
Host smart-784572a1-fdc1-4739-8226-b0684fd03ac2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959704719 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2959704719
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2341983389
Short name T145
Test name
Test status
Simulation time 354593904 ps
CPU time 0.81 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:45:13 PM PST 24
Peak memory 200920 kb
Host smart-d7cc9e31-83e9-43f8-8fa6-8d503a05115a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341983389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2341983389
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1347602248
Short name T564
Test name
Test status
Simulation time 490133724627 ps
CPU time 600.37 seconds
Started Mar 05 12:45:15 PM PST 24
Finished Mar 05 12:55:16 PM PST 24
Peak memory 201176 kb
Host smart-2025a6a3-53b2-4af4-bcc1-d8320de68831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347602248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1347602248
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3951980491
Short name T122
Test name
Test status
Simulation time 325255396735 ps
CPU time 91.36 seconds
Started Mar 05 12:45:07 PM PST 24
Finished Mar 05 12:46:38 PM PST 24
Peak memory 201092 kb
Host smart-f6e39161-0f15-4bca-9ec8-56bdb40591e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951980491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3951980491
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1055734599
Short name T505
Test name
Test status
Simulation time 324560508042 ps
CPU time 782.48 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:58:12 PM PST 24
Peak memory 201064 kb
Host smart-d11b98a0-6e42-4fea-8d31-4b19f63d478c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055734599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1055734599
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.606625317
Short name T522
Test name
Test status
Simulation time 160442123615 ps
CPU time 174.52 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 12:48:00 PM PST 24
Peak memory 201120 kb
Host smart-b283d8c8-47dd-4a4d-adbe-e954a0491e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606625317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.606625317
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2891225787
Short name T715
Test name
Test status
Simulation time 160230939320 ps
CPU time 397.01 seconds
Started Mar 05 12:45:17 PM PST 24
Finished Mar 05 12:51:54 PM PST 24
Peak memory 201096 kb
Host smart-6c22dd0c-f9e4-4056-8c0c-09978afc8a03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891225787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2891225787
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3405674040
Short name T638
Test name
Test status
Simulation time 164141835103 ps
CPU time 400 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:52:01 PM PST 24
Peak memory 201164 kb
Host smart-45ecaaca-1d84-460a-8154-9c44da43813a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405674040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3405674040
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2658423370
Short name T454
Test name
Test status
Simulation time 164748895870 ps
CPU time 360.62 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:51:12 PM PST 24
Peak memory 201072 kb
Host smart-b8df09f5-e908-4b27-ba71-fcc5677fe6c4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658423370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2658423370
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.772715860
Short name T470
Test name
Test status
Simulation time 67832637929 ps
CPU time 223.71 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:49:05 PM PST 24
Peak memory 201504 kb
Host smart-b33f2f88-1d3d-4c8c-af96-1a2e94baab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772715860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.772715860
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.1047308478
Short name T164
Test name
Test status
Simulation time 33094126259 ps
CPU time 75.72 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:46:30 PM PST 24
Peak memory 201044 kb
Host smart-8b82d68c-3ac2-4534-8515-524e725d822a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047308478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.1047308478
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1906176983
Short name T50
Test name
Test status
Simulation time 2982338106 ps
CPU time 4.26 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:45:14 PM PST 24
Peak memory 201032 kb
Host smart-e8dc1962-e1c8-4ffb-b80f-791bd290149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906176983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1906176983
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1825959010
Short name T660
Test name
Test status
Simulation time 5908415779 ps
CPU time 7.92 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 12:45:14 PM PST 24
Peak memory 201052 kb
Host smart-33fb0ce4-f168-4e1b-a0a4-8aa892471d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825959010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1825959010
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2201424798
Short name T668
Test name
Test status
Simulation time 4362175958 ps
CPU time 5.94 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 12:45:12 PM PST 24
Peak memory 200988 kb
Host smart-5d7efbdf-f5f3-40da-8091-b1786463d643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201424798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2201424798
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3246785719
Short name T587
Test name
Test status
Simulation time 594827181 ps
CPU time 0.77 seconds
Started Mar 05 12:45:15 PM PST 24
Finished Mar 05 12:45:16 PM PST 24
Peak memory 200932 kb
Host smart-359d033b-9090-47a6-8682-2f83743af2b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246785719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3246785719
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2227119027
Short name T630
Test name
Test status
Simulation time 497289583347 ps
CPU time 289.67 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:50:10 PM PST 24
Peak memory 201184 kb
Host smart-14f582a2-58a2-49b8-8607-c67d6030124c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227119027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2227119027
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.4252903556
Short name T588
Test name
Test status
Simulation time 158250993292 ps
CPU time 97.07 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:46:51 PM PST 24
Peak memory 201144 kb
Host smart-e7cc19e0-6855-4ea4-8282-e24f00c51964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252903556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.4252903556
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.41629192
Short name T477
Test name
Test status
Simulation time 329855592367 ps
CPU time 395.31 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:51:44 PM PST 24
Peak memory 201108 kb
Host smart-0ae5d209-08e8-4718-869a-9ae94329a0f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=41629192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed
.41629192
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3402375999
Short name T669
Test name
Test status
Simulation time 162033126345 ps
CPU time 323.44 seconds
Started Mar 05 12:45:16 PM PST 24
Finished Mar 05 12:50:40 PM PST 24
Peak memory 201112 kb
Host smart-40fe11ad-ecad-4324-8e43-ada9ec52c184
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402375999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3402375999
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.1516542003
Short name T432
Test name
Test status
Simulation time 492425264259 ps
CPU time 207.92 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:48:40 PM PST 24
Peak memory 201128 kb
Host smart-5746cc7f-d5a0-4d67-a14f-9e32d5dda026
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516542003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.1516542003
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.347987585
Short name T457
Test name
Test status
Simulation time 33272842319 ps
CPU time 43.39 seconds
Started Mar 05 12:45:08 PM PST 24
Finished Mar 05 12:45:51 PM PST 24
Peak memory 200956 kb
Host smart-0338f8f4-7fe7-459f-939f-0d88f7caca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347987585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.347987585
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.596626166
Short name T570
Test name
Test status
Simulation time 4938464458 ps
CPU time 12.62 seconds
Started Mar 05 12:44:58 PM PST 24
Finished Mar 05 12:45:11 PM PST 24
Peak memory 201064 kb
Host smart-1ee411c1-515d-41d2-a92d-666695023bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596626166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.596626166
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2517650596
Short name T583
Test name
Test status
Simulation time 5928870256 ps
CPU time 8.15 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:45:22 PM PST 24
Peak memory 201056 kb
Host smart-4b43852d-de21-44f2-abe2-a58190ffa94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517650596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2517650596
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2282843889
Short name T708
Test name
Test status
Simulation time 164537754310 ps
CPU time 105.55 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:47:06 PM PST 24
Peak memory 201128 kb
Host smart-632582dd-6243-4bcb-868b-4803b7dda96a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282843889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2282843889
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.750041664
Short name T649
Test name
Test status
Simulation time 476388332 ps
CPU time 0.92 seconds
Started Mar 05 12:45:13 PM PST 24
Finished Mar 05 12:45:14 PM PST 24
Peak memory 200932 kb
Host smart-058a42f0-a580-4e7a-8056-7352d4f75229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750041664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.750041664
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3228838632
Short name T204
Test name
Test status
Simulation time 503773736864 ps
CPU time 109.31 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:47:10 PM PST 24
Peak memory 201044 kb
Host smart-68c4c8f4-221d-45cb-ae06-c917d130a0de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228838632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3228838632
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3708914297
Short name T691
Test name
Test status
Simulation time 167911984496 ps
CPU time 422.97 seconds
Started Mar 05 12:45:16 PM PST 24
Finished Mar 05 12:52:20 PM PST 24
Peak memory 201144 kb
Host smart-9d8fc327-330a-49a9-99ca-8cf3854aaada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708914297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3708914297
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3199645056
Short name T296
Test name
Test status
Simulation time 161974048594 ps
CPU time 388.1 seconds
Started Mar 05 12:45:15 PM PST 24
Finished Mar 05 12:51:43 PM PST 24
Peak memory 201168 kb
Host smart-d7157063-1c26-4b1c-bb04-437b4df98486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199645056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3199645056
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.392352057
Short name T623
Test name
Test status
Simulation time 162570376544 ps
CPU time 369.48 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:51:30 PM PST 24
Peak memory 201224 kb
Host smart-538c9255-cf03-4fb9-b0ff-b9fbf254063f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=392352057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrup
t_fixed.392352057
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2506530484
Short name T135
Test name
Test status
Simulation time 327825500361 ps
CPU time 390.83 seconds
Started Mar 05 12:45:15 PM PST 24
Finished Mar 05 12:51:46 PM PST 24
Peak memory 201140 kb
Host smart-41de6953-30aa-4a11-92c8-4778ac4ddc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506530484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2506530484
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.4183698656
Short name T754
Test name
Test status
Simulation time 485436359345 ps
CPU time 572.7 seconds
Started Mar 05 12:45:23 PM PST 24
Finished Mar 05 12:54:56 PM PST 24
Peak memory 201124 kb
Host smart-86a94cdf-e0f8-4ed6-b5c2-55f73f7bc124
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183698656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.4183698656
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1678563195
Short name T527
Test name
Test status
Simulation time 498189749683 ps
CPU time 1030.44 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 01:02:31 PM PST 24
Peak memory 201052 kb
Host smart-c1999ac6-16a9-40bf-a13a-b82d416cb42f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678563195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1678563195
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.162661397
Short name T336
Test name
Test status
Simulation time 59025022868 ps
CPU time 244.74 seconds
Started Mar 05 12:45:31 PM PST 24
Finished Mar 05 12:49:36 PM PST 24
Peak memory 201508 kb
Host smart-5bf58463-50aa-4d1a-baa8-9b8f630bb97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162661397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.162661397
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1809917220
Short name T447
Test name
Test status
Simulation time 45804513015 ps
CPU time 110.29 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:47:12 PM PST 24
Peak memory 200952 kb
Host smart-e1275b15-d9a4-41cb-b31f-eaa685ae8726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809917220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1809917220
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3850776179
Short name T611
Test name
Test status
Simulation time 3494915093 ps
CPU time 2.95 seconds
Started Mar 05 12:45:25 PM PST 24
Finished Mar 05 12:45:28 PM PST 24
Peak memory 201060 kb
Host smart-f499ae4e-8bd4-48f4-9430-409bfb9b5abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850776179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3850776179
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1900826739
Short name T455
Test name
Test status
Simulation time 5667746037 ps
CPU time 13.16 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:45:24 PM PST 24
Peak memory 201056 kb
Host smart-dabc26f2-4f4e-41d0-a291-f464e9424d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900826739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1900826739
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1246348020
Short name T496
Test name
Test status
Simulation time 184977086879 ps
CPU time 425.19 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:52:28 PM PST 24
Peak memory 201300 kb
Host smart-9e707f1f-c32d-487a-bb96-14b059fb8438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246348020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1246348020
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.4279637650
Short name T208
Test name
Test status
Simulation time 107162413911 ps
CPU time 130.63 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:47:23 PM PST 24
Peak memory 209832 kb
Host smart-5cc3d567-ac17-4902-80b0-e21ef63bed70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279637650 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.4279637650
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2480263845
Short name T510
Test name
Test status
Simulation time 493844611 ps
CPU time 1.85 seconds
Started Mar 05 12:45:31 PM PST 24
Finished Mar 05 12:45:33 PM PST 24
Peak memory 200868 kb
Host smart-9c9c89ce-fe15-411b-8521-75625b25117e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480263845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2480263845
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.783238217
Short name T120
Test name
Test status
Simulation time 502146291111 ps
CPU time 223.74 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:48:58 PM PST 24
Peak memory 201076 kb
Host smart-c43bdf78-ccba-4b06-a2df-0b06684415ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783238217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.783238217
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.837510759
Short name T236
Test name
Test status
Simulation time 331910909651 ps
CPU time 416.5 seconds
Started Mar 05 12:45:27 PM PST 24
Finished Mar 05 12:52:24 PM PST 24
Peak memory 201128 kb
Host smart-3be8c4af-e3c7-4b32-9e4d-cf8244533b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837510759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.837510759
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.842260180
Short name T269
Test name
Test status
Simulation time 329742693189 ps
CPU time 685.17 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:56:59 PM PST 24
Peak memory 201200 kb
Host smart-d14ba0c0-4ecc-4fa3-bf82-14c87908b384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842260180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.842260180
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1277997366
Short name T419
Test name
Test status
Simulation time 490695881480 ps
CPU time 262.97 seconds
Started Mar 05 12:45:19 PM PST 24
Finished Mar 05 12:49:48 PM PST 24
Peak memory 201124 kb
Host smart-616bb256-4774-4fa6-87ff-4bb3acc6bf99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277997366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1277997366
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3309379978
Short name T661
Test name
Test status
Simulation time 167064269195 ps
CPU time 102.05 seconds
Started Mar 05 12:45:25 PM PST 24
Finished Mar 05 12:47:12 PM PST 24
Peak memory 201040 kb
Host smart-fbce485f-f25e-407a-a91d-47b197e2b527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309379978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3309379978
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2550741988
Short name T386
Test name
Test status
Simulation time 165394641527 ps
CPU time 89.24 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:46:39 PM PST 24
Peak memory 201116 kb
Host smart-fc022bc7-b5da-4253-a6d4-ecc1eeadcbd6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550741988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2550741988
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2065188931
Short name T646
Test name
Test status
Simulation time 167299462180 ps
CPU time 373.33 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:51:42 PM PST 24
Peak memory 201084 kb
Host smart-a2f74193-3162-4318-8456-3aefc4cff567
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065188931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2065188931
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.4112674007
Short name T742
Test name
Test status
Simulation time 163757621641 ps
CPU time 43.36 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:46:04 PM PST 24
Peak memory 201124 kb
Host smart-9685743b-299e-46b5-b1cc-951610aa4c24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112674007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.4112674007
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4114410236
Short name T31
Test name
Test status
Simulation time 125487073966 ps
CPU time 413.37 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:52:05 PM PST 24
Peak memory 201712 kb
Host smart-23e41901-4c61-49d5-a99b-2fe2ab26b377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114410236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4114410236
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3027826370
Short name T589
Test name
Test status
Simulation time 37620824302 ps
CPU time 26.83 seconds
Started Mar 05 12:45:18 PM PST 24
Finished Mar 05 12:45:44 PM PST 24
Peak memory 200992 kb
Host smart-39e9fa9f-1f27-48bd-874a-d239d6387da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027826370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3027826370
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2963027314
Short name T776
Test name
Test status
Simulation time 3580516694 ps
CPU time 9.85 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:45:30 PM PST 24
Peak memory 200924 kb
Host smart-4ede8565-6a11-4045-97db-f24d2ec74fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963027314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2963027314
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.589495178
Short name T567
Test name
Test status
Simulation time 6063771032 ps
CPU time 7.42 seconds
Started Mar 05 12:45:22 PM PST 24
Finished Mar 05 12:45:29 PM PST 24
Peak memory 201004 kb
Host smart-e277d16f-14a5-4e55-ba33-f84660425372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589495178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.589495178
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3063683906
Short name T59
Test name
Test status
Simulation time 101137070966 ps
CPU time 273.01 seconds
Started Mar 05 12:45:17 PM PST 24
Finished Mar 05 12:49:50 PM PST 24
Peak memory 217860 kb
Host smart-85b02630-7110-4fd2-abf1-b7920d8e2c30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063683906 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3063683906
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.321928770
Short name T376
Test name
Test status
Simulation time 348734988 ps
CPU time 1.02 seconds
Started Mar 05 12:45:15 PM PST 24
Finished Mar 05 12:45:16 PM PST 24
Peak memory 200908 kb
Host smart-4536fcd9-2140-4b9b-82e0-e8a11d141b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321928770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.321928770
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1187003146
Short name T424
Test name
Test status
Simulation time 165472676213 ps
CPU time 388.82 seconds
Started Mar 05 12:45:17 PM PST 24
Finished Mar 05 12:51:46 PM PST 24
Peak memory 201120 kb
Host smart-24293a4e-8dba-45dd-8bc1-16ee1b5be59c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187003146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1187003146
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4131740062
Short name T594
Test name
Test status
Simulation time 164707677414 ps
CPU time 38.64 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:46:19 PM PST 24
Peak memory 201108 kb
Host smart-7ccac35b-b8d8-4fa4-a6c5-54bbcbe57223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131740062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4131740062
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1451964801
Short name T702
Test name
Test status
Simulation time 161968608759 ps
CPU time 202.79 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:48:44 PM PST 24
Peak memory 201068 kb
Host smart-76f537b5-6bb3-4b48-bcbf-59405531f95b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451964801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1451964801
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1824149871
Short name T121
Test name
Test status
Simulation time 168002899427 ps
CPU time 360.98 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:51:21 PM PST 24
Peak memory 201200 kb
Host smart-5a547528-fd7f-4520-950a-7eb0ae567e86
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824149871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1824149871
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.946930355
Short name T637
Test name
Test status
Simulation time 168499078666 ps
CPU time 40.13 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:45:52 PM PST 24
Peak memory 201216 kb
Host smart-84ddb7ff-d671-4f8a-99ca-922cc8c32330
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946930355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.946930355
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3310948083
Short name T497
Test name
Test status
Simulation time 120736621360 ps
CPU time 415.25 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:52:15 PM PST 24
Peak memory 201536 kb
Host smart-7514c090-0291-4bc2-bbef-2535e1c07a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310948083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3310948083
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2519104228
Short name T492
Test name
Test status
Simulation time 35066826242 ps
CPU time 85.1 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:46:59 PM PST 24
Peak memory 200968 kb
Host smart-305eb87b-87ef-4646-9408-64b31b8c1453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519104228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2519104228
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2837469248
Short name T355
Test name
Test status
Simulation time 3996210059 ps
CPU time 5.09 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:45:25 PM PST 24
Peak memory 201032 kb
Host smart-93a8b9bc-be8a-43b2-8d7e-a042c73ddfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837469248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2837469248
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4230116846
Short name T177
Test name
Test status
Simulation time 5797488833 ps
CPU time 13.01 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:45:24 PM PST 24
Peak memory 201052 kb
Host smart-dd6d80bf-ac80-4490-a55d-2d68196018c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230116846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4230116846
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.102681821
Short name T659
Test name
Test status
Simulation time 308745151 ps
CPU time 1.28 seconds
Started Mar 05 12:45:30 PM PST 24
Finished Mar 05 12:45:32 PM PST 24
Peak memory 200752 kb
Host smart-a5675394-3d2d-4a83-8f02-a706ca300cf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102681821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.102681821
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.4225447033
Short name T67
Test name
Test status
Simulation time 171984123600 ps
CPU time 206.88 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:48:47 PM PST 24
Peak memory 201176 kb
Host smart-f741bc9f-65d8-4e70-b243-eaaf58d05d9f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225447033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.4225447033
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1681910328
Short name T155
Test name
Test status
Simulation time 323428214891 ps
CPU time 183.76 seconds
Started Mar 05 12:45:29 PM PST 24
Finished Mar 05 12:48:33 PM PST 24
Peak memory 201140 kb
Host smart-4d218615-938a-4f68-b359-888134d560ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681910328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1681910328
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1785021866
Short name T687
Test name
Test status
Simulation time 328482075189 ps
CPU time 50.74 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:46:24 PM PST 24
Peak memory 201124 kb
Host smart-b123574c-507c-4572-99a8-30534b11d70d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785021866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1785021866
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.266604250
Short name T595
Test name
Test status
Simulation time 489905867136 ps
CPU time 1093.68 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 01:03:25 PM PST 24
Peak memory 201200 kb
Host smart-95cfe6ca-b390-451e-9572-d398480a29f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266604250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.266604250
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.889763944
Short name T495
Test name
Test status
Simulation time 163710479873 ps
CPU time 30.82 seconds
Started Mar 05 12:45:25 PM PST 24
Finished Mar 05 12:45:56 PM PST 24
Peak memory 201116 kb
Host smart-c3830b19-261f-47dd-8788-1c88656a5cad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=889763944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.889763944
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3363927648
Short name T117
Test name
Test status
Simulation time 327814667510 ps
CPU time 760.02 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:58:20 PM PST 24
Peak memory 201116 kb
Host smart-f9d0902b-9cb5-4b08-b5b9-7f7850fe93dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363927648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3363927648
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3284944571
Short name T699
Test name
Test status
Simulation time 53917197509 ps
CPU time 332.99 seconds
Started Mar 05 12:45:26 PM PST 24
Finished Mar 05 12:50:59 PM PST 24
Peak memory 201400 kb
Host smart-5744bf7f-cf0c-4b0c-a17f-c07c74b268d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284944571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3284944571
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.603271564
Short name T6
Test name
Test status
Simulation time 26329672041 ps
CPU time 17.27 seconds
Started Mar 05 12:45:13 PM PST 24
Finished Mar 05 12:45:31 PM PST 24
Peak memory 201060 kb
Host smart-63019b9e-f29b-4194-af06-c8fcacd6db3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603271564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.603271564
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2441829301
Short name T503
Test name
Test status
Simulation time 5284533275 ps
CPU time 5.56 seconds
Started Mar 05 12:45:30 PM PST 24
Finished Mar 05 12:45:35 PM PST 24
Peak memory 201064 kb
Host smart-b56307d8-fb4b-4dd2-b216-64f2394e207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441829301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2441829301
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.83791186
Short name T680
Test name
Test status
Simulation time 5735077556 ps
CPU time 14.25 seconds
Started Mar 05 12:45:36 PM PST 24
Finished Mar 05 12:45:50 PM PST 24
Peak memory 201044 kb
Host smart-e1eb9084-54db-43fa-87b6-8eb736b64c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83791186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.83791186
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3407793016
Short name T399
Test name
Test status
Simulation time 328394236256 ps
CPU time 135.56 seconds
Started Mar 05 12:45:23 PM PST 24
Finished Mar 05 12:47:38 PM PST 24
Peak memory 201084 kb
Host smart-2e5a9fdd-97b2-40c7-a72f-878074cb789a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407793016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3407793016
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.4019646402
Short name T186
Test name
Test status
Simulation time 41842267509 ps
CPU time 105.2 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:46:59 PM PST 24
Peak memory 209764 kb
Host smart-6e25747d-c18b-4d58-b672-2510078496ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019646402 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.4019646402
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2065881278
Short name T575
Test name
Test status
Simulation time 510698067 ps
CPU time 0.94 seconds
Started Mar 05 12:44:48 PM PST 24
Finished Mar 05 12:44:49 PM PST 24
Peak memory 200932 kb
Host smart-f4097d19-7f3f-46c3-a0fa-518a9f8e0b95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065881278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2065881278
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2110869045
Short name T218
Test name
Test status
Simulation time 330738313806 ps
CPU time 378.25 seconds
Started Mar 05 12:44:49 PM PST 24
Finished Mar 05 12:51:07 PM PST 24
Peak memory 201120 kb
Host smart-ce0f90df-f1d7-4655-8d59-c48f4de4c83f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110869045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2110869045
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.1642158445
Short name T136
Test name
Test status
Simulation time 164649829813 ps
CPU time 236.9 seconds
Started Mar 05 12:44:51 PM PST 24
Finished Mar 05 12:48:48 PM PST 24
Peak memory 201136 kb
Host smart-c4053985-e566-4272-b087-28b597146cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642158445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.1642158445
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2946757374
Short name T494
Test name
Test status
Simulation time 159948338273 ps
CPU time 199.73 seconds
Started Mar 05 12:45:03 PM PST 24
Finished Mar 05 12:48:23 PM PST 24
Peak memory 201196 kb
Host smart-219e4dda-bdd5-4fc7-baea-f0a169ebc9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946757374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2946757374
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3781436574
Short name T512
Test name
Test status
Simulation time 166340878924 ps
CPU time 369.27 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:51:11 PM PST 24
Peak memory 201164 kb
Host smart-102270ef-fd43-4791-ac6b-cd7d6cfb9722
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781436574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3781436574
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2506213536
Short name T12
Test name
Test status
Simulation time 494591462957 ps
CPU time 243.41 seconds
Started Mar 05 12:44:53 PM PST 24
Finished Mar 05 12:48:57 PM PST 24
Peak memory 201124 kb
Host smart-4907dad7-89b1-475e-84e2-2f34c4010899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506213536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2506213536
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.869860815
Short name T559
Test name
Test status
Simulation time 161443636850 ps
CPU time 337.95 seconds
Started Mar 05 12:44:54 PM PST 24
Finished Mar 05 12:50:32 PM PST 24
Peak memory 201056 kb
Host smart-671d40f0-e20f-4194-b1a7-19a4d95454a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=869860815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.869860815
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2257749947
Short name T774
Test name
Test status
Simulation time 337930452608 ps
CPU time 450.25 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 12:52:25 PM PST 24
Peak memory 201128 kb
Host smart-74bf4e29-7497-4413-9008-7fa8b3266469
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257749947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2257749947
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.209971712
Short name T513
Test name
Test status
Simulation time 121806105119 ps
CPU time 675.92 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 12:56:16 PM PST 24
Peak memory 201568 kb
Host smart-1b3c0cf7-3dd1-4d7d-9af2-ecb738189440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209971712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.209971712
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.4229163760
Short name T481
Test name
Test status
Simulation time 31297061005 ps
CPU time 19.88 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:45:21 PM PST 24
Peak memory 201060 kb
Host smart-a83769f4-1a34-4589-8013-8f9e15b7576e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229163760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.4229163760
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3586529042
Short name T410
Test name
Test status
Simulation time 5331524104 ps
CPU time 6.85 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:45:08 PM PST 24
Peak memory 201060 kb
Host smart-f95ccbe9-acd3-45f2-89ec-3a917f3e2418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586529042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3586529042
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.669031528
Short name T47
Test name
Test status
Simulation time 4035685151 ps
CPU time 5.58 seconds
Started Mar 05 12:45:02 PM PST 24
Finished Mar 05 12:45:08 PM PST 24
Peak memory 216484 kb
Host smart-70470f6c-5b7c-4bee-8679-8cddf5a715aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669031528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.669031528
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2453187916
Short name T169
Test name
Test status
Simulation time 5831914384 ps
CPU time 4.43 seconds
Started Mar 05 12:44:35 PM PST 24
Finished Mar 05 12:44:39 PM PST 24
Peak memory 201008 kb
Host smart-52a6318e-7bb8-432f-9734-3898fe794811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453187916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2453187916
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1465906972
Short name T459
Test name
Test status
Simulation time 112260723791 ps
CPU time 584.15 seconds
Started Mar 05 12:44:35 PM PST 24
Finished Mar 05 12:54:20 PM PST 24
Peak memory 201564 kb
Host smart-1ac9c4c5-fe18-4c95-a0cb-625b3a77a87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465906972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1465906972
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.718983776
Short name T228
Test name
Test status
Simulation time 59103038114 ps
CPU time 123.1 seconds
Started Mar 05 12:44:51 PM PST 24
Finished Mar 05 12:46:55 PM PST 24
Peak memory 201216 kb
Host smart-c657c7a9-54c5-4cf0-8dd4-d033e287364b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718983776 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.718983776
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2234382287
Short name T69
Test name
Test status
Simulation time 511878015 ps
CPU time 0.88 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:45:15 PM PST 24
Peak memory 200820 kb
Host smart-4892940b-3325-4efa-8685-2b2a5945014a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234382287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2234382287
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3500257113
Short name T222
Test name
Test status
Simulation time 164079861661 ps
CPU time 45.7 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:46:06 PM PST 24
Peak memory 201204 kb
Host smart-26508a66-d676-496a-9ea9-cd88b37a6b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500257113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3500257113
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1147965573
Short name T275
Test name
Test status
Simulation time 330166598150 ps
CPU time 781.09 seconds
Started Mar 05 12:45:24 PM PST 24
Finished Mar 05 12:58:25 PM PST 24
Peak memory 201220 kb
Host smart-363bea06-f5ab-427e-8bfb-96b3f111ace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147965573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1147965573
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2061070844
Short name T782
Test name
Test status
Simulation time 336511061558 ps
CPU time 441.13 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:52:42 PM PST 24
Peak memory 201056 kb
Host smart-ad48c77a-d38a-455c-a279-69d1018ad41a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061070844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2061070844
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2504045891
Short name T534
Test name
Test status
Simulation time 500942203847 ps
CPU time 1194.62 seconds
Started Mar 05 12:45:19 PM PST 24
Finished Mar 05 01:05:14 PM PST 24
Peak memory 201068 kb
Host smart-54cd4cc3-1732-4fed-a494-463e944de7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504045891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2504045891
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1525853499
Short name T383
Test name
Test status
Simulation time 319129441825 ps
CPU time 718.3 seconds
Started Mar 05 12:45:27 PM PST 24
Finished Mar 05 12:57:25 PM PST 24
Peak memory 200952 kb
Host smart-7e422a37-ea62-4f6b-8c2d-b2b315f274e6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525853499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1525853499
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.405341377
Short name T322
Test name
Test status
Simulation time 603275257587 ps
CPU time 362.85 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:51:14 PM PST 24
Peak memory 201084 kb
Host smart-0054da3a-966d-4224-9433-a2cb0afd254c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405341377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.405341377
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.286258071
Short name T532
Test name
Test status
Simulation time 494188830757 ps
CPU time 308.4 seconds
Started Mar 05 12:45:27 PM PST 24
Finished Mar 05 12:50:35 PM PST 24
Peak memory 201096 kb
Host smart-acb15025-9643-4deb-87bd-05f71254519d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286258071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.286258071
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2794936184
Short name T184
Test name
Test status
Simulation time 36392245510 ps
CPU time 78.17 seconds
Started Mar 05 12:45:41 PM PST 24
Finished Mar 05 12:46:59 PM PST 24
Peak memory 201044 kb
Host smart-74326493-7a60-40df-b679-d0d6acf74f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794936184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2794936184
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2826613668
Short name T727
Test name
Test status
Simulation time 3852806069 ps
CPU time 9.82 seconds
Started Mar 05 12:45:29 PM PST 24
Finished Mar 05 12:45:39 PM PST 24
Peak memory 201000 kb
Host smart-0b7ee45f-0569-4ad2-ac57-9e1e03891050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826613668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2826613668
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1303253905
Short name T113
Test name
Test status
Simulation time 5802498829 ps
CPU time 8.31 seconds
Started Mar 05 12:45:25 PM PST 24
Finished Mar 05 12:45:33 PM PST 24
Peak memory 200880 kb
Host smart-1d8e5647-e788-4b6a-8d96-3cf2684d631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303253905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1303253905
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.1659384820
Short name T734
Test name
Test status
Simulation time 326205427998 ps
CPU time 818.97 seconds
Started Mar 05 12:45:38 PM PST 24
Finished Mar 05 12:59:18 PM PST 24
Peak memory 201172 kb
Host smart-3a9e8764-48e7-4867-8517-5b270c68f87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659384820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.1659384820
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1461945935
Short name T466
Test name
Test status
Simulation time 476928991 ps
CPU time 0.82 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 12:45:15 PM PST 24
Peak memory 200896 kb
Host smart-69e9bad7-58a6-4af5-bd74-fcc71943ac48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461945935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1461945935
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1323550395
Short name T234
Test name
Test status
Simulation time 495602109427 ps
CPU time 769.98 seconds
Started Mar 05 12:45:27 PM PST 24
Finished Mar 05 12:58:17 PM PST 24
Peak memory 201140 kb
Host smart-7625b9e5-90de-4c5c-b281-6937a962d2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323550395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1323550395
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1299453571
Short name T703
Test name
Test status
Simulation time 331345070605 ps
CPU time 706.39 seconds
Started Mar 05 12:45:29 PM PST 24
Finished Mar 05 12:57:15 PM PST 24
Peak memory 201088 kb
Host smart-c73a8e36-b727-498b-b807-a746825cc34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299453571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1299453571
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2473871279
Short name T739
Test name
Test status
Simulation time 487110147313 ps
CPU time 293.02 seconds
Started Mar 05 12:45:23 PM PST 24
Finished Mar 05 12:50:17 PM PST 24
Peak memory 201124 kb
Host smart-91bf56a3-80f4-4e44-8c2a-0081c879ec79
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473871279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2473871279
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.679254445
Short name T716
Test name
Test status
Simulation time 500735783881 ps
CPU time 291.59 seconds
Started Mar 05 12:45:13 PM PST 24
Finished Mar 05 12:50:04 PM PST 24
Peak memory 201032 kb
Host smart-a252cb92-7b1a-487f-a7a1-ba7d5b1aeac5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679254445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.679254445
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1483773547
Short name T604
Test name
Test status
Simulation time 329287946734 ps
CPU time 809.92 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:58:58 PM PST 24
Peak memory 201184 kb
Host smart-70d3381a-22e8-4fb6-9fbb-cf989f940f9b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483773547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1483773547
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2362982506
Short name T672
Test name
Test status
Simulation time 77132261271 ps
CPU time 275.67 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 12:50:10 PM PST 24
Peak memory 201572 kb
Host smart-0e105292-ab96-48c0-b4d6-caa50ce13fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362982506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2362982506
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4072363537
Short name T456
Test name
Test status
Simulation time 28492071963 ps
CPU time 30.92 seconds
Started Mar 05 12:45:23 PM PST 24
Finished Mar 05 12:45:54 PM PST 24
Peak memory 201044 kb
Host smart-f6af982c-eada-4d6e-b78a-13a62bd747a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072363537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4072363537
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2254633423
Short name T458
Test name
Test status
Simulation time 4843668393 ps
CPU time 11.12 seconds
Started Mar 05 12:45:26 PM PST 24
Finished Mar 05 12:45:37 PM PST 24
Peak memory 201008 kb
Host smart-e57faefc-7684-405f-9a26-28341c92a650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254633423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2254633423
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.295329317
Short name T469
Test name
Test status
Simulation time 5831625774 ps
CPU time 8.46 seconds
Started Mar 05 12:45:29 PM PST 24
Finished Mar 05 12:45:37 PM PST 24
Peak memory 200944 kb
Host smart-1b5761a7-37e2-4bb6-8f65-1a8f87a613fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295329317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.295329317
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.991627787
Short name T255
Test name
Test status
Simulation time 128291729230 ps
CPU time 393.32 seconds
Started Mar 05 12:45:31 PM PST 24
Finished Mar 05 12:52:04 PM PST 24
Peak memory 209772 kb
Host smart-bae73f90-8ff8-4e63-802a-296579ba4178
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991627787 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.991627787
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3074571536
Short name T666
Test name
Test status
Simulation time 327099082 ps
CPU time 1.41 seconds
Started Mar 05 12:45:30 PM PST 24
Finished Mar 05 12:45:31 PM PST 24
Peak memory 200928 kb
Host smart-ac05a06c-4a20-4f2d-8a58-aa547bc83468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074571536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3074571536
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.2603178955
Short name T16
Test name
Test status
Simulation time 167149426566 ps
CPU time 178.48 seconds
Started Mar 05 12:45:18 PM PST 24
Finished Mar 05 12:48:17 PM PST 24
Peak memory 201080 kb
Host smart-f2fff598-1c93-4662-9f4d-72f0aeb6c301
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603178955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.2603178955
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.559412614
Short name T242
Test name
Test status
Simulation time 168429621381 ps
CPU time 100.66 seconds
Started Mar 05 12:45:30 PM PST 24
Finished Mar 05 12:47:11 PM PST 24
Peak memory 201112 kb
Host smart-582fe73c-cb1c-4a64-b8a9-27dcfc8f1969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559412614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.559412614
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3968657597
Short name T679
Test name
Test status
Simulation time 161364009111 ps
CPU time 173.15 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:48:21 PM PST 24
Peak memory 201100 kb
Host smart-e4e75279-0dac-4833-8f87-9fee9919159c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968657597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3968657597
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3978976587
Short name T429
Test name
Test status
Simulation time 164804374879 ps
CPU time 390.59 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:52:04 PM PST 24
Peak memory 201088 kb
Host smart-787d0b13-9fbf-4c9a-b0bd-dfd51a77d085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978976587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3978976587
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2652969432
Short name T648
Test name
Test status
Simulation time 168263871248 ps
CPU time 196.03 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:48:58 PM PST 24
Peak memory 201096 kb
Host smart-90391cfc-0b8e-4b58-aa1d-7609b7878a62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652969432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2652969432
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3718032496
Short name T287
Test name
Test status
Simulation time 501674340878 ps
CPU time 1219.84 seconds
Started Mar 05 12:45:25 PM PST 24
Finished Mar 05 01:05:45 PM PST 24
Peak memory 201140 kb
Host smart-7c2c2e8c-3081-4e70-b3eb-b73ce81818c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718032496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3718032496
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1578773518
Short name T463
Test name
Test status
Simulation time 163416151426 ps
CPU time 193.16 seconds
Started Mar 05 12:45:25 PM PST 24
Finished Mar 05 12:48:38 PM PST 24
Peak memory 201108 kb
Host smart-ce0e027b-559a-4856-8a02-f278a41cbee0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578773518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1578773518
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3570240399
Short name T517
Test name
Test status
Simulation time 113902083076 ps
CPU time 347.86 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:50:59 PM PST 24
Peak memory 201512 kb
Host smart-0c4bea4b-6c7a-4e29-bc82-7741b296303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570240399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3570240399
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.550162003
Short name T726
Test name
Test status
Simulation time 29994392758 ps
CPU time 69.81 seconds
Started Mar 05 12:45:31 PM PST 24
Finished Mar 05 12:46:41 PM PST 24
Peak memory 201060 kb
Host smart-d4029995-2ce0-490c-98f7-61ebc30029ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550162003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.550162003
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2969502225
Short name T664
Test name
Test status
Simulation time 3196947322 ps
CPU time 2.48 seconds
Started Mar 05 12:45:19 PM PST 24
Finished Mar 05 12:45:22 PM PST 24
Peak memory 201064 kb
Host smart-38975250-ae5b-4d2e-837a-169d09a3a55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969502225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2969502225
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2873002110
Short name T472
Test name
Test status
Simulation time 5952451367 ps
CPU time 4.58 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:45:26 PM PST 24
Peak memory 200952 kb
Host smart-def63be9-e43d-4807-ae64-b05722f2d8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873002110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2873002110
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2324369078
Short name T219
Test name
Test status
Simulation time 392266486721 ps
CPU time 773.75 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:58:21 PM PST 24
Peak memory 201024 kb
Host smart-98b1fc19-c9f0-42e2-a9ae-2f305fea7585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324369078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2324369078
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1588543275
Short name T707
Test name
Test status
Simulation time 374477694 ps
CPU time 1.01 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:45:30 PM PST 24
Peak memory 200756 kb
Host smart-c8eb62cf-1817-4bd7-b49b-06c3cc62f8d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588543275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1588543275
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.4119841058
Short name T244
Test name
Test status
Simulation time 334377105233 ps
CPU time 782.6 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:58:45 PM PST 24
Peak memory 201064 kb
Host smart-c90178de-32ba-41d7-b5b0-d5311e133d2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119841058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.4119841058
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2016061820
Short name T168
Test name
Test status
Simulation time 322135564994 ps
CPU time 762.53 seconds
Started Mar 05 12:45:24 PM PST 24
Finished Mar 05 12:58:07 PM PST 24
Peak memory 201228 kb
Host smart-6713ba3e-04a9-4660-b1aa-47ba7940e916
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016061820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2016061820
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2463406381
Short name T153
Test name
Test status
Simulation time 488949110341 ps
CPU time 203.16 seconds
Started Mar 05 12:45:30 PM PST 24
Finished Mar 05 12:48:53 PM PST 24
Peak memory 201200 kb
Host smart-5ea8363e-d1c3-4dc3-87d6-0d1325fcc436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463406381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2463406381
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2386519910
Short name T713
Test name
Test status
Simulation time 163918068265 ps
CPU time 79.07 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:47:00 PM PST 24
Peak memory 201172 kb
Host smart-7835e5a0-704c-4678-a14c-3efaad98a653
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386519910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2386519910
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1374480974
Short name T609
Test name
Test status
Simulation time 161737947483 ps
CPU time 396.88 seconds
Started Mar 05 12:45:25 PM PST 24
Finished Mar 05 12:52:02 PM PST 24
Peak memory 201136 kb
Host smart-eb2ecbe3-e4c0-45bd-9b3b-cf65d49304c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374480974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1374480974
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1339375949
Short name T377
Test name
Test status
Simulation time 495689599561 ps
CPU time 153.68 seconds
Started Mar 05 12:45:32 PM PST 24
Finished Mar 05 12:48:06 PM PST 24
Peak memory 200956 kb
Host smart-d2fbd9cc-39f0-4dba-9346-623e8df021ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339375949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1339375949
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1713230540
Short name T706
Test name
Test status
Simulation time 28674359011 ps
CPU time 62.6 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:46:30 PM PST 24
Peak memory 200872 kb
Host smart-713f08bb-10df-4c9d-9ba9-d430ab70a4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713230540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1713230540
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3144462121
Short name T468
Test name
Test status
Simulation time 4115186252 ps
CPU time 3.05 seconds
Started Mar 05 12:45:49 PM PST 24
Finished Mar 05 12:45:52 PM PST 24
Peak memory 200892 kb
Host smart-3bddeeba-8121-4643-a896-048777f5eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144462121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3144462121
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.4208399665
Short name T346
Test name
Test status
Simulation time 6035785269 ps
CPU time 4.23 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 12:45:40 PM PST 24
Peak memory 201008 kb
Host smart-7d813f4d-748c-4260-a714-d0c75aef71df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208399665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.4208399665
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2359654641
Short name T682
Test name
Test status
Simulation time 369554229284 ps
CPU time 788.01 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:58:41 PM PST 24
Peak memory 201172 kb
Host smart-be32dfbf-22f3-4a04-b718-1c295b4374f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359654641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2359654641
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1968762249
Short name T323
Test name
Test status
Simulation time 24624510118 ps
CPU time 77.77 seconds
Started Mar 05 12:45:32 PM PST 24
Finished Mar 05 12:46:50 PM PST 24
Peak memory 209836 kb
Host smart-827a0446-9980-40f3-84c6-6a3a32cf5eb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968762249 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1968762249
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1340910799
Short name T723
Test name
Test status
Simulation time 499151786 ps
CPU time 1.73 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:45:35 PM PST 24
Peak memory 200840 kb
Host smart-f167ceaf-b2f3-4bc6-b912-8843e2c57d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340910799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1340910799
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.4195478558
Short name T285
Test name
Test status
Simulation time 160238385108 ps
CPU time 42.57 seconds
Started Mar 05 12:45:36 PM PST 24
Finished Mar 05 12:46:19 PM PST 24
Peak memory 201120 kb
Host smart-4883bff6-2d03-4ca5-a53b-a4191ebc5e7d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195478558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.4195478558
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3205823346
Short name T209
Test name
Test status
Simulation time 487259113578 ps
CPU time 282.29 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:50:22 PM PST 24
Peak memory 201140 kb
Host smart-eae01f6e-ed10-4bc0-aec9-0a0f6428c9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205823346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3205823346
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3507716304
Short name T416
Test name
Test status
Simulation time 330433733046 ps
CPU time 186.42 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:48:27 PM PST 24
Peak memory 201228 kb
Host smart-4794fb85-1437-48b4-9cc9-d91a85fdf997
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507716304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3507716304
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.3488367801
Short name T199
Test name
Test status
Simulation time 491670609552 ps
CPU time 285.07 seconds
Started Mar 05 12:45:16 PM PST 24
Finished Mar 05 12:50:01 PM PST 24
Peak memory 201180 kb
Host smart-d7512b72-e4a6-4bf2-af0d-c43fbb6f3c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488367801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.3488367801
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.499736379
Short name T487
Test name
Test status
Simulation time 326941518925 ps
CPU time 737.28 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 12:57:53 PM PST 24
Peak memory 201120 kb
Host smart-036f20b7-013d-4426-8f92-126dc5254176
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=499736379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fixe
d.499736379
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2203420694
Short name T324
Test name
Test status
Simulation time 499142465843 ps
CPU time 191.35 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:48:54 PM PST 24
Peak memory 201136 kb
Host smart-05c4d731-6e4f-4abf-b764-18653feb33c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203420694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2203420694
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1104551834
Short name T777
Test name
Test status
Simulation time 332134105678 ps
CPU time 62.74 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:46:31 PM PST 24
Peak memory 201124 kb
Host smart-f0206d5b-b9ac-490c-b069-6d4399604af4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104551834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1104551834
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.2218038577
Short name T427
Test name
Test status
Simulation time 61194276961 ps
CPU time 297.35 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:50:40 PM PST 24
Peak memory 201488 kb
Host smart-a89bc132-a954-4e0e-9fa2-35fd2514e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218038577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.2218038577
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.245379676
Short name T460
Test name
Test status
Simulation time 26040043153 ps
CPU time 61.13 seconds
Started Mar 05 12:45:38 PM PST 24
Finished Mar 05 12:46:39 PM PST 24
Peak memory 200988 kb
Host smart-e365a3b7-7822-4f2a-815d-1f18474f7837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245379676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.245379676
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.4267194209
Short name T403
Test name
Test status
Simulation time 5443190923 ps
CPU time 13.48 seconds
Started Mar 05 12:45:31 PM PST 24
Finished Mar 05 12:45:45 PM PST 24
Peak memory 201060 kb
Host smart-3ba1f708-4435-4569-b505-6301e7d41a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267194209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4267194209
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3887836527
Short name T448
Test name
Test status
Simulation time 6123730041 ps
CPU time 8.3 seconds
Started Mar 05 12:45:21 PM PST 24
Finished Mar 05 12:45:30 PM PST 24
Peak memory 201004 kb
Host smart-82f61722-5a9f-4a4c-b7da-488ddaa2b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887836527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3887836527
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.640220148
Short name T292
Test name
Test status
Simulation time 468207412460 ps
CPU time 1254.36 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 01:06:39 PM PST 24
Peak memory 209712 kb
Host smart-5411c71b-5a48-44e6-8aa3-51411852a4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640220148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
640220148
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2508943355
Short name T60
Test name
Test status
Simulation time 426321030228 ps
CPU time 181.43 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:48:41 PM PST 24
Peak memory 209524 kb
Host smart-6b2b699e-27e7-4496-9285-069240e3002a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508943355 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2508943355
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1871281789
Short name T387
Test name
Test status
Simulation time 554917610 ps
CPU time 1.01 seconds
Started Mar 05 12:45:45 PM PST 24
Finished Mar 05 12:45:47 PM PST 24
Peak memory 200888 kb
Host smart-8bc9cd46-e12d-4c2d-b42d-a164ae631376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871281789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1871281789
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3126344907
Short name T317
Test name
Test status
Simulation time 162564332471 ps
CPU time 111.98 seconds
Started Mar 05 12:45:34 PM PST 24
Finished Mar 05 12:47:26 PM PST 24
Peak memory 201200 kb
Host smart-589b2291-2ba1-4fab-b6b2-9f58362ac67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126344907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3126344907
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2111154894
Short name T437
Test name
Test status
Simulation time 500917326235 ps
CPU time 292.66 seconds
Started Mar 05 12:45:36 PM PST 24
Finished Mar 05 12:50:29 PM PST 24
Peak memory 201120 kb
Host smart-99d61ddf-3b7b-40ab-a432-8f86b174e2cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111154894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2111154894
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.3874157429
Short name T507
Test name
Test status
Simulation time 160476238219 ps
CPU time 181.89 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:48:42 PM PST 24
Peak memory 201144 kb
Host smart-84e5168c-eed8-4e67-881f-dd032a1739f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874157429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.3874157429
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.12122167
Short name T592
Test name
Test status
Simulation time 498336434738 ps
CPU time 522.38 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 12:54:18 PM PST 24
Peak memory 201180 kb
Host smart-ed0cec41-27ab-4f06-8737-76df53d1a6f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=12122167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixed
.12122167
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4173944816
Short name T684
Test name
Test status
Simulation time 165453466266 ps
CPU time 344.42 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 12:51:24 PM PST 24
Peak memory 201196 kb
Host smart-c23376c9-64da-4fa5-b342-6f02330d0f66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173944816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4173944816
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.598109909
Short name T441
Test name
Test status
Simulation time 331032970233 ps
CPU time 724.67 seconds
Started Mar 05 12:45:37 PM PST 24
Finished Mar 05 12:57:42 PM PST 24
Peak memory 201124 kb
Host smart-00203612-b153-4c25-8f4e-ff9ff3251aba
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598109909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
adc_ctrl_filters_wakeup_fixed.598109909
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2300571554
Short name T791
Test name
Test status
Simulation time 83997497838 ps
CPU time 488.66 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:53:42 PM PST 24
Peak memory 201456 kb
Host smart-b8d0e4a4-c5e5-4585-add2-d8f8cf763aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300571554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2300571554
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3172098433
Short name T700
Test name
Test status
Simulation time 27364827081 ps
CPU time 6.77 seconds
Started Mar 05 12:45:29 PM PST 24
Finished Mar 05 12:45:36 PM PST 24
Peak memory 201044 kb
Host smart-669bf649-d309-429f-9989-b5eaa2abd5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172098433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3172098433
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1310194460
Short name T643
Test name
Test status
Simulation time 5437852154 ps
CPU time 13.88 seconds
Started Mar 05 12:45:30 PM PST 24
Finished Mar 05 12:45:44 PM PST 24
Peak memory 201060 kb
Host smart-dd42caa0-9078-48e1-b8e5-bbe38061a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310194460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1310194460
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.4504733
Short name T391
Test name
Test status
Simulation time 5879060484 ps
CPU time 2.98 seconds
Started Mar 05 12:45:29 PM PST 24
Finished Mar 05 12:45:32 PM PST 24
Peak memory 201040 kb
Host smart-1b1f3fa0-da7a-4ca3-bc63-60c44c627c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4504733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.4504733
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.388455450
Short name T279
Test name
Test status
Simulation time 172479245988 ps
CPU time 418.09 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:52:38 PM PST 24
Peak memory 201200 kb
Host smart-b443bd90-608f-46d3-bf4c-c3373cea89e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388455450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
388455450
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.830927073
Short name T520
Test name
Test status
Simulation time 441517443 ps
CPU time 1.69 seconds
Started Mar 05 12:45:36 PM PST 24
Finished Mar 05 12:45:38 PM PST 24
Peak memory 200832 kb
Host smart-a9a9cebf-0081-4305-88b7-f77498846288
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830927073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.830927073
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1998824223
Short name T297
Test name
Test status
Simulation time 165198099948 ps
CPU time 136.25 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:47:59 PM PST 24
Peak memory 201116 kb
Host smart-3572ddad-54b0-4fe8-b92d-9cbeb67af42e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998824223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1998824223
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2843652185
Short name T305
Test name
Test status
Simulation time 161704294830 ps
CPU time 375.91 seconds
Started Mar 05 12:45:26 PM PST 24
Finished Mar 05 12:51:42 PM PST 24
Peak memory 201168 kb
Host smart-10e7dd43-9106-4aa7-8477-6e133e0477de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843652185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2843652185
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3069970369
Short name T634
Test name
Test status
Simulation time 491654374101 ps
CPU time 256.79 seconds
Started Mar 05 12:45:47 PM PST 24
Finished Mar 05 12:50:05 PM PST 24
Peak memory 201184 kb
Host smart-ac7c2213-49dd-4e91-8ac5-ae5c89ab7e03
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069970369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3069970369
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2038437748
Short name T138
Test name
Test status
Simulation time 335100822273 ps
CPU time 413.67 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:52:22 PM PST 24
Peak memory 201184 kb
Host smart-93388db4-fa00-498d-a49f-1ce79559b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038437748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2038437748
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4069143354
Short name T444
Test name
Test status
Simulation time 326761992431 ps
CPU time 58.47 seconds
Started Mar 05 12:45:38 PM PST 24
Finished Mar 05 12:46:37 PM PST 24
Peak memory 201068 kb
Host smart-1006a3fc-8d01-4ff0-a6ce-065714acb580
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069143354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4069143354
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2021001461
Short name T271
Test name
Test status
Simulation time 502552649161 ps
CPU time 1176.96 seconds
Started Mar 05 12:45:22 PM PST 24
Finished Mar 05 01:04:59 PM PST 24
Peak memory 201136 kb
Host smart-c89935b7-1ffb-4596-95e0-f84b65e0fd4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021001461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2021001461
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.240568220
Short name T624
Test name
Test status
Simulation time 331491631593 ps
CPU time 698.98 seconds
Started Mar 05 12:45:24 PM PST 24
Finished Mar 05 12:57:03 PM PST 24
Peak memory 201116 kb
Host smart-a022f37b-52d8-4f3f-9a24-c26f2bf7e65b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240568220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.240568220
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.158808035
Short name T334
Test name
Test status
Simulation time 90343455667 ps
CPU time 333.31 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:51:14 PM PST 24
Peak memory 201504 kb
Host smart-5ba9f0c8-4dc0-477e-ae96-17a2ed85bb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158808035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.158808035
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.923036231
Short name T711
Test name
Test status
Simulation time 42003853664 ps
CPU time 19.99 seconds
Started Mar 05 12:45:28 PM PST 24
Finished Mar 05 12:45:48 PM PST 24
Peak memory 201064 kb
Host smart-b68500f2-8409-49b0-bb5e-d1c7e27cfdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923036231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.923036231
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3908186750
Short name T54
Test name
Test status
Simulation time 4584287464 ps
CPU time 12.05 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:45:59 PM PST 24
Peak memory 200956 kb
Host smart-1627d38a-f292-4db6-89a2-adcfbe919563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908186750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3908186750
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1543634568
Short name T767
Test name
Test status
Simulation time 5884452774 ps
CPU time 7.29 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:45:47 PM PST 24
Peak memory 201052 kb
Host smart-1b55136f-b254-4a8b-9fb2-fe67b0fa8786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543634568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1543634568
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2091637202
Short name T721
Test name
Test status
Simulation time 382161706749 ps
CPU time 414.57 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:52:35 PM PST 24
Peak memory 201136 kb
Host smart-81e7671e-6d36-45ca-a42d-d44bf5741cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091637202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2091637202
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3238983434
Short name T62
Test name
Test status
Simulation time 43692513821 ps
CPU time 63.35 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:46:45 PM PST 24
Peak memory 201324 kb
Host smart-9bc95370-b422-42e0-a7ce-df8c1fa3a3b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238983434 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3238983434
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1040984141
Short name T382
Test name
Test status
Simulation time 361632168 ps
CPU time 1.15 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:45:41 PM PST 24
Peak memory 200920 kb
Host smart-ddb0b8ca-ad0a-4029-a386-317a774c45fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040984141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1040984141
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2849388177
Short name T65
Test name
Test status
Simulation time 330345088442 ps
CPU time 182.36 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:48:43 PM PST 24
Peak memory 201076 kb
Host smart-431b74d8-aaac-4777-a6b9-d44120d02652
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849388177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2849388177
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2069941147
Short name T212
Test name
Test status
Simulation time 167654069633 ps
CPU time 107.5 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:47:21 PM PST 24
Peak memory 201200 kb
Host smart-cb82f911-af45-4ae9-b99a-759f92c818c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069941147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2069941147
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3584286823
Short name T158
Test name
Test status
Simulation time 327428245005 ps
CPU time 782.72 seconds
Started Mar 05 12:45:34 PM PST 24
Finished Mar 05 12:58:37 PM PST 24
Peak memory 201140 kb
Host smart-14ed967d-4647-44f7-b428-1c5961e2aba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584286823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3584286823
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.819348234
Short name T538
Test name
Test status
Simulation time 337062089017 ps
CPU time 718.22 seconds
Started Mar 05 12:45:31 PM PST 24
Finished Mar 05 12:57:30 PM PST 24
Peak memory 201116 kb
Host smart-d96c947b-9a1c-4d25-8cd9-c9b01cedff7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=819348234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.819348234
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2677211989
Short name T313
Test name
Test status
Simulation time 163247970355 ps
CPU time 282.07 seconds
Started Mar 05 12:45:29 PM PST 24
Finished Mar 05 12:50:15 PM PST 24
Peak memory 201156 kb
Host smart-3e787b2e-9a2d-4002-8498-ba062fb1cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677211989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2677211989
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1593782316
Short name T553
Test name
Test status
Simulation time 494845819046 ps
CPU time 1145.91 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 01:04:42 PM PST 24
Peak memory 201124 kb
Host smart-779b4929-6273-4c53-926d-e74817841cf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593782316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1593782316
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.637078363
Short name T307
Test name
Test status
Simulation time 329429694625 ps
CPU time 200.59 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:48:59 PM PST 24
Peak memory 201036 kb
Host smart-395b4565-c794-4034-810e-58c15d159d93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637078363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.637078363
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1139452591
Short name T379
Test name
Test status
Simulation time 160822406028 ps
CPU time 375.95 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 12:51:51 PM PST 24
Peak memory 201128 kb
Host smart-690bbecd-2c64-4073-aa5e-f7e0578bc340
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139452591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1139452591
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.137364786
Short name T417
Test name
Test status
Simulation time 106200316472 ps
CPU time 364.49 seconds
Started Mar 05 12:45:45 PM PST 24
Finished Mar 05 12:51:50 PM PST 24
Peak memory 201480 kb
Host smart-46a49194-407f-4e23-9795-fe42851bae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137364786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.137364786
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2497206762
Short name T585
Test name
Test status
Simulation time 27484523671 ps
CPU time 35.81 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:46:09 PM PST 24
Peak memory 201044 kb
Host smart-b37a02ff-c92a-4ea5-aa1f-f70ca7f0c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497206762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2497206762
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2706275847
Short name T484
Test name
Test status
Simulation time 3816299169 ps
CPU time 10 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:45:57 PM PST 24
Peak memory 201060 kb
Host smart-0bb1ebe2-f13d-43b9-a51c-2a30e32a02c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706275847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2706275847
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1664388647
Short name T781
Test name
Test status
Simulation time 5640058423 ps
CPU time 13.39 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:45:53 PM PST 24
Peak memory 201032 kb
Host smart-d2f02793-0a15-4056-84da-49b617014fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664388647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1664388647
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2440874102
Short name T238
Test name
Test status
Simulation time 332094888492 ps
CPU time 563.51 seconds
Started Mar 05 12:45:50 PM PST 24
Finished Mar 05 12:55:14 PM PST 24
Peak memory 201140 kb
Host smart-e3325868-6f35-4741-a434-c579167083b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440874102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2440874102
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3057881666
Short name T194
Test name
Test status
Simulation time 25850487050 ps
CPU time 50.98 seconds
Started Mar 05 12:45:47 PM PST 24
Finished Mar 05 12:46:39 PM PST 24
Peak memory 209364 kb
Host smart-e64ea653-4a23-4f69-84d6-0161730261ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057881666 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3057881666
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1082990611
Short name T756
Test name
Test status
Simulation time 431998439 ps
CPU time 1.63 seconds
Started Mar 05 12:45:34 PM PST 24
Finished Mar 05 12:45:36 PM PST 24
Peak memory 200920 kb
Host smart-5f03ad62-3018-4f44-bf92-2b2ceb3a3606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082990611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1082990611
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.312704624
Short name T759
Test name
Test status
Simulation time 169024492408 ps
CPU time 390.06 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:52:10 PM PST 24
Peak memory 201148 kb
Host smart-7ceb33bd-ea93-42bb-86ba-6d3cf03b71fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312704624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.312704624
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.4268641256
Short name T794
Test name
Test status
Simulation time 161164531733 ps
CPU time 96.02 seconds
Started Mar 05 12:45:27 PM PST 24
Finished Mar 05 12:47:04 PM PST 24
Peak memory 201076 kb
Host smart-1c1c5f5b-5de8-48bf-aa10-e9e300b8ed6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268641256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.4268641256
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.494838194
Short name T354
Test name
Test status
Simulation time 479643258916 ps
CPU time 610.49 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:55:53 PM PST 24
Peak memory 201092 kb
Host smart-ce44e627-0af8-48f2-880b-35f3a58ffb92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=494838194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.494838194
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3740633150
Short name T584
Test name
Test status
Simulation time 333686912714 ps
CPU time 819.36 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 12:59:24 PM PST 24
Peak memory 201148 kb
Host smart-b05055ca-a4bd-4e47-82b6-5a3e000c380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740633150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3740633150
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2095745380
Short name T569
Test name
Test status
Simulation time 325932006257 ps
CPU time 772.46 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:58:32 PM PST 24
Peak memory 201124 kb
Host smart-d0ed185c-de15-450f-b870-aee51a4660cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095745380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2095745380
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.665648367
Short name T55
Test name
Test status
Simulation time 499355331659 ps
CPU time 1176.55 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 01:05:17 PM PST 24
Peak memory 201208 kb
Host smart-cbe5d2b4-4ed9-4b4b-beaf-d7020e7d9818
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665648367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.665648367
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.250985724
Short name T764
Test name
Test status
Simulation time 123127834220 ps
CPU time 667.25 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 12:56:51 PM PST 24
Peak memory 201508 kb
Host smart-7c7347ab-acb3-40a1-8f03-acdb4c3165ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250985724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.250985724
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2371792438
Short name T389
Test name
Test status
Simulation time 41647061421 ps
CPU time 51.57 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:46:31 PM PST 24
Peak memory 201048 kb
Host smart-cf0cf502-bf67-4836-8982-f53f7eeea485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371792438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2371792438
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3233183765
Short name T600
Test name
Test status
Simulation time 3488223608 ps
CPU time 3.26 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:45:50 PM PST 24
Peak memory 201032 kb
Host smart-d2ee101b-1297-49ef-8f1b-2175e5e1c61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233183765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3233183765
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1997619095
Short name T508
Test name
Test status
Simulation time 5638384638 ps
CPU time 5.51 seconds
Started Mar 05 12:45:36 PM PST 24
Finished Mar 05 12:45:42 PM PST 24
Peak memory 201008 kb
Host smart-5a9dbcd7-e9be-4326-92a6-ed30cbe65b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997619095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1997619095
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.1162841526
Short name T223
Test name
Test status
Simulation time 166389291462 ps
CPU time 112.5 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:47:33 PM PST 24
Peak memory 201084 kb
Host smart-b35e6bed-cbfd-42ce-bed5-210220f8aafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162841526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.1162841526
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.469622125
Short name T518
Test name
Test status
Simulation time 188799079652 ps
CPU time 228.21 seconds
Started Mar 05 12:45:41 PM PST 24
Finished Mar 05 12:49:30 PM PST 24
Peak memory 209836 kb
Host smart-5696376e-783b-4647-9bb6-9b9960b29d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469622125 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.469622125
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2640965201
Short name T531
Test name
Test status
Simulation time 603744517 ps
CPU time 0.72 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:45:33 PM PST 24
Peak memory 200928 kb
Host smart-af8e26c8-8afb-4f35-af86-d3fd548ebe38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640965201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2640965201
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3378163511
Short name T502
Test name
Test status
Simulation time 330204680459 ps
CPU time 838.13 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:59:41 PM PST 24
Peak memory 201116 kb
Host smart-b3ff3dcb-5f00-460c-889f-2907e9da040f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378163511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3378163511
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1098302176
Short name T288
Test name
Test status
Simulation time 164400294122 ps
CPU time 182.46 seconds
Started Mar 05 12:45:43 PM PST 24
Finished Mar 05 12:48:46 PM PST 24
Peak memory 201204 kb
Host smart-8f78ec3a-9f1f-431d-b4b3-8751efa18ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098302176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1098302176
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.4052432347
Short name T404
Test name
Test status
Simulation time 323996648811 ps
CPU time 53.31 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:46:36 PM PST 24
Peak memory 201100 kb
Host smart-2a9cc41b-9f5e-4bef-af21-2bad0a580f28
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052432347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.4052432347
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2529316177
Short name T245
Test name
Test status
Simulation time 168675893055 ps
CPU time 373.26 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:51:53 PM PST 24
Peak memory 201196 kb
Host smart-85e431ed-ad4b-47a3-acb5-993024a5c41c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529316177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2529316177
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.2087644651
Short name T740
Test name
Test status
Simulation time 490660358931 ps
CPU time 293.79 seconds
Started Mar 05 12:45:39 PM PST 24
Finished Mar 05 12:50:34 PM PST 24
Peak memory 201252 kb
Host smart-db22cb8f-e84b-42b4-bb8b-f11a41c78f59
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087644651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.2087644651
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3968228006
Short name T622
Test name
Test status
Simulation time 116899511403 ps
CPU time 569.21 seconds
Started Mar 05 12:45:45 PM PST 24
Finished Mar 05 12:55:15 PM PST 24
Peak memory 201476 kb
Host smart-5df25d5f-d566-4c04-acdf-a59798c3bc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968228006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3968228006
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4257345631
Short name T610
Test name
Test status
Simulation time 39038287374 ps
CPU time 13.42 seconds
Started Mar 05 12:45:31 PM PST 24
Finished Mar 05 12:45:45 PM PST 24
Peak memory 201076 kb
Host smart-aae24496-b611-4854-a08f-b591518df22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257345631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4257345631
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1076573564
Short name T372
Test name
Test status
Simulation time 3170526902 ps
CPU time 2.45 seconds
Started Mar 05 12:45:54 PM PST 24
Finished Mar 05 12:45:57 PM PST 24
Peak memory 201064 kb
Host smart-1a5e1826-03ff-4f1e-b93d-3536834ac093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076573564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1076573564
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2269091844
Short name T557
Test name
Test status
Simulation time 5519761171 ps
CPU time 13.19 seconds
Started Mar 05 12:45:43 PM PST 24
Finished Mar 05 12:45:56 PM PST 24
Peak memory 201036 kb
Host smart-48a4a9d8-8230-4eac-8bfb-cb80382366de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269091844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2269091844
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2821503448
Short name T189
Test name
Test status
Simulation time 37442163020 ps
CPU time 82.25 seconds
Started Mar 05 12:45:33 PM PST 24
Finished Mar 05 12:46:55 PM PST 24
Peak memory 209476 kb
Host smart-89569ab3-f0a0-4e42-a0a1-df1b527f2809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821503448 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2821503448
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2797544239
Short name T526
Test name
Test status
Simulation time 533734891 ps
CPU time 0.78 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:45:10 PM PST 24
Peak memory 200880 kb
Host smart-fb782717-7c3b-424e-a599-ffa7c2de71df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797544239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2797544239
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.4292860470
Short name T733
Test name
Test status
Simulation time 349267095689 ps
CPU time 392.44 seconds
Started Mar 05 12:44:56 PM PST 24
Finished Mar 05 12:51:28 PM PST 24
Peak memory 201196 kb
Host smart-f17b735c-b6ba-4b12-8761-4c1129704301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292860470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.4292860470
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2210982219
Short name T529
Test name
Test status
Simulation time 330257694176 ps
CPU time 398.93 seconds
Started Mar 05 12:44:58 PM PST 24
Finished Mar 05 12:51:42 PM PST 24
Peak memory 201196 kb
Host smart-d99765da-2f6f-4abf-9ec2-f52832ff6e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210982219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2210982219
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3486158933
Short name T366
Test name
Test status
Simulation time 333646289081 ps
CPU time 202.47 seconds
Started Mar 05 12:44:50 PM PST 24
Finished Mar 05 12:48:13 PM PST 24
Peak memory 201060 kb
Host smart-312c42bc-eae5-453f-9653-4ed869c53a93
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486158933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3486158933
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.129943861
Short name T479
Test name
Test status
Simulation time 164389331530 ps
CPU time 99.46 seconds
Started Mar 05 12:44:53 PM PST 24
Finished Mar 05 12:46:32 PM PST 24
Peak memory 201200 kb
Host smart-bac66977-3de5-4687-9047-dd55cd71122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129943861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.129943861
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3760442345
Short name T80
Test name
Test status
Simulation time 165683879933 ps
CPU time 375.15 seconds
Started Mar 05 12:44:50 PM PST 24
Finished Mar 05 12:51:05 PM PST 24
Peak memory 201120 kb
Host smart-c6ccad2f-2597-482d-bd30-1c4ddb975818
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760442345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3760442345
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1940553030
Short name T183
Test name
Test status
Simulation time 513536050052 ps
CPU time 255.63 seconds
Started Mar 05 12:45:07 PM PST 24
Finished Mar 05 12:49:23 PM PST 24
Peak memory 201140 kb
Host smart-93cb9106-1d04-4e3b-bd90-f54c0d819d2a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940553030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1940553030
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3339384095
Short name T605
Test name
Test status
Simulation time 492652247159 ps
CPU time 572.96 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 12:54:28 PM PST 24
Peak memory 201188 kb
Host smart-0b1eb91d-e9c1-4c7e-b437-5fcfa496485f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339384095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3339384095
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1427217842
Short name T788
Test name
Test status
Simulation time 40427263135 ps
CPU time 46.46 seconds
Started Mar 05 12:45:17 PM PST 24
Finished Mar 05 12:46:03 PM PST 24
Peak memory 201044 kb
Host smart-fed56a9a-9cea-44a2-a2ef-d8417f595be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427217842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1427217842
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3004263295
Short name T593
Test name
Test status
Simulation time 4309061088 ps
CPU time 3.14 seconds
Started Mar 05 12:44:54 PM PST 24
Finished Mar 05 12:44:58 PM PST 24
Peak memory 201060 kb
Host smart-ea3cf90d-e7e1-42e9-b4f7-8b334b588a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004263295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3004263295
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1665877206
Short name T45
Test name
Test status
Simulation time 8199830319 ps
CPU time 5.41 seconds
Started Mar 05 12:44:41 PM PST 24
Finished Mar 05 12:44:46 PM PST 24
Peak memory 217584 kb
Host smart-139546fa-8fcd-46d9-91f3-cafc25b6ce76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665877206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1665877206
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.409171499
Short name T358
Test name
Test status
Simulation time 5692841101 ps
CPU time 7.34 seconds
Started Mar 05 12:44:50 PM PST 24
Finished Mar 05 12:44:57 PM PST 24
Peak memory 201052 kb
Host smart-7fd0af0a-bd83-49f9-805b-9cc9121172de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409171499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.409171499
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3521811971
Short name T108
Test name
Test status
Simulation time 178193125047 ps
CPU time 430.99 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:52:13 PM PST 24
Peak memory 201196 kb
Host smart-c180743e-7916-4025-a5c4-e19af348f2dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521811971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3521811971
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2612922303
Short name T188
Test name
Test status
Simulation time 56005329307 ps
CPU time 141.02 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 12:47:27 PM PST 24
Peak memory 209776 kb
Host smart-ec7b5084-ea72-45fb-a322-974c8c7b84fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612922303 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2612922303
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.764519401
Short name T762
Test name
Test status
Simulation time 497951029 ps
CPU time 1.03 seconds
Started Mar 05 12:45:45 PM PST 24
Finished Mar 05 12:45:47 PM PST 24
Peak memory 200980 kb
Host smart-78ab0ed2-0fcc-47ca-a63e-0f55259b206c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764519401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.764519401
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3876718355
Short name T281
Test name
Test status
Simulation time 162485966305 ps
CPU time 186.94 seconds
Started Mar 05 12:45:45 PM PST 24
Finished Mar 05 12:48:53 PM PST 24
Peak memory 201124 kb
Host smart-41c9048e-a568-4cf9-9fda-76a365311321
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876718355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3876718355
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2551903244
Short name T718
Test name
Test status
Simulation time 497448130031 ps
CPU time 1066.24 seconds
Started Mar 05 12:45:37 PM PST 24
Finished Mar 05 01:03:24 PM PST 24
Peak memory 201080 kb
Host smart-bf9e5af4-6ac1-4bc9-93c4-b29fbd7e5f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551903244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2551903244
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.4208116930
Short name T58
Test name
Test status
Simulation time 501262703637 ps
CPU time 279.18 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 12:50:23 PM PST 24
Peak memory 201092 kb
Host smart-90adaf33-0808-4a75-b64e-550310d50661
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208116930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.4208116930
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.110424287
Short name T118
Test name
Test status
Simulation time 165454565802 ps
CPU time 342.05 seconds
Started Mar 05 12:45:51 PM PST 24
Finished Mar 05 12:51:34 PM PST 24
Peak memory 201144 kb
Host smart-aa885d54-f843-4362-a509-bb8310777ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110424287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.110424287
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2357845018
Short name T435
Test name
Test status
Simulation time 165583341063 ps
CPU time 77.09 seconds
Started Mar 05 12:45:43 PM PST 24
Finished Mar 05 12:47:00 PM PST 24
Peak memory 201184 kb
Host smart-1f83b34d-1bd2-43ba-b5f4-64cd11443599
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357845018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2357845018
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2503181949
Short name T395
Test name
Test status
Simulation time 327539412124 ps
CPU time 208.14 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:49:15 PM PST 24
Peak memory 201164 kb
Host smart-97d298f7-40ef-421d-8139-1d652c56f05b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503181949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2503181949
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1284328645
Short name T345
Test name
Test status
Simulation time 135697427875 ps
CPU time 636.26 seconds
Started Mar 05 12:45:41 PM PST 24
Finished Mar 05 12:56:18 PM PST 24
Peak memory 201572 kb
Host smart-52660bb0-c70b-48d2-b0df-7ba2fe90f6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284328645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1284328645
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2366453280
Short name T530
Test name
Test status
Simulation time 40827173385 ps
CPU time 5.83 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:45:53 PM PST 24
Peak memory 201168 kb
Host smart-6eb645b8-ac47-4461-ac1d-acbeb624bc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366453280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2366453280
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.2211550212
Short name T436
Test name
Test status
Simulation time 3844575023 ps
CPU time 2.3 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:45:44 PM PST 24
Peak memory 200972 kb
Host smart-14d2405c-8e9b-4a64-a1ef-d27b974017ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211550212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.2211550212
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2693321655
Short name T401
Test name
Test status
Simulation time 6038997172 ps
CPU time 4.25 seconds
Started Mar 05 12:45:45 PM PST 24
Finished Mar 05 12:45:50 PM PST 24
Peak memory 200976 kb
Host smart-338c8b51-320e-414b-ab17-d9221a0dbe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693321655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2693321655
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3993579434
Short name T778
Test name
Test status
Simulation time 527148364 ps
CPU time 1.19 seconds
Started Mar 05 12:45:52 PM PST 24
Finished Mar 05 12:45:54 PM PST 24
Peak memory 200912 kb
Host smart-598ced3b-6eab-4c82-a401-88a8afb33259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993579434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3993579434
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3851016008
Short name T172
Test name
Test status
Simulation time 492315706895 ps
CPU time 1112.84 seconds
Started Mar 05 12:45:47 PM PST 24
Finished Mar 05 01:04:21 PM PST 24
Peak memory 201184 kb
Host smart-38d5fc42-2df2-47e4-9583-6f7298dbfd91
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851016008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3851016008
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.2082038400
Short name T243
Test name
Test status
Simulation time 332147960093 ps
CPU time 759.68 seconds
Started Mar 05 12:45:41 PM PST 24
Finished Mar 05 12:58:21 PM PST 24
Peak memory 201204 kb
Host smart-3e619abf-144c-4498-9995-2dbcdd9feae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082038400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.2082038400
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3246824940
Short name T735
Test name
Test status
Simulation time 170135831936 ps
CPU time 109.75 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 12:47:34 PM PST 24
Peak memory 201108 kb
Host smart-fe9d44b1-6be0-41bd-8a9b-d25b10eba448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246824940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3246824940
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1831841211
Short name T11
Test name
Test status
Simulation time 159724803431 ps
CPU time 366.18 seconds
Started Mar 05 12:45:38 PM PST 24
Finished Mar 05 12:51:45 PM PST 24
Peak memory 201168 kb
Host smart-7e70b7ab-440e-4200-9fd6-e2a3e418217b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831841211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1831841211
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1075643703
Short name T578
Test name
Test status
Simulation time 169357569419 ps
CPU time 164.38 seconds
Started Mar 05 12:45:43 PM PST 24
Finished Mar 05 12:48:28 PM PST 24
Peak memory 201144 kb
Host smart-e469a110-0189-4d09-928a-0dc9ef358578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075643703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1075643703
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2673067424
Short name T760
Test name
Test status
Simulation time 489110266974 ps
CPU time 555.21 seconds
Started Mar 05 12:45:47 PM PST 24
Finished Mar 05 12:55:03 PM PST 24
Peak memory 201068 kb
Host smart-53e21f76-1131-4207-bcb8-656d73a4543d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673067424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2673067424
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3625149215
Short name T258
Test name
Test status
Simulation time 173097180126 ps
CPU time 429.62 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:52:57 PM PST 24
Peak memory 201012 kb
Host smart-f4b8c452-6b69-48f6-9d35-a41c5e52ac0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625149215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3625149215
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1021754006
Short name T405
Test name
Test status
Simulation time 168146183375 ps
CPU time 358.38 seconds
Started Mar 05 12:45:37 PM PST 24
Finished Mar 05 12:51:35 PM PST 24
Peak memory 201128 kb
Host smart-fdc6148a-c61a-438e-bcd0-a72e0663d255
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021754006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1021754006
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1136273738
Short name T771
Test name
Test status
Simulation time 146631561523 ps
CPU time 577.23 seconds
Started Mar 05 12:45:49 PM PST 24
Finished Mar 05 12:55:26 PM PST 24
Peak memory 201444 kb
Host smart-9787db8f-2b95-4153-8913-ab164059b385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136273738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1136273738
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3244081988
Short name T676
Test name
Test status
Simulation time 43779022181 ps
CPU time 28.27 seconds
Started Mar 05 12:45:50 PM PST 24
Finished Mar 05 12:46:19 PM PST 24
Peak memory 200944 kb
Host smart-80f983ae-33c2-47ea-af18-fe462e50fe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244081988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3244081988
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3463443344
Short name T523
Test name
Test status
Simulation time 3407796721 ps
CPU time 7.9 seconds
Started Mar 05 12:45:48 PM PST 24
Finished Mar 05 12:45:56 PM PST 24
Peak memory 201064 kb
Host smart-47af4a52-e24a-4d75-88f7-2dd61c0f529d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463443344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3463443344
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1090156231
Short name T486
Test name
Test status
Simulation time 5703541029 ps
CPU time 13.86 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 12:45:58 PM PST 24
Peak memory 200972 kb
Host smart-6a956085-f325-4092-92f1-ec7b4d8a3d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090156231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1090156231
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2738671534
Short name T607
Test name
Test status
Simulation time 49789246179 ps
CPU time 94.48 seconds
Started Mar 05 12:45:43 PM PST 24
Finished Mar 05 12:47:17 PM PST 24
Peak memory 209464 kb
Host smart-11030cf7-4231-4f19-a4d8-10d57b90d4d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738671534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2738671534
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1508996433
Short name T356
Test name
Test status
Simulation time 509500710 ps
CPU time 0.91 seconds
Started Mar 05 12:45:48 PM PST 24
Finished Mar 05 12:45:49 PM PST 24
Peak memory 200924 kb
Host smart-9d0bf2bf-81b7-493d-b457-5aa2d1758a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508996433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1508996433
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3519574425
Short name T765
Test name
Test status
Simulation time 167589688697 ps
CPU time 382.15 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:52:09 PM PST 24
Peak memory 201000 kb
Host smart-957a1b28-5a98-4801-b814-75c16527b436
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519574425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3519574425
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.651193520
Short name T647
Test name
Test status
Simulation time 496466110640 ps
CPU time 593.83 seconds
Started Mar 05 12:45:41 PM PST 24
Finished Mar 05 12:55:35 PM PST 24
Peak memory 201200 kb
Host smart-44a7cb97-0fbb-49bf-a165-7381394ae1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651193520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.651193520
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2860386043
Short name T768
Test name
Test status
Simulation time 494940583106 ps
CPU time 187.66 seconds
Started Mar 05 12:45:49 PM PST 24
Finished Mar 05 12:48:56 PM PST 24
Peak memory 201140 kb
Host smart-a09790b7-24a5-4b1c-bafd-f4a904a3af2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860386043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2860386043
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3057383042
Short name T157
Test name
Test status
Simulation time 501045264303 ps
CPU time 277.65 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:50:24 PM PST 24
Peak memory 201120 kb
Host smart-315d5488-33a7-4b9b-93c3-353036d8f608
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057383042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3057383042
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.744314934
Short name T581
Test name
Test status
Simulation time 164919252285 ps
CPU time 25.15 seconds
Started Mar 05 12:45:40 PM PST 24
Finished Mar 05 12:46:06 PM PST 24
Peak memory 201080 kb
Host smart-ec5347c1-f4c4-472c-b026-a0bc9d75fa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744314934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.744314934
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.118506763
Short name T783
Test name
Test status
Simulation time 494805250346 ps
CPU time 310.88 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:50:58 PM PST 24
Peak memory 201120 kb
Host smart-c7b6a3c5-2bb1-4c37-a7be-05d61c552ca7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=118506763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.118506763
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.3028611811
Short name T747
Test name
Test status
Simulation time 165870578630 ps
CPU time 367.73 seconds
Started Mar 05 12:45:49 PM PST 24
Finished Mar 05 12:51:57 PM PST 24
Peak memory 201104 kb
Host smart-ee05ba62-60af-49b0-aeef-bbc78429a70c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028611811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.3028611811
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2059999672
Short name T606
Test name
Test status
Simulation time 86007203231 ps
CPU time 292.97 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:50:35 PM PST 24
Peak memory 201388 kb
Host smart-c6406cad-282e-4497-b173-6f2205165118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059999672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2059999672
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.3460322739
Short name T761
Test name
Test status
Simulation time 23650488535 ps
CPU time 13.99 seconds
Started Mar 05 12:45:50 PM PST 24
Finished Mar 05 12:46:05 PM PST 24
Peak memory 201080 kb
Host smart-9eb1be91-58ad-44c4-96d5-097b299754f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460322739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.3460322739
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.117130628
Short name T658
Test name
Test status
Simulation time 3089574899 ps
CPU time 4.68 seconds
Started Mar 05 12:45:47 PM PST 24
Finished Mar 05 12:45:52 PM PST 24
Peak memory 201064 kb
Host smart-0f85528f-4d78-43fc-8a82-864d871025ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117130628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.117130628
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.176196001
Short name T745
Test name
Test status
Simulation time 5583180077 ps
CPU time 14.44 seconds
Started Mar 05 12:45:52 PM PST 24
Finished Mar 05 12:46:07 PM PST 24
Peak memory 201056 kb
Host smart-36ace93c-22f9-4eb8-868f-2d771b26e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176196001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.176196001
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1681389057
Short name T555
Test name
Test status
Simulation time 25027932824 ps
CPU time 28.73 seconds
Started Mar 05 12:45:51 PM PST 24
Finished Mar 05 12:46:20 PM PST 24
Peak memory 201320 kb
Host smart-98115d85-4b8d-42a7-80e7-f6792d233618
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681389057 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1681389057
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2184532589
Short name T385
Test name
Test status
Simulation time 505950936 ps
CPU time 1.71 seconds
Started Mar 05 12:45:50 PM PST 24
Finished Mar 05 12:45:51 PM PST 24
Peak memory 200928 kb
Host smart-e21682f7-c0bc-4bf8-8e27-86a2674693af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184532589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2184532589
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2376990364
Short name T237
Test name
Test status
Simulation time 327194052908 ps
CPU time 672.41 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:56:59 PM PST 24
Peak memory 201180 kb
Host smart-2434ba4f-6c4f-4bce-861b-3f21e9b6b929
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376990364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2376990364
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.658398818
Short name T303
Test name
Test status
Simulation time 170460407647 ps
CPU time 86.91 seconds
Started Mar 05 12:45:49 PM PST 24
Finished Mar 05 12:47:16 PM PST 24
Peak memory 201144 kb
Host smart-b291f3ef-c7e7-4c46-bd9c-ace60c3592ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658398818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.658398818
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3860944940
Short name T315
Test name
Test status
Simulation time 497867621711 ps
CPU time 290.01 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:50:37 PM PST 24
Peak memory 201084 kb
Host smart-ad3370e9-ac0e-497d-a396-93458cf804ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860944940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3860944940
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.1683731155
Short name T392
Test name
Test status
Simulation time 327685217723 ps
CPU time 192.43 seconds
Started Mar 05 12:45:51 PM PST 24
Finished Mar 05 12:49:04 PM PST 24
Peak memory 201064 kb
Host smart-8b5e5685-40a9-4d49-a0c5-b6b0247c6740
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683731155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.1683731155
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.475210251
Short name T201
Test name
Test status
Simulation time 162361052619 ps
CPU time 182.53 seconds
Started Mar 05 12:45:51 PM PST 24
Finished Mar 05 12:48:54 PM PST 24
Peak memory 201276 kb
Host smart-437d87f7-0e72-460b-a180-e8afd99b2dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475210251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.475210251
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2317308060
Short name T361
Test name
Test status
Simulation time 335964410373 ps
CPU time 796.97 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:59:00 PM PST 24
Peak memory 201184 kb
Host smart-03395c57-e96c-46f4-b058-450c9baa8160
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317308060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2317308060
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.103542962
Short name T580
Test name
Test status
Simulation time 165510770196 ps
CPU time 399.81 seconds
Started Mar 05 12:45:43 PM PST 24
Finished Mar 05 12:52:23 PM PST 24
Peak memory 201224 kb
Host smart-800cb8bd-46b8-4cba-83ed-20d32b514152
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103542962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.103542962
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3404050424
Short name T360
Test name
Test status
Simulation time 166139044453 ps
CPU time 380.12 seconds
Started Mar 05 12:45:41 PM PST 24
Finished Mar 05 12:52:02 PM PST 24
Peak memory 201124 kb
Host smart-54b1323d-58d1-42b8-8414-16629b59db7b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404050424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3404050424
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3736679012
Short name T617
Test name
Test status
Simulation time 91134462257 ps
CPU time 297.6 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 12:50:43 PM PST 24
Peak memory 201560 kb
Host smart-506a1671-9b9a-42cf-bd8d-92e270fdab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736679012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3736679012
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3579271838
Short name T572
Test name
Test status
Simulation time 33727613811 ps
CPU time 15.3 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 12:46:00 PM PST 24
Peak memory 201020 kb
Host smart-62165f09-4065-4295-9b0b-b00fefa32644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579271838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3579271838
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.590137367
Short name T549
Test name
Test status
Simulation time 4653615230 ps
CPU time 1.48 seconds
Started Mar 05 12:45:50 PM PST 24
Finished Mar 05 12:45:51 PM PST 24
Peak memory 201088 kb
Host smart-89bf64fa-42f3-4b3c-8e5e-1b1c52b8a130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590137367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.590137367
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.4000274127
Short name T652
Test name
Test status
Simulation time 5996257000 ps
CPU time 1.91 seconds
Started Mar 05 12:45:45 PM PST 24
Finished Mar 05 12:45:47 PM PST 24
Peak memory 201008 kb
Host smart-73f1f88a-92ce-46d5-9918-52089d323505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000274127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.4000274127
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1788998514
Short name T748
Test name
Test status
Simulation time 61950015402 ps
CPU time 37.15 seconds
Started Mar 05 12:45:35 PM PST 24
Finished Mar 05 12:46:13 PM PST 24
Peak memory 200996 kb
Host smart-cf34e106-c514-4a08-b2ef-5d9a2b6aab25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788998514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1788998514
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2177143118
Short name T264
Test name
Test status
Simulation time 296216767065 ps
CPU time 462.18 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 12:53:27 PM PST 24
Peak memory 209888 kb
Host smart-939e2af4-c937-4340-9df0-4fe12db5ac7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177143118 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2177143118
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1939273982
Short name T400
Test name
Test status
Simulation time 344721206 ps
CPU time 1.3 seconds
Started Mar 05 12:45:51 PM PST 24
Finished Mar 05 12:45:52 PM PST 24
Peak memory 200892 kb
Host smart-90722631-d9ea-4cc1-9a2c-7fa7b6ce952a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939273982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1939273982
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2569076527
Short name T731
Test name
Test status
Simulation time 165303732856 ps
CPU time 78.62 seconds
Started Mar 05 12:45:52 PM PST 24
Finished Mar 05 12:47:11 PM PST 24
Peak memory 201196 kb
Host smart-91a09c93-5826-41e8-ae54-1417c2cb69fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569076527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2569076527
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1522064025
Short name T674
Test name
Test status
Simulation time 160625849481 ps
CPU time 396.96 seconds
Started Mar 05 12:45:47 PM PST 24
Finished Mar 05 12:52:25 PM PST 24
Peak memory 201064 kb
Host smart-20bb0b1e-230f-4ffa-b67d-3c51db865533
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522064025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1522064025
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4096512585
Short name T537
Test name
Test status
Simulation time 335046226833 ps
CPU time 776.92 seconds
Started Mar 05 12:45:53 PM PST 24
Finished Mar 05 12:58:50 PM PST 24
Peak memory 201156 kb
Host smart-9e08b2aa-3c9c-45e6-b520-d225f50a9161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096512585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4096512585
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2401232269
Short name T57
Test name
Test status
Simulation time 325798662442 ps
CPU time 738.34 seconds
Started Mar 05 12:45:43 PM PST 24
Finished Mar 05 12:58:01 PM PST 24
Peak memory 201056 kb
Host smart-38c20468-2a1d-41d9-a1a6-89ab31d9d03e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401232269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2401232269
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1266281624
Short name T516
Test name
Test status
Simulation time 354700618393 ps
CPU time 887.33 seconds
Started Mar 05 12:45:53 PM PST 24
Finished Mar 05 01:00:40 PM PST 24
Peak memory 201136 kb
Host smart-e9d46dc3-51c6-4a80-9238-abdea3b291fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266281624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1266281624
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1726490597
Short name T418
Test name
Test status
Simulation time 323302438390 ps
CPU time 165.4 seconds
Started Mar 05 12:45:54 PM PST 24
Finished Mar 05 12:48:39 PM PST 24
Peak memory 201096 kb
Host smart-2f6cf84a-f31d-49fa-b127-e57cd48f3177
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726490597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1726490597
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.616008901
Short name T163
Test name
Test status
Simulation time 103482090628 ps
CPU time 359.76 seconds
Started Mar 05 12:45:53 PM PST 24
Finished Mar 05 12:51:53 PM PST 24
Peak memory 201600 kb
Host smart-a5c56622-57d3-491e-a57e-5c76bc2f4c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616008901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.616008901
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2734699752
Short name T480
Test name
Test status
Simulation time 30503302202 ps
CPU time 19.47 seconds
Started Mar 05 12:45:58 PM PST 24
Finished Mar 05 12:46:17 PM PST 24
Peak memory 201044 kb
Host smart-128fc0d5-82c4-4b35-b3ef-c8ec54a2790d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734699752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2734699752
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.203797636
Short name T411
Test name
Test status
Simulation time 4112167844 ps
CPU time 10.61 seconds
Started Mar 05 12:45:52 PM PST 24
Finished Mar 05 12:46:03 PM PST 24
Peak memory 201056 kb
Host smart-16eb9d11-4f86-43c1-ac57-5670c95c80a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203797636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.203797636
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2650576403
Short name T568
Test name
Test status
Simulation time 6173945369 ps
CPU time 4.57 seconds
Started Mar 05 12:45:42 PM PST 24
Finished Mar 05 12:45:47 PM PST 24
Peak memory 200952 kb
Host smart-0402b9c0-c633-4558-a6a3-c233053623ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650576403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2650576403
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1744469000
Short name T193
Test name
Test status
Simulation time 371440664145 ps
CPU time 248.18 seconds
Started Mar 05 12:45:53 PM PST 24
Finished Mar 05 12:50:02 PM PST 24
Peak memory 209732 kb
Host smart-523e7123-fb7e-49c5-9fe1-004640478bf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744469000 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1744469000
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2549221589
Short name T528
Test name
Test status
Simulation time 453510104 ps
CPU time 0.69 seconds
Started Mar 05 12:45:59 PM PST 24
Finished Mar 05 12:45:59 PM PST 24
Peak memory 200932 kb
Host smart-01b24600-0de7-4a83-a08c-e2c0212e9e98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549221589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2549221589
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.118363354
Short name T217
Test name
Test status
Simulation time 169506456363 ps
CPU time 382.95 seconds
Started Mar 05 12:45:52 PM PST 24
Finished Mar 05 12:52:15 PM PST 24
Peak memory 201256 kb
Host smart-11909ff1-124b-4f5c-9b0c-63a2ef6cb019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118363354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.118363354
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2288897866
Short name T515
Test name
Test status
Simulation time 322449429416 ps
CPU time 768.54 seconds
Started Mar 05 12:45:53 PM PST 24
Finished Mar 05 12:58:42 PM PST 24
Peak memory 201116 kb
Host smart-f4b5fbb7-953e-4c93-85ca-5eaaa7555192
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288897866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2288897866
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1773724137
Short name T200
Test name
Test status
Simulation time 334508603313 ps
CPU time 368.81 seconds
Started Mar 05 12:45:51 PM PST 24
Finished Mar 05 12:52:00 PM PST 24
Peak memory 201144 kb
Host smart-2c8644ee-d8e6-4c9b-a13d-0247cdd691d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773724137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1773724137
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.3283883286
Short name T412
Test name
Test status
Simulation time 166773504363 ps
CPU time 106.56 seconds
Started Mar 05 12:45:54 PM PST 24
Finished Mar 05 12:47:40 PM PST 24
Peak memory 201020 kb
Host smart-c072b169-ee0a-42ec-b7bc-024bae6ae2f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283883286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.3283883286
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.448059947
Short name T233
Test name
Test status
Simulation time 502190100477 ps
CPU time 1161.96 seconds
Started Mar 05 12:45:44 PM PST 24
Finished Mar 05 01:05:08 PM PST 24
Peak memory 201164 kb
Host smart-fe6c623b-8b04-4782-8d3b-68a922255f62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448059947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.448059947
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3486271499
Short name T554
Test name
Test status
Simulation time 327165553010 ps
CPU time 812.02 seconds
Started Mar 05 12:45:46 PM PST 24
Finished Mar 05 12:59:19 PM PST 24
Peak memory 201228 kb
Host smart-ceb3a7ff-7dc9-442e-ab7b-ef984af1b31d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486271499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3486271499
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3768834847
Short name T644
Test name
Test status
Simulation time 104526306581 ps
CPU time 375.01 seconds
Started Mar 05 12:46:00 PM PST 24
Finished Mar 05 12:52:16 PM PST 24
Peak memory 201516 kb
Host smart-4d217ce4-09fd-43bd-a944-c779e42926a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768834847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3768834847
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3144737469
Short name T378
Test name
Test status
Simulation time 26413255471 ps
CPU time 56.4 seconds
Started Mar 05 12:45:54 PM PST 24
Finished Mar 05 12:46:51 PM PST 24
Peak memory 201024 kb
Host smart-79aec6f0-b45b-4617-a970-92c698b1b11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144737469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3144737469
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1500766829
Short name T566
Test name
Test status
Simulation time 3339387764 ps
CPU time 7.78 seconds
Started Mar 05 12:45:50 PM PST 24
Finished Mar 05 12:45:59 PM PST 24
Peak memory 201064 kb
Host smart-f667041e-1d65-4af9-a5ca-8b5e3fcc5834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500766829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1500766829
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.4250509900
Short name T737
Test name
Test status
Simulation time 5628492819 ps
CPU time 7.23 seconds
Started Mar 05 12:45:54 PM PST 24
Finished Mar 05 12:46:02 PM PST 24
Peak memory 201060 kb
Host smart-77494d8a-645d-4297-9764-5ce7cf3f0a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250509900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.4250509900
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2825223867
Short name T574
Test name
Test status
Simulation time 250198601464 ps
CPU time 755.82 seconds
Started Mar 05 12:45:57 PM PST 24
Finished Mar 05 12:58:33 PM PST 24
Peak memory 209752 kb
Host smart-ab1b944a-9f4c-460d-92b2-329b7423f542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825223867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2825223867
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2556275032
Short name T191
Test name
Test status
Simulation time 67054471503 ps
CPU time 137.97 seconds
Started Mar 05 12:45:57 PM PST 24
Finished Mar 05 12:48:15 PM PST 24
Peak memory 209384 kb
Host smart-56610e2b-4391-4ca2-b6a3-e3a0b9cc08bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556275032 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2556275032
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.90765489
Short name T558
Test name
Test status
Simulation time 506146747 ps
CPU time 0.95 seconds
Started Mar 05 12:45:56 PM PST 24
Finished Mar 05 12:45:58 PM PST 24
Peak memory 200924 kb
Host smart-184b88e7-5ab9-4455-a5d2-cc3057816e86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90765489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.90765489
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3546587783
Short name T449
Test name
Test status
Simulation time 162886547726 ps
CPU time 8.3 seconds
Started Mar 05 12:46:00 PM PST 24
Finished Mar 05 12:46:10 PM PST 24
Peak memory 201020 kb
Host smart-6e832ee8-b921-47e5-bca8-9b38f772ea07
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546587783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3546587783
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4161556527
Short name T156
Test name
Test status
Simulation time 492027666042 ps
CPU time 574.34 seconds
Started Mar 05 12:45:55 PM PST 24
Finished Mar 05 12:55:29 PM PST 24
Peak memory 201140 kb
Host smart-170b4cd2-14de-463b-b31e-f58b73b2563f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161556527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4161556527
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2719725937
Short name T662
Test name
Test status
Simulation time 486968110916 ps
CPU time 1006.85 seconds
Started Mar 05 12:45:57 PM PST 24
Finished Mar 05 01:02:44 PM PST 24
Peak memory 200980 kb
Host smart-b12b9459-6944-49be-ab8c-c14eb494ec44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719725937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2719725937
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1626460824
Short name T597
Test name
Test status
Simulation time 165674679753 ps
CPU time 74.38 seconds
Started Mar 05 12:46:00 PM PST 24
Finished Mar 05 12:47:16 PM PST 24
Peak memory 201136 kb
Host smart-6e26cb57-2b0b-4439-9a6e-f56d03af61ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626460824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1626460824
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1110240116
Short name T712
Test name
Test status
Simulation time 165511623880 ps
CPU time 180.57 seconds
Started Mar 05 12:46:03 PM PST 24
Finished Mar 05 12:49:05 PM PST 24
Peak memory 201200 kb
Host smart-a9ee6841-6211-454d-a196-8e4fd18ff172
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110240116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1110240116
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1640143312
Short name T179
Test name
Test status
Simulation time 481645390048 ps
CPU time 692.07 seconds
Started Mar 05 12:46:01 PM PST 24
Finished Mar 05 12:57:34 PM PST 24
Peak memory 201136 kb
Host smart-df4ddfc3-065e-41dc-9758-e14429c87fef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640143312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1640143312
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1916824119
Short name T769
Test name
Test status
Simulation time 329604620698 ps
CPU time 751.45 seconds
Started Mar 05 12:45:59 PM PST 24
Finished Mar 05 12:58:31 PM PST 24
Peak memory 201096 kb
Host smart-8b8405db-44fe-4f67-b4c9-f58b3a4cc331
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916824119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1916824119
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1365204152
Short name T736
Test name
Test status
Simulation time 75497927053 ps
CPU time 420.37 seconds
Started Mar 05 12:46:00 PM PST 24
Finished Mar 05 12:53:02 PM PST 24
Peak memory 201472 kb
Host smart-f328dfb6-c1ed-424a-a909-28abb9613764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365204152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1365204152
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1345865521
Short name T686
Test name
Test status
Simulation time 43936771715 ps
CPU time 94.8 seconds
Started Mar 05 12:45:56 PM PST 24
Finished Mar 05 12:47:31 PM PST 24
Peak memory 201048 kb
Host smart-3d4b9e29-d627-4534-9935-3c3b854a91d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345865521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1345865521
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3564686166
Short name T353
Test name
Test status
Simulation time 4189831547 ps
CPU time 10.5 seconds
Started Mar 05 12:46:00 PM PST 24
Finished Mar 05 12:46:11 PM PST 24
Peak memory 201036 kb
Host smart-f3c7843d-7027-4911-89e4-f056071bbd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564686166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3564686166
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2135524229
Short name T730
Test name
Test status
Simulation time 6151727075 ps
CPU time 15.23 seconds
Started Mar 05 12:45:57 PM PST 24
Finished Mar 05 12:46:13 PM PST 24
Peak memory 200980 kb
Host smart-5b418bde-49f0-4f79-94a2-33238b861bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135524229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2135524229
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1894470445
Short name T274
Test name
Test status
Simulation time 497421849936 ps
CPU time 513.84 seconds
Started Mar 05 12:45:59 PM PST 24
Finished Mar 05 12:54:33 PM PST 24
Peak memory 201016 kb
Host smart-9d019e02-4c10-4b8a-9426-3e84261af01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894470445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1894470445
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.929945941
Short name T22
Test name
Test status
Simulation time 21440945149 ps
CPU time 57.55 seconds
Started Mar 05 12:45:59 PM PST 24
Finished Mar 05 12:46:57 PM PST 24
Peak memory 209864 kb
Host smart-27a0b496-5b34-4f86-a4f4-cf4bebabdcc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929945941 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.929945941
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3051597248
Short name T421
Test name
Test status
Simulation time 413884086 ps
CPU time 0.8 seconds
Started Mar 05 12:46:06 PM PST 24
Finished Mar 05 12:46:07 PM PST 24
Peak memory 200816 kb
Host smart-70da31c1-fe7c-4a53-aa41-871f06b0aa60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051597248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3051597248
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3694629087
Short name T126
Test name
Test status
Simulation time 163414728297 ps
CPU time 171.85 seconds
Started Mar 05 12:46:00 PM PST 24
Finished Mar 05 12:48:53 PM PST 24
Peak memory 201184 kb
Host smart-d6c5d7de-dd4e-44e9-ab87-b108a7c64734
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694629087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3694629087
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.956502233
Short name T298
Test name
Test status
Simulation time 498202558991 ps
CPU time 332.63 seconds
Started Mar 05 12:45:55 PM PST 24
Finished Mar 05 12:51:28 PM PST 24
Peak memory 201196 kb
Host smart-fd9e10ed-faed-4373-8841-d746741513c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956502233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.956502233
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.428218808
Short name T160
Test name
Test status
Simulation time 325318651586 ps
CPU time 116.59 seconds
Started Mar 05 12:45:56 PM PST 24
Finished Mar 05 12:47:52 PM PST 24
Peak memory 201180 kb
Host smart-341e0a7c-6a82-44fc-b134-5c33e29bb1d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=428218808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrup
t_fixed.428218808
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.681652809
Short name T546
Test name
Test status
Simulation time 483613528152 ps
CPU time 1111.8 seconds
Started Mar 05 12:45:59 PM PST 24
Finished Mar 05 01:04:31 PM PST 24
Peak memory 200992 kb
Host smart-6af320ff-7954-41bb-84db-ecd1f9a285f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681652809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.681652809
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1372907855
Short name T373
Test name
Test status
Simulation time 332145169251 ps
CPU time 806.69 seconds
Started Mar 05 12:45:54 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 201120 kb
Host smart-1d3eef28-d578-4ba6-9028-20f29d9efb12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372907855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1372907855
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2380079828
Short name T434
Test name
Test status
Simulation time 325446142764 ps
CPU time 754.02 seconds
Started Mar 05 12:45:59 PM PST 24
Finished Mar 05 12:58:33 PM PST 24
Peak memory 201184 kb
Host smart-7ea20264-822c-4ac3-b4f1-c049d41f12d1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380079828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2380079828
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.28798330
Short name T452
Test name
Test status
Simulation time 74730882522 ps
CPU time 376.01 seconds
Started Mar 05 12:46:05 PM PST 24
Finished Mar 05 12:52:21 PM PST 24
Peak memory 201560 kb
Host smart-49e95e23-50a9-41dd-8ec2-b13365b6a248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28798330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.28798330
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3543108803
Short name T673
Test name
Test status
Simulation time 29218006380 ps
CPU time 15.76 seconds
Started Mar 05 12:45:59 PM PST 24
Finished Mar 05 12:46:15 PM PST 24
Peak memory 200864 kb
Host smart-27a01f63-6945-478c-8635-1d6a4ed03676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543108803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3543108803
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4182096581
Short name T738
Test name
Test status
Simulation time 3565147543 ps
CPU time 2.85 seconds
Started Mar 05 12:46:01 PM PST 24
Finished Mar 05 12:46:06 PM PST 24
Peak memory 201008 kb
Host smart-42386622-3348-4a3a-b7f2-db0539dd7406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182096581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4182096581
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2330046740
Short name T582
Test name
Test status
Simulation time 5538204799 ps
CPU time 9.1 seconds
Started Mar 05 12:46:00 PM PST 24
Finished Mar 05 12:46:10 PM PST 24
Peak memory 201004 kb
Host smart-9d3e210a-7882-4f3e-a29f-54bd66df0049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330046740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2330046740
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.346014023
Short name T235
Test name
Test status
Simulation time 496580097794 ps
CPU time 141.43 seconds
Started Mar 05 12:45:56 PM PST 24
Finished Mar 05 12:48:18 PM PST 24
Peak memory 201176 kb
Host smart-cc68d386-e143-4626-87de-9bd748970b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346014023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all.
346014023
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2989008629
Short name T633
Test name
Test status
Simulation time 96917410656 ps
CPU time 115.14 seconds
Started Mar 05 12:46:00 PM PST 24
Finished Mar 05 12:47:56 PM PST 24
Peak memory 217476 kb
Host smart-c9430ff6-a814-404b-83ef-6cb15d65e527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989008629 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2989008629
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1790208498
Short name T635
Test name
Test status
Simulation time 388092235 ps
CPU time 0.83 seconds
Started Mar 05 12:46:05 PM PST 24
Finished Mar 05 12:46:07 PM PST 24
Peak memory 200928 kb
Host smart-5d252308-f6fe-43f2-a348-d50a008df22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790208498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1790208498
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1343897954
Short name T180
Test name
Test status
Simulation time 506560317938 ps
CPU time 285.36 seconds
Started Mar 05 12:46:04 PM PST 24
Finished Mar 05 12:50:49 PM PST 24
Peak memory 201152 kb
Host smart-dc47f728-6f21-4142-827a-cd1d85ee2f8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343897954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1343897954
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.616691516
Short name T127
Test name
Test status
Simulation time 165869920503 ps
CPU time 48.37 seconds
Started Mar 05 12:46:04 PM PST 24
Finished Mar 05 12:46:53 PM PST 24
Peak memory 201204 kb
Host smart-bd7c8a70-837d-4493-acb6-4f99c876795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616691516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.616691516
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.3036701444
Short name T509
Test name
Test status
Simulation time 160931992732 ps
CPU time 375.27 seconds
Started Mar 05 12:46:05 PM PST 24
Finished Mar 05 12:52:20 PM PST 24
Peak memory 201164 kb
Host smart-3cccada2-8fab-4e05-a511-37d7d41f0b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036701444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.3036701444
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2334273442
Short name T365
Test name
Test status
Simulation time 165769102004 ps
CPU time 89.3 seconds
Started Mar 05 12:46:02 PM PST 24
Finished Mar 05 12:47:33 PM PST 24
Peak memory 201096 kb
Host smart-78195b58-c8ae-4890-b6b5-e61cfefcc7c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334273442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2334273442
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.523535912
Short name T133
Test name
Test status
Simulation time 488807750161 ps
CPU time 284.32 seconds
Started Mar 05 12:46:02 PM PST 24
Finished Mar 05 12:50:48 PM PST 24
Peak memory 201192 kb
Host smart-dc126782-1c12-498d-bf38-e41cf1b978b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523535912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.523535912
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.153777444
Short name T535
Test name
Test status
Simulation time 324742033885 ps
CPU time 802.51 seconds
Started Mar 05 12:46:07 PM PST 24
Finished Mar 05 12:59:30 PM PST 24
Peak memory 201120 kb
Host smart-46e4b375-79b6-46e7-b245-633c03228daf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=153777444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.153777444
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1615002295
Short name T490
Test name
Test status
Simulation time 165532873269 ps
CPU time 98.97 seconds
Started Mar 05 12:46:01 PM PST 24
Finished Mar 05 12:47:41 PM PST 24
Peak memory 201196 kb
Host smart-1fd6116a-0d5e-41a4-a611-cd9aad9f536f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615002295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1615002295
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2217545107
Short name T141
Test name
Test status
Simulation time 166396451708 ps
CPU time 379.56 seconds
Started Mar 05 12:46:01 PM PST 24
Finished Mar 05 12:52:22 PM PST 24
Peak memory 201188 kb
Host smart-7ab67a31-a180-4f59-91a3-ce55668a667c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217545107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2217545107
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1230903920
Short name T343
Test name
Test status
Simulation time 82156707077 ps
CPU time 422.99 seconds
Started Mar 05 12:46:03 PM PST 24
Finished Mar 05 12:53:07 PM PST 24
Peak memory 201652 kb
Host smart-9ba70f29-5255-4c61-934a-eadb23429ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230903920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1230903920
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3817800713
Short name T362
Test name
Test status
Simulation time 31801800240 ps
CPU time 63.12 seconds
Started Mar 05 12:46:07 PM PST 24
Finished Mar 05 12:47:11 PM PST 24
Peak memory 201044 kb
Host smart-9039e625-6cff-4077-bd84-73e9378883e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817800713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3817800713
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.2562619533
Short name T539
Test name
Test status
Simulation time 3349358641 ps
CPU time 8.32 seconds
Started Mar 05 12:46:01 PM PST 24
Finished Mar 05 12:46:10 PM PST 24
Peak memory 201008 kb
Host smart-f218e34b-cd5a-4ec1-927c-79274dd056de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562619533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.2562619533
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2428962233
Short name T438
Test name
Test status
Simulation time 5495777965 ps
CPU time 4.15 seconds
Started Mar 05 12:46:01 PM PST 24
Finished Mar 05 12:46:06 PM PST 24
Peak memory 201008 kb
Host smart-8962391d-aece-4aa9-a087-086be842ace1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428962233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2428962233
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.26028727
Short name T246
Test name
Test status
Simulation time 174436479232 ps
CPU time 103.04 seconds
Started Mar 05 12:46:05 PM PST 24
Finished Mar 05 12:47:48 PM PST 24
Peak memory 201176 kb
Host smart-42176cef-819e-4b1a-b1e1-f86db500afcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26028727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all.26028727
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2741341521
Short name T165
Test name
Test status
Simulation time 43089054693 ps
CPU time 111.44 seconds
Started Mar 05 12:46:07 PM PST 24
Finished Mar 05 12:47:59 PM PST 24
Peak memory 217088 kb
Host smart-a0fd6386-a89f-4e2f-bfa1-45051739050b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741341521 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2741341521
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3898395908
Short name T655
Test name
Test status
Simulation time 573663754 ps
CPU time 0.82 seconds
Started Mar 05 12:46:14 PM PST 24
Finished Mar 05 12:46:15 PM PST 24
Peak memory 200760 kb
Host smart-41ca0d1c-445a-454b-93d6-7b5108ecae08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898395908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3898395908
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3296589602
Short name T125
Test name
Test status
Simulation time 161269799882 ps
CPU time 89.91 seconds
Started Mar 05 12:46:07 PM PST 24
Finished Mar 05 12:47:37 PM PST 24
Peak memory 201180 kb
Host smart-09951217-4ad1-4ff9-97a9-53490be08029
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296589602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3296589602
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3342566175
Short name T205
Test name
Test status
Simulation time 159377061779 ps
CPU time 245.72 seconds
Started Mar 05 12:46:06 PM PST 24
Finished Mar 05 12:50:12 PM PST 24
Peak memory 201204 kb
Host smart-b1f8d92e-9c35-42a9-a0be-ac08ba8c5236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342566175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3342566175
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1537233720
Short name T551
Test name
Test status
Simulation time 323577865079 ps
CPU time 83.37 seconds
Started Mar 05 12:46:06 PM PST 24
Finished Mar 05 12:47:29 PM PST 24
Peak memory 201144 kb
Host smart-5b28bf1e-22fc-4b83-ad7c-88746e561e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537233720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1537233720
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2252819001
Short name T541
Test name
Test status
Simulation time 333866630928 ps
CPU time 428.24 seconds
Started Mar 05 12:46:05 PM PST 24
Finished Mar 05 12:53:13 PM PST 24
Peak memory 201184 kb
Host smart-24a3e2e5-c5f2-4e1d-a6f2-fc5bc31803c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252819001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2252819001
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.669764746
Short name T544
Test name
Test status
Simulation time 322069910797 ps
CPU time 750.93 seconds
Started Mar 05 12:46:01 PM PST 24
Finished Mar 05 12:58:34 PM PST 24
Peak memory 201120 kb
Host smart-7b00fac8-c77d-4c11-88b8-638c9c0fb9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669764746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.669764746
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3239668220
Short name T665
Test name
Test status
Simulation time 166975042558 ps
CPU time 84.05 seconds
Started Mar 05 12:46:07 PM PST 24
Finished Mar 05 12:47:31 PM PST 24
Peak memory 201184 kb
Host smart-ef23bcce-b57e-40a3-8380-bac2b7bc7981
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239668220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3239668220
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3773037990
Short name T616
Test name
Test status
Simulation time 167382398974 ps
CPU time 195.93 seconds
Started Mar 05 12:46:04 PM PST 24
Finished Mar 05 12:49:20 PM PST 24
Peak memory 201096 kb
Host smart-e766fe5d-091a-464c-8102-682bb0a2a457
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773037990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3773037990
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2088904352
Short name T540
Test name
Test status
Simulation time 160816516826 ps
CPU time 102.37 seconds
Started Mar 05 12:46:07 PM PST 24
Finished Mar 05 12:47:50 PM PST 24
Peak memory 201188 kb
Host smart-b8d89af5-ed22-4bef-9212-112a92556178
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088904352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2088904352
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.1920922571
Short name T598
Test name
Test status
Simulation time 89767481192 ps
CPU time 361.83 seconds
Started Mar 05 12:46:09 PM PST 24
Finished Mar 05 12:52:11 PM PST 24
Peak memory 201508 kb
Host smart-fcf73555-5aff-4533-99c6-c650b4a5ed91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920922571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.1920922571
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3132639923
Short name T720
Test name
Test status
Simulation time 46241817312 ps
CPU time 97.18 seconds
Started Mar 05 12:46:02 PM PST 24
Finished Mar 05 12:47:40 PM PST 24
Peak memory 201044 kb
Host smart-1b948b1f-e005-49d2-a4e3-a39263761673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132639923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3132639923
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3177460935
Short name T72
Test name
Test status
Simulation time 5235287204 ps
CPU time 5.41 seconds
Started Mar 05 12:46:09 PM PST 24
Finished Mar 05 12:46:15 PM PST 24
Peak memory 201056 kb
Host smart-5243ead4-e720-42d8-afe7-efc9424e26bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177460935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3177460935
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2816521146
Short name T524
Test name
Test status
Simulation time 5855822428 ps
CPU time 5.95 seconds
Started Mar 05 12:46:07 PM PST 24
Finished Mar 05 12:46:13 PM PST 24
Peak memory 200948 kb
Host smart-68bdba5f-127c-4e9d-8d60-cc37762bcf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816521146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2816521146
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.257133044
Short name T195
Test name
Test status
Simulation time 140842753878 ps
CPU time 110.06 seconds
Started Mar 05 12:46:18 PM PST 24
Finished Mar 05 12:48:08 PM PST 24
Peak memory 201696 kb
Host smart-6afdde2e-c7b2-4be2-830a-00c090e5646d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257133044 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.257133044
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2938830862
Short name T42
Test name
Test status
Simulation time 352401284 ps
CPU time 0.86 seconds
Started Mar 05 12:44:57 PM PST 24
Finished Mar 05 12:44:58 PM PST 24
Peak memory 200812 kb
Host smart-d18fa1ac-1b04-4ffe-96ae-5e4680f54b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938830862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2938830862
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2151003238
Short name T154
Test name
Test status
Simulation time 490216596945 ps
CPU time 305.67 seconds
Started Mar 05 12:45:24 PM PST 24
Finished Mar 05 12:50:30 PM PST 24
Peak memory 201128 kb
Host smart-7ea3323e-1d3f-451c-8e0c-75a31ba4b2a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151003238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2151003238
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3484645000
Short name T311
Test name
Test status
Simulation time 325856987051 ps
CPU time 351.14 seconds
Started Mar 05 12:45:07 PM PST 24
Finished Mar 05 12:50:58 PM PST 24
Peak memory 201196 kb
Host smart-86be0adc-97cb-499f-a3be-10bbcb0d2b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484645000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3484645000
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2415602273
Short name T689
Test name
Test status
Simulation time 490249133386 ps
CPU time 583.16 seconds
Started Mar 05 12:45:18 PM PST 24
Finished Mar 05 12:55:01 PM PST 24
Peak memory 201156 kb
Host smart-29dfccf5-303d-46fe-a349-2791d0ef690b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415602273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2415602273
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1502325826
Short name T763
Test name
Test status
Simulation time 163682224420 ps
CPU time 189.33 seconds
Started Mar 05 12:45:03 PM PST 24
Finished Mar 05 12:48:13 PM PST 24
Peak memory 201176 kb
Host smart-23286d13-75b4-4c4e-9e83-0c5f8a2d9426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502325826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1502325826
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2314972623
Short name T166
Test name
Test status
Simulation time 166029892312 ps
CPU time 110.32 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 12:46:49 PM PST 24
Peak memory 201156 kb
Host smart-6358a8c1-0129-430c-a1f5-fdf10af5febe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314972623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2314972623
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.200304705
Short name T248
Test name
Test status
Simulation time 329742503835 ps
CPU time 223.4 seconds
Started Mar 05 12:45:03 PM PST 24
Finished Mar 05 12:48:47 PM PST 24
Peak memory 201116 kb
Host smart-d1f1026d-e9f2-4b0d-a6d2-21e6e6f7bfd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200304705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.200304705
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.759158625
Short name T368
Test name
Test status
Simulation time 477900775788 ps
CPU time 116.83 seconds
Started Mar 05 12:44:58 PM PST 24
Finished Mar 05 12:46:55 PM PST 24
Peak memory 201128 kb
Host smart-515f2a80-1e53-4ed4-81f1-c6dcfcc67b65
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759158625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.759158625
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3052810186
Short name T724
Test name
Test status
Simulation time 153080924207 ps
CPU time 440.29 seconds
Started Mar 05 12:45:03 PM PST 24
Finished Mar 05 12:52:23 PM PST 24
Peak memory 201568 kb
Host smart-3efa3f34-b83a-4eed-b1b4-c91c5458f284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052810186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3052810186
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2807055044
Short name T483
Test name
Test status
Simulation time 37120886495 ps
CPU time 46.11 seconds
Started Mar 05 12:45:22 PM PST 24
Finished Mar 05 12:46:08 PM PST 24
Peak memory 201064 kb
Host smart-67db67e6-523b-4e13-840f-24cfee04a3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807055044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2807055044
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2840103734
Short name T671
Test name
Test status
Simulation time 5218426917 ps
CPU time 3.81 seconds
Started Mar 05 12:45:08 PM PST 24
Finished Mar 05 12:45:11 PM PST 24
Peak memory 201128 kb
Host smart-469715f6-7a7a-4f85-adae-0f9336fa1325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840103734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2840103734
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1026816369
Short name T44
Test name
Test status
Simulation time 4521757532 ps
CPU time 1.64 seconds
Started Mar 05 12:44:56 PM PST 24
Finished Mar 05 12:44:58 PM PST 24
Peak memory 216420 kb
Host smart-449d324d-c116-4ded-acd3-692ca6a9faa9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026816369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1026816369
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.939798543
Short name T352
Test name
Test status
Simulation time 5836419852 ps
CPU time 7.78 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:45:09 PM PST 24
Peak memory 201040 kb
Host smart-cb13e1b9-ca72-4bd2-ad37-1c9b0f95b148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939798543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.939798543
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.502434609
Short name T636
Test name
Test status
Simulation time 166205735779 ps
CPU time 393.71 seconds
Started Mar 05 12:45:13 PM PST 24
Finished Mar 05 12:51:47 PM PST 24
Peak memory 201172 kb
Host smart-dd4cf67b-5c52-4c19-b1c6-a337fd998b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502434609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.502434609
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1264435278
Short name T750
Test name
Test status
Simulation time 141810725089 ps
CPU time 48.52 seconds
Started Mar 05 12:45:02 PM PST 24
Finished Mar 05 12:45:52 PM PST 24
Peak memory 209896 kb
Host smart-68970501-ba56-4d37-a251-520b7ce4060e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264435278 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1264435278
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2765946507
Short name T350
Test name
Test status
Simulation time 340213517 ps
CPU time 0.83 seconds
Started Mar 05 12:46:14 PM PST 24
Finished Mar 05 12:46:15 PM PST 24
Peak memory 200900 kb
Host smart-06faf19f-0ec1-42e9-954f-0a46e479157f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765946507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2765946507
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.767956841
Short name T221
Test name
Test status
Simulation time 332139093413 ps
CPU time 195.06 seconds
Started Mar 05 12:46:15 PM PST 24
Finished Mar 05 12:49:30 PM PST 24
Peak memory 200984 kb
Host smart-45085a1b-5df8-4e72-9103-a45988ff21e3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767956841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.767956841
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1673672208
Short name T560
Test name
Test status
Simulation time 499975766654 ps
CPU time 1140.44 seconds
Started Mar 05 12:46:12 PM PST 24
Finished Mar 05 01:05:13 PM PST 24
Peak memory 201204 kb
Host smart-454301ab-9e62-472a-8e2f-caaaccb1d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673672208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1673672208
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2239884548
Short name T579
Test name
Test status
Simulation time 163687371022 ps
CPU time 179.66 seconds
Started Mar 05 12:46:12 PM PST 24
Finished Mar 05 12:49:12 PM PST 24
Peak memory 201096 kb
Host smart-26793dc5-a44d-4413-b202-7d5a3c2f6198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239884548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2239884548
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.4280098032
Short name T170
Test name
Test status
Simulation time 170069472510 ps
CPU time 207.48 seconds
Started Mar 05 12:46:12 PM PST 24
Finished Mar 05 12:49:39 PM PST 24
Peak memory 201168 kb
Host smart-25f91bf2-51a7-4acb-a444-b80609a4adaf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280098032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.4280098032
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.938634311
Short name T678
Test name
Test status
Simulation time 323710057309 ps
CPU time 169.57 seconds
Started Mar 05 12:46:12 PM PST 24
Finished Mar 05 12:49:02 PM PST 24
Peak memory 201032 kb
Host smart-be32310f-7903-47bf-a840-d9b6701a17a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938634311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.938634311
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1960862171
Short name T753
Test name
Test status
Simulation time 166204680310 ps
CPU time 411.66 seconds
Started Mar 05 12:46:14 PM PST 24
Finished Mar 05 12:53:06 PM PST 24
Peak memory 201012 kb
Host smart-d3929b34-fa4f-4470-b867-2dd2e350c8e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960862171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1960862171
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1134806612
Short name T550
Test name
Test status
Simulation time 166969098316 ps
CPU time 402.35 seconds
Started Mar 05 12:46:11 PM PST 24
Finished Mar 05 12:52:53 PM PST 24
Peak memory 201108 kb
Host smart-d7609612-e97f-4d03-83d1-e7f028aabc84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134806612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1134806612
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2982132999
Short name T2
Test name
Test status
Simulation time 331691119497 ps
CPU time 632.97 seconds
Started Mar 05 12:46:13 PM PST 24
Finished Mar 05 12:56:47 PM PST 24
Peak memory 201128 kb
Host smart-c042567e-6d69-4a99-9483-8839956f4f34
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982132999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2982132999
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1384166323
Short name T21
Test name
Test status
Simulation time 70456956218 ps
CPU time 293.89 seconds
Started Mar 05 12:46:17 PM PST 24
Finished Mar 05 12:51:11 PM PST 24
Peak memory 201516 kb
Host smart-c9ffac41-0706-4745-bfe7-df86cac4858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384166323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1384166323
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3108596637
Short name T642
Test name
Test status
Simulation time 36420577377 ps
CPU time 24.05 seconds
Started Mar 05 12:46:17 PM PST 24
Finished Mar 05 12:46:42 PM PST 24
Peak memory 201048 kb
Host smart-db75236c-1c1a-4dfe-b9d8-a55627402cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108596637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3108596637
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4212933835
Short name T545
Test name
Test status
Simulation time 4469833011 ps
CPU time 11.24 seconds
Started Mar 05 12:46:14 PM PST 24
Finished Mar 05 12:46:26 PM PST 24
Peak memory 200924 kb
Host smart-fcbe657b-15dd-4114-9533-c717681cd8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212933835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4212933835
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1094889354
Short name T394
Test name
Test status
Simulation time 5901466437 ps
CPU time 4.51 seconds
Started Mar 05 12:46:10 PM PST 24
Finished Mar 05 12:46:15 PM PST 24
Peak memory 201008 kb
Host smart-6f3a2493-4e84-4e32-b795-894e095fd834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094889354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1094889354
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2399729032
Short name T792
Test name
Test status
Simulation time 339043628148 ps
CPU time 179.72 seconds
Started Mar 05 12:46:11 PM PST 24
Finished Mar 05 12:49:11 PM PST 24
Peak memory 201268 kb
Host smart-5ef2025a-9888-46cf-9e7f-1b4c5489cb74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399729032 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2399729032
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2629882061
Short name T640
Test name
Test status
Simulation time 326651239 ps
CPU time 1.35 seconds
Started Mar 05 12:46:23 PM PST 24
Finished Mar 05 12:46:24 PM PST 24
Peak memory 200876 kb
Host smart-df50a7a9-69b7-4465-8b98-fdb48a367925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629882061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2629882061
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2965397382
Short name T66
Test name
Test status
Simulation time 163464849590 ps
CPU time 72.32 seconds
Started Mar 05 12:46:21 PM PST 24
Finished Mar 05 12:47:33 PM PST 24
Peak memory 201152 kb
Host smart-8a43dd29-be4d-4cc0-bc75-79d26cb3698d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965397382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2965397382
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3280436865
Short name T291
Test name
Test status
Simulation time 162673797955 ps
CPU time 192.26 seconds
Started Mar 05 12:46:26 PM PST 24
Finished Mar 05 12:49:39 PM PST 24
Peak memory 201096 kb
Host smart-d715b6be-3d41-4037-b711-da320216ccae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280436865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3280436865
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1436889918
Short name T744
Test name
Test status
Simulation time 165308363596 ps
CPU time 379.01 seconds
Started Mar 05 12:46:13 PM PST 24
Finished Mar 05 12:52:32 PM PST 24
Peak memory 201140 kb
Host smart-da8bf6fd-6700-4da4-a424-fe40629c6351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436889918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1436889918
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1034680961
Short name T608
Test name
Test status
Simulation time 160010479328 ps
CPU time 28.48 seconds
Started Mar 05 12:46:13 PM PST 24
Finished Mar 05 12:46:42 PM PST 24
Peak memory 201124 kb
Host smart-179302b2-a19a-4b92-91c6-3ff170ddb34e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034680961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1034680961
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3560083767
Short name T151
Test name
Test status
Simulation time 320297096393 ps
CPU time 152.58 seconds
Started Mar 05 12:46:12 PM PST 24
Finished Mar 05 12:48:44 PM PST 24
Peak memory 201144 kb
Host smart-22e740eb-4d62-43ef-8c3c-adc2bdb97404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560083767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3560083767
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.398606456
Short name T471
Test name
Test status
Simulation time 161083943228 ps
CPU time 373.37 seconds
Started Mar 05 12:46:13 PM PST 24
Finished Mar 05 12:52:27 PM PST 24
Peak memory 201108 kb
Host smart-24dcf9b0-a284-4f40-8506-03bfff191cf8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=398606456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fixe
d.398606456
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.567661152
Short name T464
Test name
Test status
Simulation time 160460211514 ps
CPU time 374.5 seconds
Started Mar 05 12:46:24 PM PST 24
Finished Mar 05 12:52:38 PM PST 24
Peak memory 201036 kb
Host smart-3fbc9fee-5d95-4942-b938-99d979359791
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567661152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.567661152
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3763599526
Short name T722
Test name
Test status
Simulation time 164496670965 ps
CPU time 123.79 seconds
Started Mar 05 12:46:22 PM PST 24
Finished Mar 05 12:48:26 PM PST 24
Peak memory 201156 kb
Host smart-a982c020-825c-4e7d-9aa1-447142cb5c49
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763599526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3763599526
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2722657546
Short name T333
Test name
Test status
Simulation time 144723914258 ps
CPU time 715.46 seconds
Started Mar 05 12:46:21 PM PST 24
Finished Mar 05 12:58:17 PM PST 24
Peak memory 201576 kb
Host smart-019aa3c1-7d53-49e1-a153-a69fbc81197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722657546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2722657546
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1105093762
Short name T498
Test name
Test status
Simulation time 49497818107 ps
CPU time 55.74 seconds
Started Mar 05 12:46:23 PM PST 24
Finished Mar 05 12:47:18 PM PST 24
Peak memory 201044 kb
Host smart-e01b82f8-2b1b-4039-9615-d0567024a3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105093762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1105093762
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.241276787
Short name T790
Test name
Test status
Simulation time 4409572768 ps
CPU time 2.97 seconds
Started Mar 05 12:46:21 PM PST 24
Finished Mar 05 12:46:24 PM PST 24
Peak memory 201096 kb
Host smart-4fde6a2a-c5d8-4840-97cf-586b38b9cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241276787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.241276787
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.4153752847
Short name T363
Test name
Test status
Simulation time 5769959866 ps
CPU time 3.81 seconds
Started Mar 05 12:46:11 PM PST 24
Finished Mar 05 12:46:15 PM PST 24
Peak memory 201052 kb
Host smart-cfb44978-92c5-4219-8a85-2b4aa9a73704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153752847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.4153752847
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.262216025
Short name T5
Test name
Test status
Simulation time 16289213271 ps
CPU time 43.81 seconds
Started Mar 05 12:46:20 PM PST 24
Finished Mar 05 12:47:04 PM PST 24
Peak memory 201140 kb
Host smart-bfb28efc-0888-4ad7-a9f9-d900f8471fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262216025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
262216025
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3989179731
Short name T229
Test name
Test status
Simulation time 49925167116 ps
CPU time 112.99 seconds
Started Mar 05 12:46:23 PM PST 24
Finished Mar 05 12:48:16 PM PST 24
Peak memory 201268 kb
Host smart-a9a5f0cb-c8ab-4e93-ad0e-ca7aea2dfb0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989179731 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3989179731
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3630331698
Short name T626
Test name
Test status
Simulation time 342417524 ps
CPU time 0.99 seconds
Started Mar 05 12:46:28 PM PST 24
Finished Mar 05 12:46:30 PM PST 24
Peak memory 201064 kb
Host smart-4433a6bc-9d16-4ca9-b3b2-8b0c20524c1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630331698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3630331698
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2185627466
Short name T318
Test name
Test status
Simulation time 167207665480 ps
CPU time 65.27 seconds
Started Mar 05 12:46:32 PM PST 24
Finished Mar 05 12:47:38 PM PST 24
Peak memory 201124 kb
Host smart-0c7f4503-c9e8-4300-839f-75b60259d467
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185627466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2185627466
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.905376540
Short name T319
Test name
Test status
Simulation time 485616358063 ps
CPU time 1152.84 seconds
Started Mar 05 12:46:31 PM PST 24
Finished Mar 05 01:05:44 PM PST 24
Peak memory 201032 kb
Host smart-ddc113f8-4278-4e1f-af69-185fc162a6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905376540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.905376540
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.946987801
Short name T214
Test name
Test status
Simulation time 164697135653 ps
CPU time 394.31 seconds
Started Mar 05 12:46:37 PM PST 24
Finished Mar 05 12:53:12 PM PST 24
Peak memory 201112 kb
Host smart-011f319d-0c7b-411a-b242-79994671fde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946987801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.946987801
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.715797795
Short name T433
Test name
Test status
Simulation time 490477651577 ps
CPU time 1078.75 seconds
Started Mar 05 12:46:29 PM PST 24
Finished Mar 05 01:04:28 PM PST 24
Peak memory 201152 kb
Host smart-d0e446af-5734-4dc7-b927-3e50c210aa9e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=715797795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.715797795
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.732926401
Short name T450
Test name
Test status
Simulation time 164548692786 ps
CPU time 83.44 seconds
Started Mar 05 12:46:22 PM PST 24
Finished Mar 05 12:47:45 PM PST 24
Peak memory 201196 kb
Host smart-9f1515eb-c496-4fae-b3f7-6159b4d40529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732926401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.732926401
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1928194852
Short name T692
Test name
Test status
Simulation time 492139082617 ps
CPU time 304.77 seconds
Started Mar 05 12:46:21 PM PST 24
Finished Mar 05 12:51:26 PM PST 24
Peak memory 201116 kb
Host smart-936ea643-187b-40d2-a86d-635bd2388a45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928194852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1928194852
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3457212011
Short name T489
Test name
Test status
Simulation time 345215779680 ps
CPU time 693.12 seconds
Started Mar 05 12:46:29 PM PST 24
Finished Mar 05 12:58:02 PM PST 24
Peak memory 201196 kb
Host smart-bf5449d4-7b2a-4c63-99ba-b9151b1adada
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457212011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3457212011
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.4204667950
Short name T695
Test name
Test status
Simulation time 507941158068 ps
CPU time 930.61 seconds
Started Mar 05 12:46:29 PM PST 24
Finished Mar 05 01:01:59 PM PST 24
Peak memory 201128 kb
Host smart-e618f339-1a35-4ee3-9ea7-95566be7cabd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204667950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.4204667950
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.520932488
Short name T342
Test name
Test status
Simulation time 115506916264 ps
CPU time 380.82 seconds
Started Mar 05 12:46:30 PM PST 24
Finished Mar 05 12:52:52 PM PST 24
Peak memory 201552 kb
Host smart-b34548ff-b009-47db-af10-324a7711bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520932488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.520932488
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.805877372
Short name T755
Test name
Test status
Simulation time 23223786106 ps
CPU time 13.76 seconds
Started Mar 05 12:46:32 PM PST 24
Finished Mar 05 12:46:46 PM PST 24
Peak memory 201064 kb
Host smart-b300b64a-984b-4ad2-9964-40d122e47a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805877372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.805877372
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2427093472
Short name T439
Test name
Test status
Simulation time 4962632439 ps
CPU time 12.57 seconds
Started Mar 05 12:46:34 PM PST 24
Finished Mar 05 12:46:47 PM PST 24
Peak memory 201064 kb
Host smart-ed67dde4-2ed9-4102-81dc-87d13bb7d251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427093472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2427093472
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1825948160
Short name T696
Test name
Test status
Simulation time 5913835325 ps
CPU time 14.27 seconds
Started Mar 05 12:46:22 PM PST 24
Finished Mar 05 12:46:36 PM PST 24
Peak memory 200960 kb
Host smart-1f4851dc-83ad-472d-994f-56430b9d4df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825948160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1825948160
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1155440830
Short name T628
Test name
Test status
Simulation time 199463396717 ps
CPU time 471.73 seconds
Started Mar 05 12:46:32 PM PST 24
Finished Mar 05 12:54:24 PM PST 24
Peak memory 209896 kb
Host smart-7131482b-c9f5-4049-8f51-3e05763b13a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155440830 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1155440830
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.3717018083
Short name T627
Test name
Test status
Simulation time 346179270 ps
CPU time 0.7 seconds
Started Mar 05 12:46:30 PM PST 24
Finished Mar 05 12:46:30 PM PST 24
Peak memory 200976 kb
Host smart-18af72ca-3e0d-4a9c-b073-9fab5ad8ed3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717018083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.3717018083
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1508811556
Short name T140
Test name
Test status
Simulation time 328135992518 ps
CPU time 731.51 seconds
Started Mar 05 12:46:33 PM PST 24
Finished Mar 05 12:58:45 PM PST 24
Peak memory 201200 kb
Host smart-faf9bdad-3cf0-4085-b112-a19d5cfdbfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508811556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1508811556
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.251377645
Short name T506
Test name
Test status
Simulation time 164765309394 ps
CPU time 25.41 seconds
Started Mar 05 12:46:31 PM PST 24
Finished Mar 05 12:46:56 PM PST 24
Peak memory 201168 kb
Host smart-caaf99f6-3f00-41a3-9a0f-800abac3bfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251377645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.251377645
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2723001819
Short name T359
Test name
Test status
Simulation time 328710706822 ps
CPU time 363.82 seconds
Started Mar 05 12:46:32 PM PST 24
Finished Mar 05 12:52:36 PM PST 24
Peak memory 201100 kb
Host smart-2458f63c-c1e4-44ae-a6b3-ed7bee6af594
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723001819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2723001819
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1200189961
Short name T260
Test name
Test status
Simulation time 163743750192 ps
CPU time 103.03 seconds
Started Mar 05 12:46:34 PM PST 24
Finished Mar 05 12:48:18 PM PST 24
Peak memory 201204 kb
Host smart-fd5f2372-c74e-4f57-a585-1eab7e287973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200189961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1200189961
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.6840407
Short name T369
Test name
Test status
Simulation time 490383778135 ps
CPU time 764.67 seconds
Started Mar 05 12:46:30 PM PST 24
Finished Mar 05 12:59:14 PM PST 24
Peak memory 201124 kb
Host smart-63d96c19-d6b2-43d3-8e5a-6cebbb91f7d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=6840407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixed.6840407
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1887505578
Short name T749
Test name
Test status
Simulation time 169458107727 ps
CPU time 254.5 seconds
Started Mar 05 12:46:31 PM PST 24
Finished Mar 05 12:50:46 PM PST 24
Peak memory 201124 kb
Host smart-e023b6c8-ce59-4b83-b9fb-74df2ed66db3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887505578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1887505578
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.4196175488
Short name T375
Test name
Test status
Simulation time 325767339164 ps
CPU time 753.1 seconds
Started Mar 05 12:46:33 PM PST 24
Finished Mar 05 12:59:06 PM PST 24
Peak memory 201124 kb
Host smart-4c6180a7-70d1-4f68-bcae-24065e7717c8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196175488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.4196175488
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2330540991
Short name T746
Test name
Test status
Simulation time 82242596638 ps
CPU time 479.42 seconds
Started Mar 05 12:46:33 PM PST 24
Finished Mar 05 12:54:32 PM PST 24
Peak memory 201512 kb
Host smart-29f26cd4-e48a-41c8-84d4-9c8be149fc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330540991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2330540991
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3438910930
Short name T422
Test name
Test status
Simulation time 25078406114 ps
CPU time 26.47 seconds
Started Mar 05 12:46:31 PM PST 24
Finished Mar 05 12:46:58 PM PST 24
Peak memory 201048 kb
Host smart-fd1da694-983f-4b59-b22b-3c593b26be07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438910930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3438910930
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1594403458
Short name T705
Test name
Test status
Simulation time 2936383114 ps
CPU time 4.05 seconds
Started Mar 05 12:46:31 PM PST 24
Finished Mar 05 12:46:35 PM PST 24
Peak memory 200924 kb
Host smart-52c7d95c-2e0b-41c9-a3a9-97a20db214eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594403458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1594403458
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.2931038849
Short name T543
Test name
Test status
Simulation time 6114387422 ps
CPU time 9.18 seconds
Started Mar 05 12:46:33 PM PST 24
Finished Mar 05 12:46:43 PM PST 24
Peak memory 201056 kb
Host smart-c5b92cc2-e9cd-493a-849b-ad5d81a8b1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931038849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.2931038849
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.746206004
Short name T632
Test name
Test status
Simulation time 601422492810 ps
CPU time 1501.18 seconds
Started Mar 05 12:46:31 PM PST 24
Finished Mar 05 01:11:33 PM PST 24
Peak memory 201508 kb
Host smart-689bac05-b14f-4f54-bca1-2021fd14a604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746206004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
746206004
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1405341264
Short name T79
Test name
Test status
Simulation time 120766873376 ps
CPU time 179.6 seconds
Started Mar 05 12:46:31 PM PST 24
Finished Mar 05 12:49:30 PM PST 24
Peak memory 217856 kb
Host smart-db3cef5e-31f8-43a5-8739-a126cc3ebafb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405341264 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1405341264
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.2693507868
Short name T729
Test name
Test status
Simulation time 349724996 ps
CPU time 0.99 seconds
Started Mar 05 12:46:51 PM PST 24
Finished Mar 05 12:46:52 PM PST 24
Peak memory 200968 kb
Host smart-02a43bd1-f75b-431d-a137-747599dd7dbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693507868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.2693507868
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1171217320
Short name T173
Test name
Test status
Simulation time 506300889091 ps
CPU time 576.82 seconds
Started Mar 05 12:46:37 PM PST 24
Finished Mar 05 12:56:14 PM PST 24
Peak memory 200996 kb
Host smart-b3542c4a-fbc7-4204-adb8-2e99a2820833
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171217320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1171217320
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.1155081256
Short name T603
Test name
Test status
Simulation time 325620887868 ps
CPU time 711.77 seconds
Started Mar 05 12:46:41 PM PST 24
Finished Mar 05 12:58:33 PM PST 24
Peak memory 201140 kb
Host smart-0c7578fc-db47-477d-9872-fce452ddebbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155081256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.1155081256
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2205186979
Short name T785
Test name
Test status
Simulation time 163735086063 ps
CPU time 364.59 seconds
Started Mar 05 12:46:40 PM PST 24
Finished Mar 05 12:52:45 PM PST 24
Peak memory 201160 kb
Host smart-5fe5b07c-3ceb-4421-a0a3-d37a1ec5876f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205186979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2205186979
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3400775795
Short name T770
Test name
Test status
Simulation time 167034169376 ps
CPU time 184.18 seconds
Started Mar 05 12:46:29 PM PST 24
Finished Mar 05 12:49:33 PM PST 24
Peak memory 201144 kb
Host smart-341c5fb8-97b3-4383-9df3-216fc387a022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400775795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3400775795
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2830005749
Short name T167
Test name
Test status
Simulation time 161572298884 ps
CPU time 119.6 seconds
Started Mar 05 12:46:34 PM PST 24
Finished Mar 05 12:48:34 PM PST 24
Peak memory 201120 kb
Host smart-fdfac055-704e-471a-b980-c526f44fa9f8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830005749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2830005749
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1222449103
Short name T784
Test name
Test status
Simulation time 495145855724 ps
CPU time 306.76 seconds
Started Mar 05 12:46:38 PM PST 24
Finished Mar 05 12:51:45 PM PST 24
Peak memory 201200 kb
Host smart-57a87b22-b1dc-40dd-b0be-c8f9ba8162ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222449103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1222449103
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2861245255
Short name T629
Test name
Test status
Simulation time 156621951806 ps
CPU time 96.2 seconds
Started Mar 05 12:46:39 PM PST 24
Finished Mar 05 12:48:15 PM PST 24
Peak memory 201224 kb
Host smart-3579b481-c9f9-4c1a-9529-b39790f7cc66
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861245255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2861245255
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2303136282
Short name T573
Test name
Test status
Simulation time 86023112002 ps
CPU time 301.51 seconds
Started Mar 05 12:46:42 PM PST 24
Finished Mar 05 12:51:44 PM PST 24
Peak memory 201520 kb
Host smart-9738310d-033f-4a15-aa42-f89208780004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303136282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2303136282
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1976951499
Short name T374
Test name
Test status
Simulation time 27656921811 ps
CPU time 17.07 seconds
Started Mar 05 12:46:40 PM PST 24
Finished Mar 05 12:46:57 PM PST 24
Peak memory 201020 kb
Host smart-5795f3c3-e503-4fd8-961f-e49018738cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976951499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1976951499
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.59980590
Short name T112
Test name
Test status
Simulation time 3096909178 ps
CPU time 7.68 seconds
Started Mar 05 12:46:38 PM PST 24
Finished Mar 05 12:46:46 PM PST 24
Peak memory 201048 kb
Host smart-ea0928cf-f44b-4ee6-8c4b-3a4c0bce23eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59980590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.59980590
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1843544929
Short name T789
Test name
Test status
Simulation time 5712236136 ps
CPU time 6.72 seconds
Started Mar 05 12:46:33 PM PST 24
Finished Mar 05 12:46:40 PM PST 24
Peak memory 200976 kb
Host smart-54afe1b4-7119-4ddc-93e3-dc60b2f90dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843544929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1843544929
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.535700755
Short name T261
Test name
Test status
Simulation time 174697648276 ps
CPU time 95.93 seconds
Started Mar 05 12:46:42 PM PST 24
Finished Mar 05 12:48:19 PM PST 24
Peak memory 201200 kb
Host smart-3df6fa1b-6ca6-4243-89ef-057169adc003
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535700755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all.
535700755
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2389071703
Short name T717
Test name
Test status
Simulation time 348832913 ps
CPU time 1.08 seconds
Started Mar 05 12:47:03 PM PST 24
Finished Mar 05 12:47:04 PM PST 24
Peak memory 200928 kb
Host smart-b0401301-ab8a-4ae5-867e-95ae9a9dd658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389071703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2389071703
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2244930169
Short name T152
Test name
Test status
Simulation time 496973563697 ps
CPU time 106.75 seconds
Started Mar 05 12:46:51 PM PST 24
Finished Mar 05 12:48:38 PM PST 24
Peak memory 201068 kb
Host smart-ad2dc4a8-20e3-4fbe-85ae-5d6156c15a26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244930169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2244930169
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1033290433
Short name T473
Test name
Test status
Simulation time 161067471829 ps
CPU time 368.48 seconds
Started Mar 05 12:46:49 PM PST 24
Finished Mar 05 12:52:58 PM PST 24
Peak memory 201112 kb
Host smart-244a8d06-fafe-4d11-baed-ac6ffd762b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033290433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1033290433
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1872462748
Short name T51
Test name
Test status
Simulation time 157792474303 ps
CPU time 52.75 seconds
Started Mar 05 12:46:47 PM PST 24
Finished Mar 05 12:47:40 PM PST 24
Peak memory 201140 kb
Host smart-df0544d1-5ff6-42e6-be4e-146b60992c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872462748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1872462748
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1486300692
Short name T571
Test name
Test status
Simulation time 336743391618 ps
CPU time 746.01 seconds
Started Mar 05 12:46:49 PM PST 24
Finished Mar 05 12:59:15 PM PST 24
Peak memory 201012 kb
Host smart-97d27b21-821d-4b3b-8829-eab5c18af49c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486300692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1486300692
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.2457021128
Short name T670
Test name
Test status
Simulation time 165619585491 ps
CPU time 180.83 seconds
Started Mar 05 12:46:50 PM PST 24
Finished Mar 05 12:49:51 PM PST 24
Peak memory 201144 kb
Host smart-b4140b1f-fe64-4059-be3b-1cb274323d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457021128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.2457021128
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2552364620
Short name T415
Test name
Test status
Simulation time 486672611481 ps
CPU time 1110.22 seconds
Started Mar 05 12:46:51 PM PST 24
Finished Mar 05 01:05:22 PM PST 24
Peak memory 201124 kb
Host smart-ff0ea518-e7a0-4b3a-b2d8-cb3cbb5a08c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552364620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2552364620
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2511930452
Short name T70
Test name
Test status
Simulation time 166762763438 ps
CPU time 154.71 seconds
Started Mar 05 12:46:55 PM PST 24
Finished Mar 05 12:49:30 PM PST 24
Peak memory 201200 kb
Host smart-2fd8d12d-99d1-4b7b-ba71-e821fb509f4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511930452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2511930452
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.251373056
Short name T631
Test name
Test status
Simulation time 167999337968 ps
CPU time 370.98 seconds
Started Mar 05 12:46:48 PM PST 24
Finished Mar 05 12:52:59 PM PST 24
Peak memory 201068 kb
Host smart-1d7e8f5e-ddaf-4587-ba7f-b8acfe1fb95e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251373056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
adc_ctrl_filters_wakeup_fixed.251373056
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1058861516
Short name T24
Test name
Test status
Simulation time 101130760078 ps
CPU time 428.45 seconds
Started Mar 05 12:46:57 PM PST 24
Finished Mar 05 12:54:06 PM PST 24
Peak memory 201620 kb
Host smart-8875322c-65bb-4d15-8564-df64e6aad4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058861516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1058861516
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.4073755088
Short name T351
Test name
Test status
Simulation time 25182634547 ps
CPU time 52.34 seconds
Started Mar 05 12:46:57 PM PST 24
Finished Mar 05 12:47:49 PM PST 24
Peak memory 200872 kb
Host smart-c26f6ea0-198c-4094-bdbc-3ed3e86cce4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073755088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.4073755088
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2668146353
Short name T467
Test name
Test status
Simulation time 4381894838 ps
CPU time 11.82 seconds
Started Mar 05 12:46:59 PM PST 24
Finished Mar 05 12:47:11 PM PST 24
Peak memory 201060 kb
Host smart-631019ff-7c89-4448-85a8-8e8a250d4d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668146353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2668146353
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.255939436
Short name T364
Test name
Test status
Simulation time 5519368886 ps
CPU time 14.36 seconds
Started Mar 05 12:46:49 PM PST 24
Finished Mar 05 12:47:04 PM PST 24
Peak memory 200984 kb
Host smart-72d3be3a-a0c2-4ff4-b124-bc5d77135f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255939436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.255939436
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1619702262
Short name T123
Test name
Test status
Simulation time 334663010436 ps
CPU time 206.76 seconds
Started Mar 05 12:47:00 PM PST 24
Finished Mar 05 12:50:27 PM PST 24
Peak memory 201060 kb
Host smart-e630afbb-08b2-47df-8335-f6d710523a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619702262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1619702262
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1467365440
Short name T61
Test name
Test status
Simulation time 18934294157 ps
CPU time 37.96 seconds
Started Mar 05 12:46:59 PM PST 24
Finished Mar 05 12:47:37 PM PST 24
Peak memory 201324 kb
Host smart-85947ed9-351b-4c52-bfca-08437081a926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467365440 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1467365440
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2083714296
Short name T380
Test name
Test status
Simulation time 442260322 ps
CPU time 1.16 seconds
Started Mar 05 12:47:17 PM PST 24
Finished Mar 05 12:47:18 PM PST 24
Peak memory 200788 kb
Host smart-45647c78-492b-4963-9da5-843fa44a62df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083714296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2083714296
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.2038478543
Short name T290
Test name
Test status
Simulation time 336999880082 ps
CPU time 402.92 seconds
Started Mar 05 12:47:06 PM PST 24
Finished Mar 05 12:53:49 PM PST 24
Peak memory 201148 kb
Host smart-69b5d3b6-03b9-4c92-9d44-ef94e5e630ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038478543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.2038478543
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.2891395332
Short name T488
Test name
Test status
Simulation time 163059207212 ps
CPU time 184.84 seconds
Started Mar 05 12:46:58 PM PST 24
Finished Mar 05 12:50:03 PM PST 24
Peak memory 201096 kb
Host smart-b2c2030e-274e-4f3f-881e-7f3582c93f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891395332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.2891395332
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3015354870
Short name T423
Test name
Test status
Simulation time 167785225898 ps
CPU time 105.37 seconds
Started Mar 05 12:46:56 PM PST 24
Finished Mar 05 12:48:42 PM PST 24
Peak memory 201168 kb
Host smart-e92aa7a0-20e4-42f0-a48e-b0f79de40376
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015354870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3015354870
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.101610494
Short name T272
Test name
Test status
Simulation time 497702257528 ps
CPU time 1071.75 seconds
Started Mar 05 12:46:59 PM PST 24
Finished Mar 05 01:04:51 PM PST 24
Peak memory 201200 kb
Host smart-3a13bdd3-8292-48ea-9b05-6f23633175c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101610494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.101610494
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.842202938
Short name T381
Test name
Test status
Simulation time 482827094309 ps
CPU time 545.27 seconds
Started Mar 05 12:46:57 PM PST 24
Finished Mar 05 12:56:03 PM PST 24
Peak memory 201120 kb
Host smart-a63ba0dd-979e-4427-93e0-0da2eadf4814
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=842202938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.842202938
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1485378243
Short name T224
Test name
Test status
Simulation time 331390734582 ps
CPU time 284.76 seconds
Started Mar 05 12:46:58 PM PST 24
Finished Mar 05 12:51:43 PM PST 24
Peak memory 201116 kb
Host smart-df2d1bd4-7e11-41e7-a83f-1e3d1bce4387
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485378243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1485378243
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1400650473
Short name T453
Test name
Test status
Simulation time 164297111205 ps
CPU time 203.66 seconds
Started Mar 05 12:47:10 PM PST 24
Finished Mar 05 12:50:34 PM PST 24
Peak memory 201128 kb
Host smart-91d6df41-296f-43c1-afc9-c0cb9f68e493
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400650473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1400650473
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3011572604
Short name T332
Test name
Test status
Simulation time 123049605188 ps
CPU time 456.55 seconds
Started Mar 05 12:47:16 PM PST 24
Finished Mar 05 12:54:52 PM PST 24
Peak memory 201496 kb
Host smart-bc574534-4e75-4197-ace4-dd0b68c69620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011572604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3011572604
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2308527960
Short name T697
Test name
Test status
Simulation time 31236114715 ps
CPU time 50.71 seconds
Started Mar 05 12:47:09 PM PST 24
Finished Mar 05 12:48:00 PM PST 24
Peak memory 200992 kb
Host smart-1e8e71eb-0518-4ba6-b07e-e14d7b07f672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308527960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2308527960
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.49335819
Short name T525
Test name
Test status
Simulation time 4128631895 ps
CPU time 7.95 seconds
Started Mar 05 12:47:12 PM PST 24
Finished Mar 05 12:47:20 PM PST 24
Peak memory 201044 kb
Host smart-162a1f4d-680e-4e28-8424-01bb392287e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49335819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.49335819
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2991724700
Short name T142
Test name
Test status
Simulation time 6064341624 ps
CPU time 6.38 seconds
Started Mar 05 12:46:59 PM PST 24
Finished Mar 05 12:47:06 PM PST 24
Peak memory 200952 kb
Host smart-1605cbbf-eb0e-45ac-9c27-5580e256ac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991724700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2991724700
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1868163946
Short name T562
Test name
Test status
Simulation time 331688005371 ps
CPU time 627.15 seconds
Started Mar 05 12:47:22 PM PST 24
Finished Mar 05 12:57:49 PM PST 24
Peak memory 201140 kb
Host smart-8fc61f19-fd63-4756-8f60-039db1b9fe07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868163946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1868163946
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3306074871
Short name T474
Test name
Test status
Simulation time 423001858 ps
CPU time 1.65 seconds
Started Mar 05 12:47:25 PM PST 24
Finished Mar 05 12:47:27 PM PST 24
Peak memory 200932 kb
Host smart-f38e66b5-ab00-4064-8792-5992dfc2ab47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306074871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3306074871
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.82876999
Short name T677
Test name
Test status
Simulation time 493782423176 ps
CPU time 427.9 seconds
Started Mar 05 12:47:24 PM PST 24
Finished Mar 05 12:54:32 PM PST 24
Peak memory 201224 kb
Host smart-f6e8f84a-fe07-47f2-9d35-695d818ddd7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82876999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gatin
g.82876999
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3790864001
Short name T306
Test name
Test status
Simulation time 170487439199 ps
CPU time 276.03 seconds
Started Mar 05 12:47:24 PM PST 24
Finished Mar 05 12:52:00 PM PST 24
Peak memory 201184 kb
Host smart-cfcb357c-70de-4e1d-b8f0-e1b735bd21c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790864001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3790864001
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.106035588
Short name T284
Test name
Test status
Simulation time 482558580405 ps
CPU time 1042.86 seconds
Started Mar 05 12:47:20 PM PST 24
Finished Mar 05 01:04:43 PM PST 24
Peak memory 201136 kb
Host smart-160c9498-3bbd-473e-8f22-85fc8175d6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106035588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.106035588
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1546601155
Short name T357
Test name
Test status
Simulation time 491329606360 ps
CPU time 343.18 seconds
Started Mar 05 12:47:22 PM PST 24
Finished Mar 05 12:53:05 PM PST 24
Peak memory 201124 kb
Host smart-e88daf77-50ea-4d69-bfc9-815e14ef40a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546601155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1546601155
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2887004489
Short name T148
Test name
Test status
Simulation time 326575426045 ps
CPU time 171.95 seconds
Started Mar 05 12:47:14 PM PST 24
Finished Mar 05 12:50:06 PM PST 24
Peak memory 201076 kb
Host smart-d455158f-56f4-4216-800b-4b777119db40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887004489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2887004489
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1286126854
Short name T440
Test name
Test status
Simulation time 487885832701 ps
CPU time 1180.47 seconds
Started Mar 05 12:47:16 PM PST 24
Finished Mar 05 01:06:56 PM PST 24
Peak memory 201092 kb
Host smart-fc8360cd-6896-4821-b94c-648cd839ab12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286126854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1286126854
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1468308947
Short name T714
Test name
Test status
Simulation time 332510427343 ps
CPU time 107.63 seconds
Started Mar 05 12:47:26 PM PST 24
Finished Mar 05 12:49:13 PM PST 24
Peak memory 201136 kb
Host smart-9fa83db4-2b61-4bd7-9c0f-266704f11f2b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468308947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1468308947
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1055183001
Short name T175
Test name
Test status
Simulation time 165952127367 ps
CPU time 96.19 seconds
Started Mar 05 12:47:24 PM PST 24
Finished Mar 05 12:49:01 PM PST 24
Peak memory 201124 kb
Host smart-44f8cd39-806f-4551-a670-d24017bc4ad5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055183001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1055183001
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1777439366
Short name T694
Test name
Test status
Simulation time 28938349990 ps
CPU time 16.82 seconds
Started Mar 05 12:47:23 PM PST 24
Finished Mar 05 12:47:40 PM PST 24
Peak memory 201048 kb
Host smart-bf817cfe-a56f-4c9d-aa78-e139650b355a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777439366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1777439366
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1072011527
Short name T445
Test name
Test status
Simulation time 3986980236 ps
CPU time 5.1 seconds
Started Mar 05 12:47:25 PM PST 24
Finished Mar 05 12:47:30 PM PST 24
Peak memory 201000 kb
Host smart-ebbe8b77-f3d8-4887-8ac6-ad49d6401c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072011527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1072011527
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3926061557
Short name T787
Test name
Test status
Simulation time 5892734652 ps
CPU time 15.62 seconds
Started Mar 05 12:47:18 PM PST 24
Finished Mar 05 12:47:34 PM PST 24
Peak memory 201004 kb
Host smart-7d03c224-f3c5-42ca-aa9d-cf62f33520f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926061557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3926061557
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.771736803
Short name T247
Test name
Test status
Simulation time 169557730747 ps
CPU time 410.03 seconds
Started Mar 05 12:47:24 PM PST 24
Finished Mar 05 12:54:14 PM PST 24
Peak memory 201236 kb
Host smart-395ff8d9-fb9c-4718-b247-585640fda556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771736803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
771736803
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3849387995
Short name T4
Test name
Test status
Simulation time 530710339 ps
CPU time 1.79 seconds
Started Mar 05 12:47:33 PM PST 24
Finished Mar 05 12:47:35 PM PST 24
Peak memory 200820 kb
Host smart-901bcb26-6801-4af3-859f-adeab76318bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849387995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3849387995
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.4280892821
Short name T485
Test name
Test status
Simulation time 163720352998 ps
CPU time 363.17 seconds
Started Mar 05 12:47:35 PM PST 24
Finished Mar 05 12:53:38 PM PST 24
Peak memory 201064 kb
Host smart-634d8ff5-4547-4f01-9b22-58c639990d4f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280892821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.4280892821
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.455306948
Short name T52
Test name
Test status
Simulation time 159167467880 ps
CPU time 83.43 seconds
Started Mar 05 12:47:33 PM PST 24
Finished Mar 05 12:48:57 PM PST 24
Peak memory 201204 kb
Host smart-1a348203-a1d1-4dfc-a2bc-7e90226878ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455306948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.455306948
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.2021317725
Short name T741
Test name
Test status
Simulation time 323260163990 ps
CPU time 364.1 seconds
Started Mar 05 12:47:33 PM PST 24
Finished Mar 05 12:53:38 PM PST 24
Peak memory 201140 kb
Host smart-cd607d1e-581c-4978-8ade-8bf843b939a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021317725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.2021317725
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.3089826960
Short name T620
Test name
Test status
Simulation time 162989173899 ps
CPU time 93.13 seconds
Started Mar 05 12:47:36 PM PST 24
Finished Mar 05 12:49:09 PM PST 24
Peak memory 201160 kb
Host smart-55b7a68d-8f1a-45fa-9bbe-5c06f48bd8e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089826960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.3089826960
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.844144742
Short name T147
Test name
Test status
Simulation time 160762697663 ps
CPU time 93.73 seconds
Started Mar 05 12:47:33 PM PST 24
Finished Mar 05 12:49:06 PM PST 24
Peak memory 201112 kb
Host smart-8e4541d7-d228-4103-aa77-1b47720d4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844144742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.844144742
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1604384178
Short name T398
Test name
Test status
Simulation time 167558142204 ps
CPU time 94.89 seconds
Started Mar 05 12:47:35 PM PST 24
Finished Mar 05 12:49:10 PM PST 24
Peak memory 201124 kb
Host smart-c11fb0b4-0813-46b4-8b3f-06815fa56b32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604384178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1604384178
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1471919906
Short name T8
Test name
Test status
Simulation time 172506817103 ps
CPU time 427.69 seconds
Started Mar 05 12:47:33 PM PST 24
Finished Mar 05 12:54:40 PM PST 24
Peak memory 201168 kb
Host smart-5b75204a-19a4-443a-9a54-c17e8c9c0483
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471919906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1471919906
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.375902529
Short name T20
Test name
Test status
Simulation time 483649666846 ps
CPU time 252.52 seconds
Started Mar 05 12:47:32 PM PST 24
Finished Mar 05 12:51:45 PM PST 24
Peak memory 201168 kb
Host smart-5eff8e57-58da-4e99-b8f7-7552139beffd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375902529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.375902529
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.653002093
Short name T23
Test name
Test status
Simulation time 68443060518 ps
CPU time 269.67 seconds
Started Mar 05 12:47:32 PM PST 24
Finished Mar 05 12:52:02 PM PST 24
Peak memory 201508 kb
Host smart-e5ba6bdd-6ddf-46bc-9326-fc2245886e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653002093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.653002093
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.853779241
Short name T547
Test name
Test status
Simulation time 40836414398 ps
CPU time 86.45 seconds
Started Mar 05 12:47:35 PM PST 24
Finished Mar 05 12:49:02 PM PST 24
Peak memory 201084 kb
Host smart-4c5b43c8-9660-458f-bca6-af980f49e039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853779241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.853779241
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3364268673
Short name T347
Test name
Test status
Simulation time 4163095158 ps
CPU time 3.05 seconds
Started Mar 05 12:47:35 PM PST 24
Finished Mar 05 12:47:38 PM PST 24
Peak memory 201004 kb
Host smart-1ade457f-0879-45c2-b917-f8b970308704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364268673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3364268673
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3058496624
Short name T461
Test name
Test status
Simulation time 5897036269 ps
CPU time 7.36 seconds
Started Mar 05 12:47:23 PM PST 24
Finished Mar 05 12:47:30 PM PST 24
Peak memory 201056 kb
Host smart-e583da4a-37ab-46cd-9c09-09f04369f506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058496624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3058496624
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.2997550137
Short name T751
Test name
Test status
Simulation time 327659931008 ps
CPU time 397.36 seconds
Started Mar 05 12:47:36 PM PST 24
Finished Mar 05 12:54:14 PM PST 24
Peak memory 201200 kb
Host smart-693dee5f-fb36-4fe8-941e-1a1092d81eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997550137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.2997550137
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2075451463
Short name T773
Test name
Test status
Simulation time 322898487710 ps
CPU time 201.71 seconds
Started Mar 05 12:47:34 PM PST 24
Finished Mar 05 12:50:56 PM PST 24
Peak memory 209812 kb
Host smart-212b559d-c197-4e5f-8efe-d0c5c7bbc5cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075451463 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2075451463
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2808963717
Short name T462
Test name
Test status
Simulation time 528934528 ps
CPU time 1.84 seconds
Started Mar 05 12:47:45 PM PST 24
Finished Mar 05 12:47:47 PM PST 24
Peak memory 200928 kb
Host smart-74a529a5-6fc0-4f9c-ac34-7eaa08c24563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808963717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2808963717
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2372426069
Short name T602
Test name
Test status
Simulation time 165580036125 ps
CPU time 418.46 seconds
Started Mar 05 12:47:40 PM PST 24
Finished Mar 05 12:54:39 PM PST 24
Peak memory 201132 kb
Host smart-95877633-1c2b-4399-8b48-5b14b0ebb76f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372426069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2372426069
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2262694266
Short name T612
Test name
Test status
Simulation time 491813743249 ps
CPU time 1122.61 seconds
Started Mar 05 12:47:44 PM PST 24
Finished Mar 05 01:06:27 PM PST 24
Peak memory 201084 kb
Host smart-c8051c17-3fa2-4e8e-816a-3e948c0568c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262694266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2262694266
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3654589077
Short name T241
Test name
Test status
Simulation time 319564058982 ps
CPU time 646.35 seconds
Started Mar 05 12:47:42 PM PST 24
Finished Mar 05 12:58:28 PM PST 24
Peak memory 201200 kb
Host smart-51325aa7-c987-4b77-be54-60a5960a7662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654589077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3654589077
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.4191179358
Short name T683
Test name
Test status
Simulation time 328401017229 ps
CPU time 410.49 seconds
Started Mar 05 12:47:42 PM PST 24
Finished Mar 05 12:54:33 PM PST 24
Peak memory 201100 kb
Host smart-905f2fe6-9e32-4289-93a6-87a90e27bcbd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191179358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.4191179358
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1541237451
Short name T653
Test name
Test status
Simulation time 163598197935 ps
CPU time 102.95 seconds
Started Mar 05 12:47:41 PM PST 24
Finished Mar 05 12:49:24 PM PST 24
Peak memory 201188 kb
Host smart-4d5a8bd5-70dc-46e8-89d0-07e0588fb2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541237451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1541237451
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4000790457
Short name T499
Test name
Test status
Simulation time 483089490912 ps
CPU time 1151.91 seconds
Started Mar 05 12:47:45 PM PST 24
Finished Mar 05 01:06:57 PM PST 24
Peak memory 201180 kb
Host smart-8bf8d602-3ef8-4866-a57b-89018430e77a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000790457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4000790457
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.1995257505
Short name T304
Test name
Test status
Simulation time 173025628322 ps
CPU time 120.74 seconds
Started Mar 05 12:47:51 PM PST 24
Finished Mar 05 12:49:52 PM PST 24
Peak memory 201076 kb
Host smart-34ada943-96ac-4cd8-ba79-f30ca40dde20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995257505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.1995257505
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2765710070
Short name T371
Test name
Test status
Simulation time 325851433077 ps
CPU time 210.59 seconds
Started Mar 05 12:47:42 PM PST 24
Finished Mar 05 12:51:13 PM PST 24
Peak memory 201060 kb
Host smart-2d2e1e2f-d94b-4b3c-81f8-70058dad17ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765710070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2765710070
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.610374948
Short name T650
Test name
Test status
Simulation time 146306525431 ps
CPU time 715.11 seconds
Started Mar 05 12:47:41 PM PST 24
Finished Mar 05 12:59:37 PM PST 24
Peak memory 201464 kb
Host smart-d17d5342-74dc-4dd7-9cbc-841ba2c2af8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610374948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.610374948
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2190111124
Short name T396
Test name
Test status
Simulation time 30218779103 ps
CPU time 17.25 seconds
Started Mar 05 12:47:44 PM PST 24
Finished Mar 05 12:48:02 PM PST 24
Peak memory 200988 kb
Host smart-de9118ea-d6cc-4038-9f60-2ab41941805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190111124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2190111124
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3658626747
Short name T536
Test name
Test status
Simulation time 2852514363 ps
CPU time 1.51 seconds
Started Mar 05 12:47:45 PM PST 24
Finished Mar 05 12:47:47 PM PST 24
Peak memory 200984 kb
Host smart-75d9c10b-8d4a-4f58-81b9-0467b50ebe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658626747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3658626747
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3037826896
Short name T443
Test name
Test status
Simulation time 5778812051 ps
CPU time 4.27 seconds
Started Mar 05 12:47:46 PM PST 24
Finished Mar 05 12:47:50 PM PST 24
Peak memory 201024 kb
Host smart-e7a0a29f-f873-4001-baf9-175326fb36b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037826896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3037826896
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.189613298
Short name T251
Test name
Test status
Simulation time 204575481303 ps
CPU time 128.83 seconds
Started Mar 05 12:47:45 PM PST 24
Finished Mar 05 12:49:54 PM PST 24
Peak memory 201056 kb
Host smart-0a530fb5-a975-4db2-a8f7-9e2255081fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189613298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
189613298
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2072055339
Short name T74
Test name
Test status
Simulation time 28922271433 ps
CPU time 70.91 seconds
Started Mar 05 12:47:41 PM PST 24
Finished Mar 05 12:48:52 PM PST 24
Peak memory 209896 kb
Host smart-9b90ef23-8482-4feb-8e4c-d459006f431c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072055339 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2072055339
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.330734639
Short name T548
Test name
Test status
Simulation time 456537606 ps
CPU time 0.7 seconds
Started Mar 05 12:45:04 PM PST 24
Finished Mar 05 12:45:04 PM PST 24
Peak memory 200872 kb
Host smart-f59f6945-0ad6-46dc-91ba-b6990e4ad861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330734639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.330734639
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2004660614
Short name T68
Test name
Test status
Simulation time 159319505491 ps
CPU time 55.57 seconds
Started Mar 05 12:45:27 PM PST 24
Finished Mar 05 12:46:23 PM PST 24
Peak memory 201124 kb
Host smart-707d937c-0e86-4f60-887c-73ceb803e9ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004660614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2004660614
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3935191364
Short name T226
Test name
Test status
Simulation time 319166474552 ps
CPU time 211.99 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:48:43 PM PST 24
Peak memory 201196 kb
Host smart-010f53f2-5d95-4a47-a952-e63f4e6e0e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935191364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3935191364
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3106510862
Short name T619
Test name
Test status
Simulation time 326725592621 ps
CPU time 195.26 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 12:48:19 PM PST 24
Peak memory 201072 kb
Host smart-0e5f3ba6-3afe-44a1-8139-c56daef2e2ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106510862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3106510862
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1669995607
Short name T10
Test name
Test status
Simulation time 336902532325 ps
CPU time 745.27 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 12:57:30 PM PST 24
Peak memory 201192 kb
Host smart-f64661b1-f2af-456d-962b-06248348a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669995607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1669995607
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.4036644912
Short name T701
Test name
Test status
Simulation time 159421200094 ps
CPU time 369.1 seconds
Started Mar 05 12:45:00 PM PST 24
Finished Mar 05 12:51:09 PM PST 24
Peak memory 201156 kb
Host smart-bc59d8b8-2baa-4786-a0a9-c2d90698effe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036644912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.4036644912
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3971033505
Short name T293
Test name
Test status
Simulation time 169024026699 ps
CPU time 100.25 seconds
Started Mar 05 12:45:03 PM PST 24
Finished Mar 05 12:46:44 PM PST 24
Peak memory 201140 kb
Host smart-cbf2e1ca-3abd-4ee9-86b8-9444adb83f7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971033505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3971033505
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4019592733
Short name T349
Test name
Test status
Simulation time 495955744386 ps
CPU time 1046.62 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 01:02:26 PM PST 24
Peak memory 201160 kb
Host smart-d942c380-307d-4546-a775-e569eb1b31ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019592733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4019592733
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3460514818
Short name T30
Test name
Test status
Simulation time 111571369993 ps
CPU time 377.97 seconds
Started Mar 05 12:45:07 PM PST 24
Finished Mar 05 12:51:25 PM PST 24
Peak memory 201512 kb
Host smart-05d60559-b111-4d00-b2d1-52cec55f42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460514818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3460514818
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1763846847
Short name T367
Test name
Test status
Simulation time 40839869405 ps
CPU time 95.62 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 12:46:35 PM PST 24
Peak memory 201060 kb
Host smart-e425f078-74b8-4f6a-9b34-9cc85d8f8ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763846847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1763846847
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3776088947
Short name T501
Test name
Test status
Simulation time 4620561426 ps
CPU time 10.25 seconds
Started Mar 05 12:44:58 PM PST 24
Finished Mar 05 12:45:08 PM PST 24
Peak memory 201040 kb
Host smart-6fc4b24c-866a-4f1e-bdac-01607d7900eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776088947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3776088947
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.410709729
Short name T772
Test name
Test status
Simulation time 6080192547 ps
CPU time 15.39 seconds
Started Mar 05 12:45:18 PM PST 24
Finished Mar 05 12:45:33 PM PST 24
Peak memory 200976 kb
Host smart-6990699a-a697-46eb-85d9-1679659a0e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410709729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.410709729
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2947917271
Short name T196
Test name
Test status
Simulation time 248586855635 ps
CPU time 349.8 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:50:51 PM PST 24
Peak memory 209684 kb
Host smart-2459b3a5-346f-4d23-87ea-918406d6447e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947917271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2947917271
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3978335863
Short name T190
Test name
Test status
Simulation time 257603101244 ps
CPU time 84.7 seconds
Started Mar 05 12:44:52 PM PST 24
Finished Mar 05 12:46:17 PM PST 24
Peak memory 209472 kb
Host smart-5f0490b6-c2f6-467f-9c78-5d679d9ad2ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978335863 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3978335863
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2866830845
Short name T413
Test name
Test status
Simulation time 410140904 ps
CPU time 1.63 seconds
Started Mar 05 12:44:58 PM PST 24
Finished Mar 05 12:45:00 PM PST 24
Peak memory 200924 kb
Host smart-cad87443-dce1-4901-956f-d4e0ad7165d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866830845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2866830845
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.4189905998
Short name T618
Test name
Test status
Simulation time 487035047325 ps
CPU time 173.13 seconds
Started Mar 05 12:44:52 PM PST 24
Finished Mar 05 12:47:45 PM PST 24
Peak memory 201240 kb
Host smart-1f66db18-630e-423c-b58c-9a5c2a72e6cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189905998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.4189905998
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3990765171
Short name T621
Test name
Test status
Simulation time 167551028275 ps
CPU time 378.68 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:51:31 PM PST 24
Peak memory 201200 kb
Host smart-de04d5dd-cd43-43d6-b442-d5822462ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990765171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3990765171
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.4232791806
Short name T590
Test name
Test status
Simulation time 489419970075 ps
CPU time 1204.2 seconds
Started Mar 05 12:45:14 PM PST 24
Finished Mar 05 01:05:19 PM PST 24
Peak memory 201196 kb
Host smart-9487ff1d-3258-4c37-97fb-af5852658a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232791806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.4232791806
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2452309565
Short name T521
Test name
Test status
Simulation time 490630116098 ps
CPU time 1136.71 seconds
Started Mar 05 12:45:00 PM PST 24
Finished Mar 05 01:03:57 PM PST 24
Peak memory 201184 kb
Host smart-e5e6b108-ad69-4244-8c66-c5fa5d47ad77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452309565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2452309565
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2280589944
Short name T321
Test name
Test status
Simulation time 160399629326 ps
CPU time 349.95 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:51:01 PM PST 24
Peak memory 201080 kb
Host smart-c95ed498-7f2c-4a5c-86fd-df6e86b9b7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280589944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2280589944
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3119238095
Short name T71
Test name
Test status
Simulation time 485610206005 ps
CPU time 673.07 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 12:56:19 PM PST 24
Peak memory 201116 kb
Host smart-3a1d4075-baa5-436c-bbde-8527fd105168
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119238095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3119238095
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3127577240
Short name T493
Test name
Test status
Simulation time 516998095866 ps
CPU time 596.9 seconds
Started Mar 05 12:45:18 PM PST 24
Finished Mar 05 12:55:15 PM PST 24
Peak memory 201280 kb
Host smart-09077661-ea24-4809-ae4a-ab57909bfda2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127577240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3127577240
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3066408125
Short name T719
Test name
Test status
Simulation time 162812003677 ps
CPU time 405.18 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:51:55 PM PST 24
Peak memory 201124 kb
Host smart-7a4a6a53-a735-416b-b929-143b3e26a239
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066408125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3066408125
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.673649420
Short name T331
Test name
Test status
Simulation time 115189686691 ps
CPU time 662.41 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:56:13 PM PST 24
Peak memory 201568 kb
Host smart-50c73bd5-ab8b-4dfc-9411-ec7757b8fc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673649420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.673649420
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2481064062
Short name T601
Test name
Test status
Simulation time 38934720531 ps
CPU time 11.42 seconds
Started Mar 05 12:45:04 PM PST 24
Finished Mar 05 12:45:15 PM PST 24
Peak memory 201036 kb
Host smart-3c5c04f3-0da1-4193-b967-51b8a270782a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481064062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2481064062
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.315679383
Short name T370
Test name
Test status
Simulation time 3302025960 ps
CPU time 8.11 seconds
Started Mar 05 12:45:02 PM PST 24
Finished Mar 05 12:45:11 PM PST 24
Peak memory 200904 kb
Host smart-34fa44f6-d7cc-49f7-b771-ec74ed07244f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315679383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.315679383
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2975886232
Short name T732
Test name
Test status
Simulation time 5845664215 ps
CPU time 14.01 seconds
Started Mar 05 12:44:42 PM PST 24
Finished Mar 05 12:44:57 PM PST 24
Peak memory 200948 kb
Host smart-44c986dd-ab14-4fa0-b359-15e8cc131f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975886232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2975886232
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.44349540
Short name T256
Test name
Test status
Simulation time 328823948533 ps
CPU time 191.13 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:48:22 PM PST 24
Peak memory 201192 kb
Host smart-307c523a-2638-4c12-9a2f-7f2233f5eccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44349540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.44349540
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.3031727962
Short name T257
Test name
Test status
Simulation time 73298361769 ps
CPU time 153.42 seconds
Started Mar 05 12:44:56 PM PST 24
Finished Mar 05 12:47:29 PM PST 24
Peak memory 209788 kb
Host smart-ea84f4b8-7f63-4e8e-a578-918377baded8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031727962 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.3031727962
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.318824806
Short name T384
Test name
Test status
Simulation time 516753871 ps
CPU time 0.94 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:45:10 PM PST 24
Peak memory 200896 kb
Host smart-853f6f0e-4315-4d0f-a04d-1c434d7e6da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318824806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.318824806
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.4156351101
Short name T309
Test name
Test status
Simulation time 337932730937 ps
CPU time 442.96 seconds
Started Mar 05 12:45:08 PM PST 24
Finished Mar 05 12:52:31 PM PST 24
Peak memory 201156 kb
Host smart-242ec81f-e238-43f8-9119-c24cff555a47
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156351101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.4156351101
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.340125967
Short name T254
Test name
Test status
Simulation time 327944527148 ps
CPU time 389.45 seconds
Started Mar 05 12:45:04 PM PST 24
Finished Mar 05 12:51:34 PM PST 24
Peak memory 201140 kb
Host smart-566ed603-3f09-4ea8-a893-6577a1b53ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340125967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.340125967
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.684140427
Short name T198
Test name
Test status
Simulation time 495873831285 ps
CPU time 1223.37 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 01:05:33 PM PST 24
Peak memory 201132 kb
Host smart-b5a4870f-eb10-4223-9a71-2f3bb5fe47e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684140427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.684140427
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3198680051
Short name T576
Test name
Test status
Simulation time 167569215147 ps
CPU time 96.19 seconds
Started Mar 05 12:44:57 PM PST 24
Finished Mar 05 12:46:33 PM PST 24
Peak memory 201068 kb
Host smart-363c0f16-71da-45e0-a8ae-001f09869e9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198680051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3198680051
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3912877519
Short name T149
Test name
Test status
Simulation time 161702787446 ps
CPU time 192.4 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:48:23 PM PST 24
Peak memory 201196 kb
Host smart-90141760-b962-4e62-b89b-774a0a361bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912877519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3912877519
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.4087702951
Short name T478
Test name
Test status
Simulation time 493001485406 ps
CPU time 1145.99 seconds
Started Mar 05 12:45:02 PM PST 24
Finished Mar 05 01:04:08 PM PST 24
Peak memory 201076 kb
Host smart-9363c473-521e-44c6-86d0-d36bddda16db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087702951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.4087702951
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3758545511
Short name T182
Test name
Test status
Simulation time 488510015689 ps
CPU time 219.16 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:48:59 PM PST 24
Peak memory 201108 kb
Host smart-a293d5ed-86be-4320-aaf2-ff4a5d05547a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758545511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3758545511
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1716567550
Short name T426
Test name
Test status
Simulation time 158022816811 ps
CPU time 75.74 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:46:17 PM PST 24
Peak memory 201072 kb
Host smart-e2553c42-5694-467b-a863-0c561e5be7a8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716567550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1716567550
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3661559798
Short name T9
Test name
Test status
Simulation time 41815092711 ps
CPU time 11.65 seconds
Started Mar 05 12:44:56 PM PST 24
Finished Mar 05 12:45:07 PM PST 24
Peak memory 201060 kb
Host smart-00772cf4-39c1-4647-98c3-00349553b010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661559798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3661559798
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1664450369
Short name T614
Test name
Test status
Simulation time 4768441779 ps
CPU time 3.54 seconds
Started Mar 05 12:44:53 PM PST 24
Finished Mar 05 12:44:57 PM PST 24
Peak memory 201064 kb
Host smart-2bf8b4a3-ff6b-4366-86cd-ecf31f0826ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664450369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1664450369
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3502816167
Short name T657
Test name
Test status
Simulation time 5724749867 ps
CPU time 14.61 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 12:45:14 PM PST 24
Peak memory 201004 kb
Host smart-8ca21f0f-8dd5-4e00-b1aa-095b8ef0ae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502816167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3502816167
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1041628481
Short name T116
Test name
Test status
Simulation time 171671665190 ps
CPU time 184.82 seconds
Started Mar 05 12:45:13 PM PST 24
Finished Mar 05 12:48:18 PM PST 24
Peak memory 201176 kb
Host smart-53cc697f-e4f0-4811-9189-6d844c3d55e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041628481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1041628481
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3811093074
Short name T397
Test name
Test status
Simulation time 282239129 ps
CPU time 1.25 seconds
Started Mar 05 12:45:03 PM PST 24
Finished Mar 05 12:45:05 PM PST 24
Peak memory 200844 kb
Host smart-dec0bc7f-41c9-4086-8637-d00af5b15120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811093074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3811093074
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.3933753298
Short name T49
Test name
Test status
Simulation time 164306962883 ps
CPU time 65.25 seconds
Started Mar 05 12:45:08 PM PST 24
Finished Mar 05 12:46:13 PM PST 24
Peak memory 201140 kb
Host smart-4f306955-311a-413a-bd18-1c7bc8de1366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933753298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.3933753298
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2303190958
Short name T681
Test name
Test status
Simulation time 165504005204 ps
CPU time 100.38 seconds
Started Mar 05 12:45:02 PM PST 24
Finished Mar 05 12:46:42 PM PST 24
Peak memory 201192 kb
Host smart-2a736d06-0180-431e-8c00-cd59c4bce8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303190958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2303190958
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.160528081
Short name T475
Test name
Test status
Simulation time 165428268977 ps
CPU time 101 seconds
Started Mar 05 12:44:54 PM PST 24
Finished Mar 05 12:46:35 PM PST 24
Peak memory 201124 kb
Host smart-86c1e7f2-6196-467d-8d4a-0b88e68ce163
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=160528081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.160528081
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2545749397
Short name T685
Test name
Test status
Simulation time 489431742910 ps
CPU time 1167.36 seconds
Started Mar 05 12:44:59 PM PST 24
Finished Mar 05 01:04:27 PM PST 24
Peak memory 201196 kb
Host smart-c531dc96-d45a-475f-995a-9e57bee48c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545749397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2545749397
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.1564189032
Short name T698
Test name
Test status
Simulation time 163451052643 ps
CPU time 43.39 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:46:04 PM PST 24
Peak memory 201104 kb
Host smart-96f477b9-8290-47d8-a5fa-c3b29ac1808f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564189032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.1564189032
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2351298155
Short name T654
Test name
Test status
Simulation time 168876317223 ps
CPU time 96.27 seconds
Started Mar 05 12:45:22 PM PST 24
Finished Mar 05 12:46:59 PM PST 24
Peak memory 201064 kb
Host smart-1dd8abff-6619-447c-9d7d-dde781498941
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351298155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2351298155
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3093264057
Short name T420
Test name
Test status
Simulation time 490614443423 ps
CPU time 1129.27 seconds
Started Mar 05 12:45:03 PM PST 24
Finished Mar 05 01:03:53 PM PST 24
Peak memory 201060 kb
Host smart-f7b4648f-fb53-4ee6-893c-2bbafacb805e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093264057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3093264057
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1873815874
Short name T341
Test name
Test status
Simulation time 71954395022 ps
CPU time 258.51 seconds
Started Mar 05 12:45:11 PM PST 24
Finished Mar 05 12:49:30 PM PST 24
Peak memory 201508 kb
Host smart-642334ed-8cac-4993-b367-e045351ecbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873815874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1873815874
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1177996218
Short name T176
Test name
Test status
Simulation time 32596369818 ps
CPU time 7.63 seconds
Started Mar 05 12:45:04 PM PST 24
Finished Mar 05 12:45:12 PM PST 24
Peak memory 201060 kb
Host smart-f2bba727-8a5e-4c5f-8991-0fb675a7980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177996218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1177996218
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2956098872
Short name T407
Test name
Test status
Simulation time 3125734395 ps
CPU time 7.94 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 12:45:13 PM PST 24
Peak memory 200992 kb
Host smart-1ed4e7ca-9634-46e2-8811-95bfb175779a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956098872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2956098872
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1198344299
Short name T111
Test name
Test status
Simulation time 6063403124 ps
CPU time 4.05 seconds
Started Mar 05 12:45:01 PM PST 24
Finished Mar 05 12:45:05 PM PST 24
Peak memory 200996 kb
Host smart-aad6cee7-bee4-4ddb-b5b3-717798a39e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198344299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1198344299
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3099863768
Short name T294
Test name
Test status
Simulation time 261572819803 ps
CPU time 342.02 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:50:54 PM PST 24
Peak memory 201704 kb
Host smart-36877ed2-315b-41d3-815f-ffd77d525cff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099863768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3099863768
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3813645470
Short name T185
Test name
Test status
Simulation time 27741346264 ps
CPU time 67.68 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 12:46:13 PM PST 24
Peak memory 209888 kb
Host smart-89aa7904-13d1-4ee8-97c0-79eef0af5556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813645470 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3813645470
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2432856590
Short name T430
Test name
Test status
Simulation time 413748040 ps
CPU time 1.05 seconds
Started Mar 05 12:44:54 PM PST 24
Finished Mar 05 12:44:55 PM PST 24
Peak memory 200876 kb
Host smart-b5f031a7-f450-4bc3-9958-55e17758c555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432856590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2432856590
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.1145058400
Short name T161
Test name
Test status
Simulation time 505694312661 ps
CPU time 185.01 seconds
Started Mar 05 12:45:02 PM PST 24
Finished Mar 05 12:48:08 PM PST 24
Peak memory 201332 kb
Host smart-19f0d0e6-e8c6-40d3-89cc-1c7e64867072
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145058400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.1145058400
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1159772982
Short name T500
Test name
Test status
Simulation time 171031259385 ps
CPU time 101.69 seconds
Started Mar 05 12:45:12 PM PST 24
Finished Mar 05 12:46:54 PM PST 24
Peak memory 201200 kb
Host smart-a5faa869-236c-40d4-b272-50f17aae534e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159772982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1159772982
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1459802761
Short name T250
Test name
Test status
Simulation time 497735457936 ps
CPU time 1187.14 seconds
Started Mar 05 12:45:05 PM PST 24
Finished Mar 05 01:04:58 PM PST 24
Peak memory 201088 kb
Host smart-94ebc4f5-084e-4bdc-8428-3a3b06c49a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459802761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1459802761
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1578727156
Short name T150
Test name
Test status
Simulation time 499653912483 ps
CPU time 198.53 seconds
Started Mar 05 12:45:03 PM PST 24
Finished Mar 05 12:48:21 PM PST 24
Peak memory 201068 kb
Host smart-4eae3def-5157-4763-84f4-e909d65389d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578727156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1578727156
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3459601534
Short name T613
Test name
Test status
Simulation time 323943117532 ps
CPU time 821.32 seconds
Started Mar 05 12:45:07 PM PST 24
Finished Mar 05 12:58:49 PM PST 24
Peak memory 201064 kb
Host smart-2061d761-a40e-41e4-b26a-b9e2ab97ae2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459601534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3459601534
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.603124322
Short name T267
Test name
Test status
Simulation time 161884033296 ps
CPU time 92.87 seconds
Started Mar 05 12:45:06 PM PST 24
Finished Mar 05 12:46:39 PM PST 24
Peak memory 201144 kb
Host smart-024049b0-3766-44af-8d17-3e350c7a12c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603124322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.603124322
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2585024969
Short name T625
Test name
Test status
Simulation time 491547737117 ps
CPU time 214.11 seconds
Started Mar 05 12:45:09 PM PST 24
Finished Mar 05 12:48:44 PM PST 24
Peak memory 201032 kb
Host smart-51afb69b-1214-4624-ae65-5d4ee6d34410
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585024969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2585024969
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.2978149009
Short name T340
Test name
Test status
Simulation time 137757251245 ps
CPU time 445.6 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:52:46 PM PST 24
Peak memory 201512 kb
Host smart-e5118b5f-bf9c-43fb-8d89-2fd555dfd108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978149009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.2978149009
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.307664181
Short name T651
Test name
Test status
Simulation time 30178776269 ps
CPU time 69.24 seconds
Started Mar 05 12:44:55 PM PST 24
Finished Mar 05 12:46:05 PM PST 24
Peak memory 201064 kb
Host smart-2ce2de36-42ff-417d-9a4d-5c249644841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307664181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.307664181
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3192560058
Short name T491
Test name
Test status
Simulation time 3778776059 ps
CPU time 1.6 seconds
Started Mar 05 12:45:08 PM PST 24
Finished Mar 05 12:45:09 PM PST 24
Peak memory 201004 kb
Host smart-85850443-20f4-4126-8b81-98b4db9d5d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192560058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3192560058
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2237622433
Short name T388
Test name
Test status
Simulation time 5975244929 ps
CPU time 4.48 seconds
Started Mar 05 12:45:10 PM PST 24
Finished Mar 05 12:45:14 PM PST 24
Peak memory 201052 kb
Host smart-79630f61-77af-4a9d-a900-f6eaf9f0bab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237622433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2237622433
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3597715246
Short name T709
Test name
Test status
Simulation time 196454340147 ps
CPU time 93.26 seconds
Started Mar 05 12:45:20 PM PST 24
Finished Mar 05 12:46:53 PM PST 24
Peak memory 201200 kb
Host smart-8e9a92bb-b358-490d-87e3-01ede7bd2c26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597715246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3597715246
Directory /workspace/9.adc_ctrl_stress_all/latest
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