Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7300	1			T1	20		T3	81		T8	58
testmodes[AdcCtrlTestmodeNormal]	5545	1			T3	42		T7	2		T8	30
testmodes[AdcCtrlTestmodeLowpower]	5987	1			T2	19		T3	29		T4	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4024	1			T1	19		T3	61		T8	37
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1770	1			T3	14		T8	13		T37	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1399	1			T3	6		T8	8		T39	20
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1756	1			T3	13		T8	12		T118	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2011	1			T3	18		T7	1		T8	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1445	1			T3	10		T8	6		T37	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1408	1			T3	7		T8	9		T37	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1438	1			T3	10		T8	4		T39	25
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2891	1			T2	18		T3	12		T4	2