Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23456

1

T1

20

T2

19

T3

158

auto[ADC_CTRL_FILTER_COND_OUT]

3531

1

T3

20

T4

4

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20754

1

T1

20

T2

19

T3

148

auto[1]

6233

1

T3

30

T5

11

T6

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	479	1			T3	11		T8	4		T39	11
values[0]	126	1			T189	19		T190	19		T191	32
values[1]	617	1			T4	4		T38	12		T151	1
values[2]	2802	1			T4	14		T7	2		T9	27
values[3]	708	1			T3	19		T5	11		T8	3
values[4]	710	1			T11	12		T38	9		T123	14
values[5]	666	1			T3	1		T121	1		T38	13
values[6]	468	1			T12	1		T26	13		T37	8
values[7]	581	1			T12	1		T23	28		T37	3
values[8]	899	1			T4	13		T8	14		T26	6
values[9]	1477	1			T3	8		T6	18		T11	2
minimum	17454	1			T1	20		T2	19		T3	139

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	978	1			T4	4		T38	12		T151	1
values[1]	2740	1			T3	19		T4	14		T5	11
values[2]	576	1			T38	9		T129	28		T125	30
values[3]	825	1			T8	3		T11	12		T123	14
values[4]	645	1			T121	1		T120	13		T30	3
values[5]	460	1			T3	1		T12	1		T23	10
values[6]	615	1			T12	1		T23	18		T26	6
values[7]	910	1			T3	8		T4	13		T8	14
values[8]	1111	1			T6	18		T24	2		T136	11
values[9]	165	1			T11	2		T172	7		T27	1
minimum	17962	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T151	1		T129	16		T144	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T4	4		T38	12		T130	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1493	1			T4	14		T5	11		T7	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	11		T23	11		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T38	9		T125	15		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T129	15		T131	14		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	1		T123	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	2		T11	1		T129	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T121	1		T140	1		T117	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T120	1		T30	1		T123	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T23	10		T38	13		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	1		T12	1		T26	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T12	1		T26	6		T125	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T23	18		T37	2		T48	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T3	4		T4	13		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	8		T139	5		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T24	1		T136	1		T117	31
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T6	18		T24	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T11	1		T27	1		T13	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T172	2		T192	1		T150	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17822	1			T1	20		T2	19		T3	147
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T129	4		T131	2		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T130	13		T193	2		T175	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T166	7		T156	13		T157	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T3	8		T31	1		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T125	15		T187	11		T194	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T129	13		T131	12		T187	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	2		T123	13		T34	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	1		T11	8		T129	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T44	2		T195	15		T196	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T120	12		T30	2		T123	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T31	2		T42	2		T35	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T37	7		T31	7		T152	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T125	12		T43	11		T197	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T37	1		T48	10		T165	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	4		T30	2		T130	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	6		T36	14		T198	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T136	10		T117	24		T32	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T120	11		T123	12		T199	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T11	1		T200	3		T201	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T172	5		T150	13		T202	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	3		T31	3		T165	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	479	1			T3	11		T8	4		T39	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T189	15		T203	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T190	3		T191	16		T204	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T151	1		T205	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T4	4		T38	12		T130	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T4	14		T7	2		T9	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T23	11		T31	3		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T5	11		T155	1		T172	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	11		T8	2		T48	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	1		T38	9		T123	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	1		T129	26		T32	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T121	1		T38	13		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	1		T120	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T139	10		T117	2		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T26	13		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	1		T23	10		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T23	18		T37	2		T48	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T4	13		T26	6		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	8		T139	5		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T3	4		T11	1		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T6	18		T24	1		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17332	1			T1	20		T2	19		T3	136
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T189	4		T203	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T190	16		T191	16		T206	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T199	7		T94	9		T207	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T130	13		T193	2		T175	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T166	7		T156	13		T157	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T31	1		T127	13		T208	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T172	13		T125	15		T187	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	8		T8	1		T48	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	2		T123	13		T194	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	8		T129	24		T32	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T44	2		T34	1		T35	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T120	12		T30	2		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T42	2		T195	15		T209	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T37	7		T31	7		T123	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T31	2		T43	11		T127	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T37	1		T48	10		T152	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T136	10		T30	2		T125	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T8	6		T165	8		T198	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T3	4		T11	1		T117	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	400	1			T120	11		T123	12		T172	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T151	1		T129	5		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T4	1		T38	1		T130	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T4	1		T5	1		T7	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	11		T23	1		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T38	1		T125	16		T187	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T129	14		T131	13		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	3		T123	14		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T8	2		T11	9		T129	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T121	1		T140	1		T117	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T120	13		T30	3		T123	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T23	1		T38	1		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	1		T12	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T26	1		T125	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T23	1		T37	2		T48	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	5		T4	1		T30	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T8	11		T139	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T24	1		T136	11		T117	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T6	1		T24	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T11	2		T27	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T172	6		T192	1		T150	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17952	1			T1	20		T2	19		T3	150
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T129	15		T144	13		T131	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T4	3		T38	11		T153	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T4	13		T5	10		T9	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T3	8		T23	10		T31	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T38	8		T125	14		T194	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T129	14		T131	13		T194	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T194	10		T210	8		T159	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	1		T129	10		T32	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T117	1		T171	12		T195	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T48	6		T172	7		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T23	9		T38	12		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T26	12		T31	9		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T26	5		T125	8		T159	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T23	17		T37	1		T48	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	3		T4	12		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T8	3		T139	4		T15	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T117	29		T32	2		T212	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T6	17		T120	9		T199	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T13	4		T200	2		T213	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T172	1		T150	10		T202	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T204	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	479	1			T3	11		T8	4		T39	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T189	5		T203	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T190	17		T191	17		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T151	1		T205	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	1		T38	1		T130	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T4	1		T7	2		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T23	1		T31	3		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	1		T155	1		T172	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	11		T8	2		T48	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	3		T38	1		T123	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	9		T129	26		T32	27
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T121	1		T38	1		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	1		T120	13		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T139	1		T117	1		T42	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T12	1		T26	1		T37	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	1		T23	1		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T23	1		T37	2		T48	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	1		T26	1		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T8	11		T139	1		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	387	1			T3	5		T11	2		T24	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	469	1			T6	1		T24	1		T122	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17454	1			T1	20		T2	19		T3	139
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T189	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T190	2		T191	15		T204	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T199	10		T214	13		T215	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	3		T38	11		T193	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T4	13		T9	25		T170	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T23	10		T31	1		T153	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	10		T172	16		T125	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	8		T8	1		T48	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T38	8		T194	10		T210	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T129	24		T32	13		T210	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T38	12		T171	12		T35	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T172	7		T34	1		T216	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T139	9		T117	1		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T26	12		T31	9		T48	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T23	9		T31	1		T159	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T23	17		T37	1		T48	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T4	12		T26	5		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	3		T139	4		T217	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T3	3		T117	29		T32	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T6	17		T120	9		T172	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

auto[0]

4071

1

T3

11

T4

28

T5

10

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26987

1

T1

20

T2

19

T3

178

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23537

1

T1

20

T2

19

T3

151

auto[ADC_CTRL_FILTER_COND_OUT]

3450

1

T3

27

T4

13

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21197

1

T1

20

T2

19

T3

178

auto[1]

5790

1

T4

27

T6

18

T7

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22903

1

T1

20

T2

19

T3

163

auto[1]

4084

1

T3

15

T8

7

T11

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T37	3		T187	11		T218	9
values[0]	129	1			T210	21		T219	26		T178	23
values[1]	688	1			T23	21		T24	1		T120	13
values[2]	630	1			T171	13		T183	1		T131	26
values[3]	607	1			T3	19		T11	3		T12	1
values[4]	626	1			T3	8		T6	18		T12	1
values[5]	750	1			T24	1		T26	13		T122	1
values[6]	661	1			T4	13		T121	1		T38	9
values[7]	703	1			T11	2		T38	12		T117	2
values[8]	819	1			T3	1		T4	18		T8	17
values[9]	3419	1			T5	11		T7	2		T9	27
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	998	1			T23	21		T24	1		T120	13
values[1]	632	1			T3	19		T23	18		T171	13
values[2]	548	1			T6	18		T11	3		T12	1
values[3]	641	1			T12	1		T24	2		T151	1
values[4]	812	1			T3	8		T26	13		T122	1
values[5]	681	1			T4	13		T11	2		T121	1
values[6]	2882	1			T4	4		T7	2		T8	14
values[7]	854	1			T3	1		T4	14		T5	11
values[8]	803	1			T11	9		T37	8		T139	10
values[9]	204	1			T37	3		T171	14		T187	12
minimum	17932	1			T1	20		T2	19		T3	150

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22916

1

T1

20

T2

19

T3

167

auto[1]

4071

1

T3

11

T4

28

T5

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T23	21		T120	1		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T24	1		T31	12		T117	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T23	18		T171	13		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	11		T130	1		T183	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	1		T26	6		T38	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	18		T11	1		T30	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T151	1		T144	14		T205	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T24	2		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T26	13		T155	1		T129	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T3	4		T122	1		T38	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	1		T117	2		T186	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T4	13		T121	1		T165	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1457	1			T4	4		T7	2		T9	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	8		T123	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T3	1		T4	14		T5	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	2		T140	1		T48	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T37	1		T129	11		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T139	10		T125	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T37	2		T171	14		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T212	4		T220	7		T164	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T120	12		T165	8		T172	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T31	7		T117	13		T158	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T41	13		T34	1		T199	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	8		T131	12		T194	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T44	2		T35	4		T127	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	2		T30	2		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T42	2		T217	10		T221	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T123	12		T125	17		T211	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T129	13		T131	5		T198	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	4		T31	1		T48	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	1		T197	6		T92	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T32	5		T33	1		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T166	7		T156	13		T157	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	6		T123	7		T130	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T136	10		T120	11		T30	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T8	1		T48	9		T194	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T37	7		T129	11		T187	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	8		T125	12		T131	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T37	1		T187	11		T201	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T212	4		T220	7		T164	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T37	2		T187	1		T218	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T219	13		T179	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T210	9		T178	13		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T23	21		T120	1		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T24	1		T31	12		T117	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T171	13		T199	11		T36	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T183	1		T131	14		T199	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	1		T23	18		T26	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	11		T11	1		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T151	1		T44	1		T42	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	4		T6	18		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T26	13		T155	1		T144	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T24	1		T122	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T129	15		T186	3		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	13		T121	1		T38	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	1		T38	12		T117	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T123	1		T130	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T3	1		T4	18		T136	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	10		T48	7		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T5	11		T7	2		T9	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T11	1		T139	10		T140	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17810	1			T1	20		T2	19		T3	147
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T37	1		T187	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T219	13		T179	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T210	12		T178	10		T222	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T120	12		T165	8		T172	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T31	7		T117	13		T158	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T199	7		T36	14		T200	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T131	12		T199	12		T194	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T34	1		T35	4		T127	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	8		T11	2		T31	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T44	2		T42	2		T221	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	4		T30	2		T117	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T131	5		T207	4		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T31	1		T48	10		T172	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T129	13		T92	13		T198	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T48	2		T32	5		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	1		T127	11		T195	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T123	7		T130	13		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	10		T120	11		T130	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	7		T48	9		T43	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1139	1			T37	7		T166	7		T30	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T11	8		T125	12		T131	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	3		T31	3		T165	1